Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870253
Voravit Vorapipat, Cooper S. Levy, P. Asbeck
In modern communication, wideband and high-spectral-efficiency modulation results in high peak-to-average power ratio (PAPR), up to 8 to 10dB. Well-known PA-efficiency-enhancement techniques, such as Doherty and outphasing, offer reduced efficiency improvement beyond 6dB back-off, limiting the efficiency enhancement obtainable with high PAPR modulation. Recent works have shown that a combination of different techniques [1–3] can result in improved efficiency well beyond 6dB back-off. However, these combined techniques have come at a cost of glitches due to mode-transitions, when power supply voltage or load impedance undergo large variations at critical power levels. In [1,2] switching between power supply voltages causes significant glitches, which degrade the EVM and ACPR of the transmitted signal. In [1], reasonable EVM is achieved, by reducing the average output power so that power supply switching is less frequent. A “skipping window” technique is proposed in [3] to skip high-frequency mode-transitions reducing overall glitching. While this improves the ACPR, the efficiency is degraded since there is no enhancement during a skipped transition.
{"title":"2.8 A Class-G voltage-mode Doherty power amplifier","authors":"Voravit Vorapipat, Cooper S. Levy, P. Asbeck","doi":"10.1109/ISSCC.2017.7870253","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870253","url":null,"abstract":"In modern communication, wideband and high-spectral-efficiency modulation results in high peak-to-average power ratio (PAPR), up to 8 to 10dB. Well-known PA-efficiency-enhancement techniques, such as Doherty and outphasing, offer reduced efficiency improvement beyond 6dB back-off, limiting the efficiency enhancement obtainable with high PAPR modulation. Recent works have shown that a combination of different techniques [1–3] can result in improved efficiency well beyond 6dB back-off. However, these combined techniques have come at a cost of glitches due to mode-transitions, when power supply voltage or load impedance undergo large variations at critical power levels. In [1,2] switching between power supply voltages causes significant glitches, which degrade the EVM and ACPR of the transmitted signal. In [1], reasonable EVM is achieved, by reducing the average output power so that power supply switching is less frequent. A “skipping window” technique is proposed in [3] to skip high-frequency mode-transitions reducing overall glitching. While this improves the ACPR, the efficiency is degraded since there is no enhancement during a skipped transition.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121704780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870385
Hossein Jalili, O. Momeni
Fully integrated implementation of mm-wave/THz radiators and phased arrays presents new potentials for applications like spectroscopy, imaging, and high data-rate communication. These applications demand sufficient radiated power, wide frequency range, and variable phase shifting between sources to perform beam steering. Limited power generation capability of transistors close to the maximum oscillation frequency (fmax) of available silicon processes in addition to the poor quality factor of varactors makes realizing these requirements particularly challenging. Harmonic oscillators are often coupled together in arrays to boost the output power and steer the radiation beam [1–6]. The coupling elements along with varactors used for frequency tuning add loss and parasitics to the circuit and significantly reduce the output power, operation frequency, and tuning range at mm-wave/THz frequencies. In this work, we implemented a standing-wave (SW) structure that overcomes these challenges to achieve broadband frequency tuning, wide beam steering and high power radiation at the same time.
{"title":"17.10 A 318-to-370GHz standing-wave 2D phased array in 0.13µm BiCMOS","authors":"Hossein Jalili, O. Momeni","doi":"10.1109/ISSCC.2017.7870385","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870385","url":null,"abstract":"Fully integrated implementation of mm-wave/THz radiators and phased arrays presents new potentials for applications like spectroscopy, imaging, and high data-rate communication. These applications demand sufficient radiated power, wide frequency range, and variable phase shifting between sources to perform beam steering. Limited power generation capability of transistors close to the maximum oscillation frequency (fmax) of available silicon processes in addition to the poor quality factor of varactors makes realizing these requirements particularly challenging. Harmonic oscillators are often coupled together in arrays to boost the output power and steer the radiation beam [1–6]. The coupling elements along with varactors used for frequency tuning add loss and parasitics to the circuit and significantly reduce the output power, operation frequency, and tuning range at mm-wave/THz frequencies. In this work, we implemented a standing-wave (SW) structure that overcomes these challenges to achieve broadband frequency tuning, wide beam steering and high power radiation at the same time.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870283
Fan Yang, P. Mok
Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific minimum supply voltages. Point-of-load low-dropout regulators (LDOs) are used to power these modules as per the required applications, from a global supply rail Vdd. The global Vdd is noisy and can be varied within a wide range, which adds to the difficulty of designing LDOs in such applications.
{"title":"5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over −20dB PSR at 0.2V lowest supply voltage","authors":"Fan Yang, P. Mok","doi":"10.1109/ISSCC.2017.7870283","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870283","url":null,"abstract":"Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific minimum supply voltages. Point-of-load low-dropout regulators (LDOs) are used to power these modules as per the required applications, from a global supply rail Vdd. The global Vdd is noisy and can be varied within a wide range, which adds to the difficulty of designing LDOs in such applications.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130424541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870430
Il-Min Yi, Min-Kyun Chae, S. Hyun, Seung-Jun Bae, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park
Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate that can be handled by the receiver (RX); the maximum data rate reported is below 10Gb/s with a supply voltage of 0.8V in 65nm CMOS [2-4]. In a conventional RX at a low-supply voltage, the maximum data rate is limited by the small gm/C of the RX front-end circuit. To eliminate this gm/C constraint, this work proposes a time-based RX for 12Gb/s operation at 0.8V.
{"title":"23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS","authors":"Il-Min Yi, Min-Kyun Chae, S. Hyun, Seung-Jun Bae, J. Choi, Seong-Jin Jang, Byungsub Kim, J. Sim, Hong-June Park","doi":"10.1109/ISSCC.2017.7870430","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870430","url":null,"abstract":"Single-ended transceivers are mostly used for DRAM interfaces to reduce pin count. A low-supply transceiver is preferred, especially for mobile DRAM interfaces, for low-power consumption while maintaining a high-speed interface for transmission of image data [1]. To reduce transmitter power in single-ended transceivers, both the supply voltage and the signal swing are reduced: 0.8V and 200mV, or below [2]. However, with a small signal swing the low-supply voltage limits the maximum data rate that can be handled by the receiver (RX); the maximum data rate reported is below 10Gb/s with a supply voltage of 0.8V in 65nm CMOS [2-4]. In a conventional RX at a low-supply voltage, the maximum data rate is limited by the small gm/C of the RX front-end circuit. To eliminate this gm/C constraint, this work proposes a time-based RX for 12Gb/s operation at 0.8V.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124671259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870349
A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.
{"title":"14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems","authors":"","doi":"10.1109/ISSCC.2017.7870349","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870349","url":null,"abstract":"A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116517869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870297
D. Lachartre, F. Dehmas, C. Bernier, C. Fourtet, L. Ouvry, F. Lepin, E. Mercier, S. Hamard, Lionel Zirphile, S. Thuries, F. Chaix
Ultra-narrow-band (UNB) signaling is an enabling technology for low-power wide-area (LPWA) networks for the “Internet-of-Things”. Indeed, UNB signaling, based on spectrally efficient modulations such as DBPSK, simultaneously optimizes network capacity while maximizing the communication link budget. However, UNB signaling poses many technical challenges. In the receiver, carrier frequency offsets (CFO) can shift the desired signal from the expected channel. In the transmitter, the difficulty resides in generating the modulated signal with the required spectral purity. This work presents an 850-to-920 MHz RF transceiver dedicated to UNB communication systems employing the DBPSK/GFSK modulations. The receiver is resistant to CFO offsets and drifts of ±75Hz (i.e. 150% of the 100Hz channel) and 35Hz/s, respectively, with only 1dB sensitivity loss, thus allowing the circuit to function without a TCXO. In DBPSK 100b/s transmission mode, an error vector magnitude (EVM) better than 5% is measured for output powers up to 10dBm.
{"title":"7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks","authors":"D. Lachartre, F. Dehmas, C. Bernier, C. Fourtet, L. Ouvry, F. Lepin, E. Mercier, S. Hamard, Lionel Zirphile, S. Thuries, F. Chaix","doi":"10.1109/ISSCC.2017.7870297","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870297","url":null,"abstract":"Ultra-narrow-band (UNB) signaling is an enabling technology for low-power wide-area (LPWA) networks for the “Internet-of-Things”. Indeed, UNB signaling, based on spectrally efficient modulations such as DBPSK, simultaneously optimizes network capacity while maximizing the communication link budget. However, UNB signaling poses many technical challenges. In the receiver, carrier frequency offsets (CFO) can shift the desired signal from the expected channel. In the transmitter, the difficulty resides in generating the modulated signal with the required spectral purity. This work presents an 850-to-920 MHz RF transceiver dedicated to UNB communication systems employing the DBPSK/GFSK modulations. The receiver is resistant to CFO offsets and drifts of ±75Hz (i.e. 150% of the 100Hz channel) and 35Hz/s, respectively, with only 1dB sensitivity loss, thus allowing the circuit to function without a TCXO. In DBPSK 100b/s transmission mode, an error vector magnitude (EVM) better than 5% is measured for output powers up to 10dBm.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"2008 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120849007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870401
Mo Huang, Yan Lu, S. U, R. Martins
Low-dropout regulators (LDOs) are widely distributed in SoC designs to supply individual voltage domains, and a digital LDO (DLDO) is favorable for its low-voltage operation and process scalability. However, as many SoCs generate a load current (ILOAD) variation at sub-A/ns level, voltage regulators require a large area-consuming output capacitor (COUT) to maintain the output voltage (VOUT) during fast transients. A conventional shift-register (SR)-based DLDO [1] suffers from a power and speed trade-off, thus requires a large COUT. To break the tie and minimize COUT, [2–5] applied coarse-fine tuning and adaptive clocking, but a fast sampling clock is still necessary for instantaneous VOUT sensing. Event-driven control used in [6] reacts fast within one clock cycle, but the ADC (with 7 comparators) and the digital PI controller increase the complexity and power consumption. This work presents an analog-assisted (AA) tri-loop control scheme for transient improvement, low power, and COUT reduction.
{"title":"20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control","authors":"Mo Huang, Yan Lu, S. U, R. Martins","doi":"10.1109/ISSCC.2017.7870401","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870401","url":null,"abstract":"Low-dropout regulators (LDOs) are widely distributed in SoC designs to supply individual voltage domains, and a digital LDO (DLDO) is favorable for its low-voltage operation and process scalability. However, as many SoCs generate a load current (ILOAD) variation at sub-A/ns level, voltage regulators require a large area-consuming output capacitor (COUT) to maintain the output voltage (VOUT) during fast transients. A conventional shift-register (SR)-based DLDO [1] suffers from a power and speed trade-off, thus requires a large COUT. To break the tie and minimize COUT, [2–5] applied coarse-fine tuning and adaptive clocking, but a fast sampling clock is still necessary for instantaneous VOUT sensing. Event-driven control used in [6] reacts fast within one clock cycle, but the ADC (with 7 comparators) and the digital PI controller increase the complexity and power consumption. This work presents an analog-assisted (AA) tri-loop control scheme for transient improvement, low power, and COUT reduction.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870346
A. Passamani, D. Ponton, E. Thaller, G. Knoblinger, A. Neviani, A. Bevilacqua
In today's connected world, smaller and leaner wireless applications emerge, calling for increasingly higher integration and smaller footprint, while ensuring high reliability and operation at limited supply voltages. In this context, the integration of the power amplifier (PA) is a challenge. Wireless transmission requires Watt-level peak power, which is usually achieved by means of a dedicated external PA, although monolithic integration of the PA within the radio transceiver has recently become more and more common [1–6]. In both cases, however, a dedicated PA supply voltage is usually provided, and the PA is typically operated at a higher supply voltage than that of the digital core of the transmitter to achieve the required output power level.
{"title":"13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE","authors":"A. Passamani, D. Ponton, E. Thaller, G. Knoblinger, A. Neviani, A. Bevilacqua","doi":"10.1109/ISSCC.2017.7870346","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870346","url":null,"abstract":"In today's connected world, smaller and leaner wireless applications emerge, calling for increasingly higher integration and smaller footprint, while ensuring high reliability and operation at limited supply voltages. In this context, the integration of the power amplifier (PA) is a challenge. Wireless transmission requires Watt-level peak power, which is usually achieved by means of a dedicated external PA, although monolithic integration of the PA within the radio transceiver has recently become more and more common [1–6]. In both cases, however, a dedicated PA supply voltage is usually provided, and the PA is typically operated at a higher supply voltage than that of the digital core of the transmitter to achieve the required output power level.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127088834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870434
Yao-Hong Liu, V. Purushothaman, Chuang Lu, J. Dijkhuis, R. Staszewski, Christian Bachmann, K. Philips
We propose an ultra-low-power (ULP) and low-voltage phase-tracking RX for IoT applications. Several popular standards are defined for IoT, e.g., IEEE802.15.4 and Bluetooth Low Energy (BLE), where they envision massive numbers of interconnected sensors; however, the cost of replacing/recharging batteries can become an impediment to their massive deployment. In this work, aggressively improving the transceiver energy efficiency, lowering the supply, and simultaneously reducing the cost (die area) of the design are our primary goals. Hence, we propose a digitally-controlled oscillator (DCO)-based phase-tracking RX, which efficiently combines frequency downconversion, channel selection, carrier generation and signal demodulation, all of which lead to an ultra-low-power, low-voltage and low-cost RX.
{"title":"24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications","authors":"Yao-Hong Liu, V. Purushothaman, Chuang Lu, J. Dijkhuis, R. Staszewski, Christian Bachmann, K. Philips","doi":"10.1109/ISSCC.2017.7870434","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870434","url":null,"abstract":"We propose an ultra-low-power (ULP) and low-voltage phase-tracking RX for IoT applications. Several popular standards are defined for IoT, e.g., IEEE802.15.4 and Bluetooth Low Energy (BLE), where they envision massive numbers of interconnected sensors; however, the cost of replacing/recharging batteries can become an impediment to their massive deployment. In this work, aggressively improving the transceiver energy efficiency, lowering the supply, and simultaneously reducing the cost (die area) of the design are our primary goals. Hence, we propose a digitally-controlled oscillator (DCO)-based phase-tracking RX, which efficiently combines frequency downconversion, channel selection, carrier generation and signal demodulation, all of which lead to an ultra-low-power, low-voltage and low-cost RX.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133330437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870322
Yong-Min Ju, Se-un Shin, Yeunhee Huh, Sang-Hui Park, Jun-Suk Bang, Kiduk Kim, Sung-Won Choi, Ji-Hun Lee, G. Cho
The number of mobile device users increases every year. Each mobile device is usually equipped with a Li-ion battery having voltage that varies from a minimum of 2.7V to a maximum of 4.2V. Therefore, as the battery voltage decreases with time, a DC-DC converter is required for a regulated supply lower or higher than the battery voltage. A simple buck converter is not suited for this case, since step-up conversion is not available [1]. Instead, a non-inverting buck-boost converter can be a solution over the entire range of the battery voltage [1–4]. Many research studies related to buck-boost converters operated on Li-ion batteries set the target output voltage at around 3.4V [3,4]. Since Li-ion batteries have a wide plateau from 3.6V to 3.8V and a small energy storage below the plateau, DC-DC converters are generally operated on step-down mode at most of the battery voltage range, as shown in Fig. 10.4.1 top. Notwithstanding, step-up conversion is also required for extracting the energy below the plateau even if it is a small amount in the battery. Therefore, in DC-DC converters, it is critical to maintain high efficiency over the whole range of the battery voltage when it operates on both step-down and step-up modes to prolong the battery usage effectively. However, if the conventional buck-boost topology of Fig. 10.4.1 bottom-left is used for step-up and step-down purposes, there are always two switches (S1 and S3) conducting in the main current path through the inductor. Thus, the switches become large in size to minimize the conduction loss. As the switching loss also increases when the switch size is larger, the efficiency of this structure is usually lower than that of the simple buck (or boost) converter [1]. In this respect, this paper proposes a topology named a flying-capacitor buck-boost (FCBB) converter suitable for such an application by obtaining both step-up and step-down operations with high efficiency throughout the whole range of the battery voltage.
{"title":"10.4 A hybrid inductor-based flying-capacitor-assisted step-up/step-down DC-DC converter with 96.56% efficiency","authors":"Yong-Min Ju, Se-un Shin, Yeunhee Huh, Sang-Hui Park, Jun-Suk Bang, Kiduk Kim, Sung-Won Choi, Ji-Hun Lee, G. Cho","doi":"10.1109/ISSCC.2017.7870322","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870322","url":null,"abstract":"The number of mobile device users increases every year. Each mobile device is usually equipped with a Li-ion battery having voltage that varies from a minimum of 2.7V to a maximum of 4.2V. Therefore, as the battery voltage decreases with time, a DC-DC converter is required for a regulated supply lower or higher than the battery voltage. A simple buck converter is not suited for this case, since step-up conversion is not available [1]. Instead, a non-inverting buck-boost converter can be a solution over the entire range of the battery voltage [1–4]. Many research studies related to buck-boost converters operated on Li-ion batteries set the target output voltage at around 3.4V [3,4]. Since Li-ion batteries have a wide plateau from 3.6V to 3.8V and a small energy storage below the plateau, DC-DC converters are generally operated on step-down mode at most of the battery voltage range, as shown in Fig. 10.4.1 top. Notwithstanding, step-up conversion is also required for extracting the energy below the plateau even if it is a small amount in the battery. Therefore, in DC-DC converters, it is critical to maintain high efficiency over the whole range of the battery voltage when it operates on both step-down and step-up modes to prolong the battery usage effectively. However, if the conventional buck-boost topology of Fig. 10.4.1 bottom-left is used for step-up and step-down purposes, there are always two switches (S1 and S3) conducting in the main current path through the inductor. Thus, the switches become large in size to minimize the conduction loss. As the switching loss also increases when the switch size is larger, the efficiency of this structure is usually lower than that of the simple buck (or boost) converter [1]. In this respect, this paper proposes a topology named a flying-capacitor buck-boost (FCBB) converter suitable for such an application by obtaining both step-up and step-down operations with high efficiency throughout the whole range of the battery voltage.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130160652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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