Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332792
Y. Chiu, Paul R. Gray, Borivoje Nikolic
A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.
{"title":"A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 /spl mu/m CMOS with 99 dB SFDR","authors":"Y. Chiu, Paul R. Gray, Borivoje Nikolic","doi":"10.1109/ISSCC.2004.1332792","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332792","url":null,"abstract":"A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129591571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332639
Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo
A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332718
J. DeNatale
MEMS phase shifters, based on switchable passive components, are used to achieve a variety of circuits with low insertion loss, wide bandwidth and compact die size. Integration of MEMS switches with active GaAs pHEMT MMICs achieves reconfigurable LNA and PA devices. A 4 b true time-delay phase-shifter achieves /spl les/1.2 dB insertion loss on a 7 mm/sup 2/ die.
{"title":"Reconfigurable RF circuits based on integrated MEMS switches","authors":"J. DeNatale","doi":"10.1109/ISSCC.2004.1332718","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332718","url":null,"abstract":"MEMS phase shifters, based on switchable passive components, are used to achieve a variety of circuits with low insertion loss, wide bandwidth and compact die size. Integration of MEMS switches with active GaAs pHEMT MMICs achieves reconfigurable LNA and PA devices. A 4 b true time-delay phase-shifter achieves /spl les/1.2 dB insertion loss on a 7 mm/sup 2/ die.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332587
Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan
A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.
{"title":"A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM","authors":"Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan","doi":"10.1109/ISSCC.2004.1332587","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332587","url":null,"abstract":"A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125651053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332649
H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib
A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.
{"title":"A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter","authors":"H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib","doi":"10.1109/ISSCC.2004.1332649","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332649","url":null,"abstract":"A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125937563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332612
M. Terrovitis, M. Mack, K. Singh, M. Zargari
A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.
{"title":"A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN","authors":"M. Terrovitis, M. Mack, K. Singh, M. Zargari","doi":"10.1109/ISSCC.2004.1332612","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332612","url":null,"abstract":"A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332580
N. Lu
In three decades, the IC industry grew from nothing to current GSI levels (with 10/sup 9/ devices on a chip). Its major driving force has been the use of device scaling, which has been especially effective in enhancing the performance of digital chips. However, increasingly, diverse system applications have created an additional driving force - the development of more and more system chips with an increased need to integrate more diverse functionality (digital, analog, memory, RF, etc.) within a limited form factor. In addition to current SoCs on a 2D die, a trend for the coming decade is multidimensional die integration on interconnected substrates in a compact package. Correspondingly, a metric analyzing technology trends is presented. At the same time, beyond the innovative foundry/fabless business structure of the 1990s, new business models are evolving for the realization of system chips. Such models, leading to an effective solution called virtual vertical integration, is discussed. System-chip development must also be vertically integrated to achieve optimized performance, but advanced technologies required to realize such integration cover various horizontal segments of knowledge, such as multidimensional-die architecture design, circuit design, and related design automation, as well as novel testing and packaging techniques, leading-edge device and wafer-fabrication technologies, and solution-oriented software coding. In this regard, critical challenges are highlighted in terms of power partitioning, integrated design, and built-in quality assurance for known-good-die, signal integrity in field applications, and technology optimization across different segments. The parallelism of technology solutions with business models, and their conjoined optimization in the coming system-chip era, is illustrated in this paper.
{"title":"Emerging technology and business solutions for system chips","authors":"N. Lu","doi":"10.1109/ISSCC.2004.1332580","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332580","url":null,"abstract":"In three decades, the IC industry grew from nothing to current GSI levels (with 10/sup 9/ devices on a chip). Its major driving force has been the use of device scaling, which has been especially effective in enhancing the performance of digital chips. However, increasingly, diverse system applications have created an additional driving force - the development of more and more system chips with an increased need to integrate more diverse functionality (digital, analog, memory, RF, etc.) within a limited form factor. In addition to current SoCs on a 2D die, a trend for the coming decade is multidimensional die integration on interconnected substrates in a compact package. Correspondingly, a metric analyzing technology trends is presented. At the same time, beyond the innovative foundry/fabless business structure of the 1990s, new business models are evolving for the realization of system chips. Such models, leading to an effective solution called virtual vertical integration, is discussed. System-chip development must also be vertically integrated to achieve optimized performance, but advanced technologies required to realize such integration cover various horizontal segments of knowledge, such as multidimensional-die architecture design, circuit design, and related design automation, as well as novel testing and packaging techniques, leading-edge device and wafer-fabrication technologies, and solution-oriented software coding. In this regard, critical challenges are highlighted in terms of power partitioning, integrated design, and built-in quality assurance for known-good-die, signal integrity in field applications, and technology optimization across different segments. The parallelism of technology solutions with business models, and their conjoined optimization in the coming system-chip era, is illustrated in this paper.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127641222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332746
T. Kaplan, J. Jensen, C. Fields, M. Chang
A 3b /spl Delta//spl Sigma/-modulated mismatch-shaped DAC is presented. The mismatch shaper uses 7 tunable 1.5b switched-capacitor bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. The DAC can generate narrowband signals from 250 to 750MHz with /spl ges/68dB SNR, /spl ges/74dB SFDR, and -80dBc intermodulation distortion.
{"title":"A 2GS/s 3b /spl Delta//spl Sigma/-modulated DAC with a tunable switched-capacitor bandpass DAC mismatch shaper","authors":"T. Kaplan, J. Jensen, C. Fields, M. Chang","doi":"10.1109/ISSCC.2004.1332746","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332746","url":null,"abstract":"A 3b /spl Delta//spl Sigma/-modulated mismatch-shaped DAC is presented. The mismatch shaper uses 7 tunable 1.5b switched-capacitor bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. The DAC can generate narrowband signals from 250 to 750MHz with /spl ges/68dB SNR, /spl ges/74dB SFDR, and -80dBc intermodulation distortion.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332674
H. Eltoukhy, K. Salama, A. El Gamal, M. Ronaghi, R. Davis
A chip comprising a 8x16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP is fabricated in a 0.18/spl mu/m CMOS process. Detection of 10/sup -6/lux at 30s integration time is achieved via on-chip background subtraction, correlated multiple sampling and averaged 128 13b digitizations/readout. The IC is 25mm/sup 2/ and contains 492k transistors.
{"title":"A 0.18/spl mu/m CMOS 10/sup -6/ lux bioluminescence detection system-on-chip","authors":"H. Eltoukhy, K. Salama, A. El Gamal, M. Ronaghi, R. Davis","doi":"10.1109/ISSCC.2004.1332674","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332674","url":null,"abstract":"A chip comprising a 8x16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP is fabricated in a 0.18/spl mu/m CMOS process. Detection of 10/sup -6/lux at 30s integration time is achieved via on-chip background subtraction, correlated multiple sampling and averaged 128 13b digitizations/readout. The IC is 25mm/sup 2/ and contains 492k transistors.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332813
K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz
A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.
在1.8 V 0.18 /spl mu/m CMOS工艺中实现了一个2kb可重构SRAM块，使用自定时脉冲模式电路，能够模拟部分缓存或流FIFO，工作频率为1.1 GHz (10F04周期)。可重构性所需的额外逻辑消耗了总功率的26%和总面积的32%。
{"title":"Architecture and circuit techniques for a reconfigurable memory block","authors":"K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz","doi":"10.1109/ISSCC.2004.1332813","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332813","url":null,"abstract":"A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128832623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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