Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332687
Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim
A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.
提出了一种用于高速DRAM的同时4级双向I/O接口。它的数据速率为4Gb/s/引脚，使用500MHz时钟发生器和全CMOS电源导轨摆幅。这个I/O接口是在330x66/spl mu/m/sup 2/ /的0.10/spl mu/m DRAM CMOS工艺上制造的。收发器在1.8V供电的通道上执行200mVx690ps通过眼窗。
{"title":"A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory","authors":"Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim","doi":"10.1109/ISSCC.2004.1332687","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332687","url":null,"abstract":"A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115501781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/JSSC.2004.837027
L. Wong, Shohan Hossain, Andrew Ta, Jörgen Edvinsson, Dominic H. Rivas, Hans Nääs
A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains LNAs, filters, ADCs, a battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. The 200k transistor IC occupies 49mm/sup 2/, is fabricated in a 0.5/spl mu/m 2P3M multi-V, CMOS process and consumes 8/spl mu/W from a 2.8V supply.
{"title":"A very low power CMOS mixed-signal IC for implantable pacemaker applications","authors":"L. Wong, Shohan Hossain, Andrew Ta, Jörgen Edvinsson, Dominic H. Rivas, Hans Nääs","doi":"10.1109/JSSC.2004.837027","DOIUrl":"https://doi.org/10.1109/JSSC.2004.837027","url":null,"abstract":"A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains LNAs, filters, ADCs, a battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. The 200k transistor IC occupies 49mm/sup 2/, is fabricated in a 0.5/spl mu/m 2P3M multi-V, CMOS process and consumes 8/spl mu/W from a 2.8V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332587
Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan
A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.
{"title":"A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM","authors":"Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan","doi":"10.1109/ISSCC.2004.1332587","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332587","url":null,"abstract":"A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125651053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332612
M. Terrovitis, M. Mack, K. Singh, M. Zargari
A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.
{"title":"A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN","authors":"M. Terrovitis, M. Mack, K. Singh, M. Zargari","doi":"10.1109/ISSCC.2004.1332612","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332612","url":null,"abstract":"A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332649
H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib
A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.
{"title":"A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter","authors":"H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib","doi":"10.1109/ISSCC.2004.1332649","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332649","url":null,"abstract":"A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125937563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332674
H. Eltoukhy, K. Salama, A. El Gamal, M. Ronaghi, R. Davis
A chip comprising a 8x16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP is fabricated in a 0.18/spl mu/m CMOS process. Detection of 10/sup -6/lux at 30s integration time is achieved via on-chip background subtraction, correlated multiple sampling and averaged 128 13b digitizations/readout. The IC is 25mm/sup 2/ and contains 492k transistors.
{"title":"A 0.18/spl mu/m CMOS 10/sup -6/ lux bioluminescence detection system-on-chip","authors":"H. Eltoukhy, K. Salama, A. El Gamal, M. Ronaghi, R. Davis","doi":"10.1109/ISSCC.2004.1332674","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332674","url":null,"abstract":"A chip comprising a 8x16 pseudo-differential pixel array, 128-channel 13b ADC and column-level DSP is fabricated in a 0.18/spl mu/m CMOS process. Detection of 10/sup -6/lux at 30s integration time is achieved via on-chip background subtraction, correlated multiple sampling and averaged 128 13b digitizations/readout. The IC is 25mm/sup 2/ and contains 492k transistors.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130135735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332792
Y. Chiu, Paul R. Gray, Borivoje Nikolic
A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.
{"title":"A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 /spl mu/m CMOS with 99 dB SFDR","authors":"Y. Chiu, Paul R. Gray, Borivoje Nikolic","doi":"10.1109/ISSCC.2004.1332792","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332792","url":null,"abstract":"A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129591571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332617
Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue
A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.
{"title":"A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel","authors":"Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue","doi":"10.1109/ISSCC.2004.1332617","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332617","url":null,"abstract":"A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332632
E. Beyne
Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).
{"title":"3D interconnection and packaging: impending reality or still a dream?","authors":"E. Beyne","doi":"10.1109/ISSCC.2004.1332632","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332632","url":null,"abstract":"Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332775
P. Urard, L. Paumier, Malika Viollet, E. Lantreibecq, H. Michel, Srikanth Muroor, Benjamin Coates, B. Gupta
The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannon's limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.
{"title":"A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder","authors":"P. Urard, L. Paumier, Malika Viollet, E. Lantreibecq, H. Michel, Srikanth Muroor, Benjamin Coates, B. Gupta","doi":"10.1109/ISSCC.2004.1332775","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332775","url":null,"abstract":"The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannon's limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125695820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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