Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332775
P. Urard, L. Paumier, Malika Viollet, E. Lantreibecq, H. Michel, Srikanth Muroor, Benjamin Coates, B. Gupta
The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannon's limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.
{"title":"A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder","authors":"P. Urard, L. Paumier, Malika Viollet, E. Lantreibecq, H. Michel, Srikanth Muroor, Benjamin Coates, B. Gupta","doi":"10.1109/ISSCC.2004.1332775","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332775","url":null,"abstract":"The implementation of a 350 Mb/s 16-state SISO turbo decoder and its corresponding coder are described. It performs within 1.8 dB of Shannon's limit in terms of error correction. Implemented in 0.13 /spl mu/m low-leakage technology, this codec occupies 10 mm/sup 2/ and is designed using a Matlab-to-RTL design flow.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125695820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332640
D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne
Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.
{"title":"Low-voltage-swing logic circuits for a 7GHz x86 integer core","authors":"D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne","doi":"10.1109/ISSCC.2004.1332640","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332640","url":null,"abstract":"Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133217506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332660
A. Scuderi, F. Carrara, G. Palmisano
A 1.8 GHz silicon bipolar PA is presented. A protection circuit enables the amplifier to sustain a 10:1 load VSWR at 5 V supply despite a low BV/sub ceo/ of 6.5 V. A temperature-compensated bias network allows a moderate power-control slope of less than 80 dB/V. A 50% PAE is attained at a 33.8 dBm output power level. The 1.2/spl times/1.5 mm/sup 2/ die is implemented in 0.8 /spl mu/m BiPMOS.
{"title":"VSWR-protected silicon bipolar power amplifier with smooth power control slope","authors":"A. Scuderi, F. Carrara, G. Palmisano","doi":"10.1109/ISSCC.2004.1332660","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332660","url":null,"abstract":"A 1.8 GHz silicon bipolar PA is presented. A protection circuit enables the amplifier to sustain a 10:1 load VSWR at 5 V supply despite a low BV/sub ceo/ of 6.5 V. A temperature-compensated bias network allows a moderate power-control slope of less than 80 dB/V. A 50% PAE is attained at a 33.8 dBm output power level. The 1.2/spl times/1.5 mm/sup 2/ die is implemented in 0.8 /spl mu/m BiPMOS.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133406050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332743
Bernd Schafferer, R. Adams
This paper presents an uncalibrated 0.18 /spl mu/m CMOS 14 bit 1.4 GS/s DAC, with an LVDS interface, which achieves 67 dB SFDR for a 260 MHz full-scale tone and 70 dB ACLR for a two-carrier output, centered at 470 MHz. The IC dissipates a core power of 200 mW.
本文提出了一种未经校准的0.18 /spl mu/m CMOS 14位1.4 GS/s DAC，具有LVDS接口，在260 MHz满频音下实现67 dB SFDR，在470 MHz中心双载波输出时实现70 dB ACLR。该IC的核心功耗为200mw。
{"title":"A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications","authors":"Bernd Schafferer, R. Adams","doi":"10.1109/ISSCC.2004.1332743","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332743","url":null,"abstract":"This paper presents an uncalibrated 0.18 /spl mu/m CMOS 14 bit 1.4 GS/s DAC, with an LVDS interface, which achieves 67 dB SFDR for a 260 MHz full-scale tone and 70 dB ACLR for a two-carrier output, centered at 470 MHz. The IC dissipates a core power of 200 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132619838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332601
Bas M. Putter
A continuous-time 1 b /spl Sigma//spl Delta/ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 /spl mu/m CMOS chip consumes 6.0 mW.
{"title":"/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC","authors":"Bas M. Putter","doi":"10.1109/ISSCC.2004.1332601","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332601","url":null,"abstract":"A continuous-time 1 b /spl Sigma//spl Delta/ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 /spl mu/m CMOS chip consumes 6.0 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/JSSC.2004.837027
L. Wong, Shohan Hossain, Andrew Ta, Jörgen Edvinsson, Dominic H. Rivas, Hans Nääs
A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains LNAs, filters, ADCs, a battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. The 200k transistor IC occupies 49mm/sup 2/, is fabricated in a 0.5/spl mu/m 2P3M multi-V, CMOS process and consumes 8/spl mu/W from a 2.8V supply.
{"title":"A very low power CMOS mixed-signal IC for implantable pacemaker applications","authors":"L. Wong, Shohan Hossain, Andrew Ta, Jörgen Edvinsson, Dominic H. Rivas, Hans Nääs","doi":"10.1109/JSSC.2004.837027","DOIUrl":"https://doi.org/10.1109/JSSC.2004.837027","url":null,"abstract":"A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains LNAs, filters, ADCs, a battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. The 200k transistor IC occupies 49mm/sup 2/, is fabricated in a 0.5/spl mu/m 2P3M multi-V, CMOS process and consumes 8/spl mu/W from a 2.8V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332617
Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue
A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.
{"title":"A 3.9 /spl mu/m pixel pitch VGA format 10 b digital image sensor with 1.5-transistor/pixel","authors":"Hidekazu Takahashi, M. Kinoshita, Kazumichi Morita, Takahiro Shirai, Toshiaki Sato, T. Kimura, H. Yuzurihara, S. Inoue","doi":"10.1109/ISSCC.2004.1332617","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332617","url":null,"abstract":"A CMOS image sensor with a shared 1.5 transistor/pixel architecture and buried photodiode with complete charge transfer capability is described. The sensor achieves a 330 /spl mu/V noise floor and 50 pA/cm/sup 2/ dark current at 45/spl deg/C. The chip is fabricated in a thin planarized 0.35 /spl mu/m 1P2M CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332632
E. Beyne
Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).
{"title":"3D interconnection and packaging: impending reality or still a dream?","authors":"E. Beyne","doi":"10.1109/ISSCC.2004.1332632","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332632","url":null,"abstract":"Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116529594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332687
Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim
A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.
提出了一种用于高速DRAM的同时4级双向I/O接口。它的数据速率为4Gb/s/引脚，使用500MHz时钟发生器和全CMOS电源导轨摆幅。这个I/O接口是在330x66/spl mu/m/sup 2/ /的0.10/spl mu/m DRAM CMOS工艺上制造的。收发器在1.8V供电的通道上执行200mVx690ps通过眼窗。
{"title":"A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory","authors":"Jin-Hyun Kim, Sua Kim, Woo-Seop Kim, J. Choi, H. Hwang, Changhyun Kim, Sooin Cho, Suki Kim","doi":"10.1109/ISSCC.2004.1332687","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332687","url":null,"abstract":"A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10/spl mu/m DRAM CMOS process in 330x66/spl mu/m/sup 2/. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115501781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332624
H. Morimura, T. Shimannura, K. Fujii, S. Shigematsu, Y. Okazaki, M. Katsuyuki
Pixel-parallel architecture with 1b ADC per pixel achieves 6.4/spl mu/W dissipation. Pixel memory element and event counting sensing circuitry control fingerprint acquisition. A 224 x 256 pixel array is built in a 0.25/spl mu/m CMOS process.
像素并行架构，每像素1b ADC，功耗6.4/spl mu/W。像素存储元件和事件计数传感电路控制指纹采集。在0.25/spl mu/m CMOS工艺中构建了224 x 256像素阵列。
{"title":"A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier","authors":"H. Morimura, T. Shimannura, K. Fujii, S. Shigematsu, Y. Okazaki, M. Katsuyuki","doi":"10.1109/ISSCC.2004.1332624","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332624","url":null,"abstract":"Pixel-parallel architecture with 1b ADC per pixel achieves 6.4/spl mu/W dissipation. Pixel memory element and event counting sensing circuitry control fingerprint acquisition. A 224 x 256 pixel array is built in a 0.25/spl mu/m CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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