Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332681
M. Meghelli
A 4:1 multiplexer implemented in a 210GHz f/sub t/, 0.13/spl mu/m SiGe-bipolar technology and operating beyond 100Gb/s is reported. Control of on-chip clock distribution is critical to achieve such data rate. The chip consumes 1.45W from a -3.3V supply and exhibits less than 340fs rms jitter on the output data.
{"title":"A 108Gb/s 4:1 multiplexer in 0.13/spl mu/m SiGe-bipolar technology","authors":"M. Meghelli","doi":"10.1109/ISSCC.2004.1332681","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332681","url":null,"abstract":"A 4:1 multiplexer implemented in a 210GHz f/sub t/, 0.13/spl mu/m SiGe-bipolar technology and operating beyond 100Gb/s is reported. Control of on-chip clock distribution is critical to achieve such data rate. The chip consumes 1.45W from a -3.3V supply and exhibits less than 340fs rms jitter on the output data.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332585
J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino
The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.
{"title":"A 4Mb 0.18 /spl mu/m 1T1MTJ Toggle MRAM memory","authors":"J. Nahas, T. Andre, Chitra K. Subramanian, B. Garni, H. Lin, A. Omair, W. Martino","doi":"10.1109/ISSCC.2004.1332585","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332585","url":null,"abstract":"The 4.5/spl times/6.3mm/sup 2/ 25ns cycle-time 4Mb Toggle MRAM memory, built in 0.18 /spl mu/m 5M CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction. The memory uses uni-directional programming currents with isolated write and read paths and balanced current mirror sense amplifier.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332606
K. Philips, Peter Nuijten, R. Roovers, F. Muñoz, M. Tejero, A. Torralba
A continuous-time /spl Sigma//spl Delta/ ADC with merged channel filter and programmable-gain functionality is presented. Interferers above full-scale can be applied without jeopardizing reception of weak desired signals. The merged design occupies 0.14 mm/sup 2/ in 0.18 /spl mu/m CMOS, consumes 2 mW, and achieves 89 dB of dynamic range (DR) in a 1 MHz bandwidth.
{"title":"A 2 mW 89 dB DR continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to wide-band interferers","authors":"K. Philips, Peter Nuijten, R. Roovers, F. Muñoz, M. Tejero, A. Torralba","doi":"10.1109/ISSCC.2004.1332606","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332606","url":null,"abstract":"A continuous-time /spl Sigma//spl Delta/ ADC with merged channel filter and programmable-gain functionality is presented. Interferers above full-scale can be applied without jeopardizing reception of weak desired signals. The merged design occupies 0.14 mm/sup 2/ in 0.18 /spl mu/m CMOS, consumes 2 mW, and achieves 89 dB of dynamic range (DR) in a 1 MHz bandwidth.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121405294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332682
T. Yamamoto, M. Horinaka, D. Yamazaki, H. Nomura, K. Hashimoto, H. Onodera
The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.
{"title":"A 43Gb/s 2:1 selector IC in 90nm CMOS technology","authors":"T. Yamamoto, M. Horinaka, D. Yamazaki, H. Nomura, K. Hashimoto, H. Onodera","doi":"10.1109/ISSCC.2004.1332682","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332682","url":null,"abstract":"The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332651
Jeongsik Yang, Jinwook Kim, S. Byun, C. Conroy, Beomsup Kim
This paper presents a quad-channel serial-link transceiver which provides 12.5 Gb/s full duplex raw data rate for a single 10 Gb XAUI interface. A mixed-mode LMS adaptive equalizer is adopted, which achieves 3 dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64 ps-pp jitter. The IC consumes 718 mW at 3.125 Gb/s/ch with full duplex data rate.
{"title":"A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18 /spl mu/m CMOS","authors":"Jeongsik Yang, Jinwook Kim, S. Byun, C. Conroy, Beomsup Kim","doi":"10.1109/ISSCC.2004.1332651","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332651","url":null,"abstract":"This paper presents a quad-channel serial-link transceiver which provides 12.5 Gb/s full duplex raw data rate for a single 10 Gb XAUI interface. A mixed-mode LMS adaptive equalizer is adopted, which achieves 3 dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64 ps-pp jitter. The IC consumes 718 mW at 3.125 Gb/s/ch with full duplex data rate.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"495 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115882270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332706
T. Shimoda, T. Kawase
All-polymer TFTs are developed using an inkjet printing process. Conductive polymer is deposited onto a substrate having a wettability contrast to realize a channel length of 10/spl mu/m and 500/spl mu/m width. Polymer integrated circuits and active-matrix backplanes are also developed and their operation demonstrated.
{"title":"All-polymer thin film transistor fabricated by high-resolution ink-jet printing","authors":"T. Shimoda, T. Kawase","doi":"10.1109/ISSCC.2004.1332706","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332706","url":null,"abstract":"All-polymer TFTs are developed using an inkjet printing process. Conductive polymer is deposited onto a substrate having a wettability contrast to realize a channel length of 10/spl mu/m and 500/spl mu/m width. Polymer integrated circuits and active-matrix backplanes are also developed and their operation demonstrated.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115907391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332799
S. Radovanovic, A. Annema, B. Nauta
A 3 Gb/s optical detector with integrated photodiode and pre-amplifier for 850 nm light is presented. The IC is implemented in standard 0.18 /spl mu/m CMOS. The data rate is achieved by using an inherently robust analog equalizer without sacrificing responsivity.
{"title":"3Gb/s monolithically integrated photodiode and pre-amplifier in standard 0.18/spl mu/m CMOS","authors":"S. Radovanovic, A. Annema, B. Nauta","doi":"10.1109/ISSCC.2004.1332799","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332799","url":null,"abstract":"A 3 Gb/s optical detector with integrated photodiode and pre-amplifier for 850 nm light is presented. The IC is implemented in standard 0.18 /spl mu/m CMOS. The data rate is achieved by using an inherently robust analog equalizer without sacrificing responsivity.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134584337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332667
H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H. Mattausch, T. Koide, S. Soeda, K. Dosaka, K. Arinnoto
A 4.5 Mb dynamic ternary CAM (DTCAM) is designed in 0.13 /spl mu/m embedded DRAM technology. A performance of 143 M searches/sec is achieved at a power dissipation of 1.1 W and on a small silicon area of 32 mm/sup 2/. A 3.6-times yield improvement is estimated by employing pipelined hierarchical searching and row/column-shift redundancy.
{"title":"A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture","authors":"H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H. Mattausch, T. Koide, S. Soeda, K. Dosaka, K. Arinnoto","doi":"10.1109/ISSCC.2004.1332667","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332667","url":null,"abstract":"A 4.5 Mb dynamic ternary CAM (DTCAM) is designed in 0.13 /spl mu/m embedded DRAM technology. A performance of 143 M searches/sec is achieved at a power dissipation of 1.1 W and on a small silicon area of 32 mm/sup 2/. A 3.6-times yield improvement is estimated by employing pipelined hierarchical searching and row/column-shift redundancy.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133922033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332675
A. Romani, N. Manaresi, L. Marzocchi, G. Medoro, A. Leonardi, L. Altomare, M. Tartagni, R. Guerrieri
Fully-electronic detection of cells and microbeads is achieved on a 320x320 array of capacitive sensors in 0.35/spl mu/m 2P3M CMOS technology that also integrates particle actuation by dielectrophoresis. Particle-associated equivalent input capacitance variations larger than 0.42fF are measured with 39dB SNR. Output noise is /spl les/1.6mV, the resolution of the 12b ADC.
{"title":"Capacitive sensor array for localization of bioparticles in CMOS lab-on-a-chip","authors":"A. Romani, N. Manaresi, L. Marzocchi, G. Medoro, A. Leonardi, L. Altomare, M. Tartagni, R. Guerrieri","doi":"10.1109/ISSCC.2004.1332675","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332675","url":null,"abstract":"Fully-electronic detection of cells and microbeads is achieved on a 320x320 array of capacitive sensors in 0.35/spl mu/m 2P3M CMOS technology that also integrates particle actuation by dielectrophoresis. Particle-associated equivalent input capacitance variations larger than 0.42fF are measured with 39dB SNR. Output noise is /spl les/1.6mV, the resolution of the 12b ADC.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-13DOI: 10.1109/ISSCC.2004.1332773
D. Garrett, G. Woodward, L. Davis, G. Knagge, C. Nicol
A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4/spl times/4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 /spl mu/m 6M CMOS, the core of the chip covers an 11.6 mm/sup 2/ area.
{"title":"A 28.8 Mb/s 4/spl times/4 MIMO 3G high-speed downlink packet access receiver with normalized least mean square equalization","authors":"D. Garrett, G. Woodward, L. Davis, G. Knagge, C. Nicol","doi":"10.1109/ISSCC.2004.1332773","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332773","url":null,"abstract":"A receiver for high-speed downlink packet access supporting 28.8 Mb/s using QPSK over a 5 MHz frequency selective 4/spl times/4 MIMO wireless channel (5.76 b/s/Hz). A key feature is the normalized least mean squares space-time equalizer using a pilot correlator for more accurate adaptation. Fabricated in 0.18 /spl mu/m 6M CMOS, the core of the chip covers an 11.6 mm/sup 2/ area.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131761140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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