Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060846
Lee Wang, S. Hsu
Scalable Logic Gate Non-Volatile Memory (SLGNVM) devices fabricated with standard CMOS logic process have been demonstrated with 110 nm, 55 nm, and 40 nm nodes. The cell sizes for the NOR flash array complied with the process design rules of the CMOS logic nodes are 0.5424 μm2, 0.2287 μm2, and 0.1095 μm2, respectively. The SLGNVM devices have 3V ~ 5V program/erase windows with good data retention and endurance properties. The arrays of SLGNVM devices are suitable for embedded EEPROM and flash in digital circuitries, and for the new applications of non-volatile-SRAM (nvSRAM), Non-Volatile-Register (NVR), and non-volatile FPGA (nvFPGA).
{"title":"Scalable Logic Gate Non-Volatile Memory","authors":"Lee Wang, S. Hsu","doi":"10.1109/NVMTS.2014.7060846","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060846","url":null,"abstract":"Scalable Logic Gate Non-Volatile Memory (SLGNVM) devices fabricated with standard CMOS logic process have been demonstrated with 110 nm, 55 nm, and 40 nm nodes. The cell sizes for the NOR flash array complied with the process design rules of the CMOS logic nodes are 0.5424 μm2, 0.2287 μm2, and 0.1095 μm2, respectively. The SLGNVM devices have 3V ~ 5V program/erase windows with good data retention and endurance properties. The arrays of SLGNVM devices are suitable for embedded EEPROM and flash in digital circuitries, and for the new applications of non-volatile-SRAM (nvSRAM), Non-Volatile-Register (NVR), and non-volatile FPGA (nvFPGA).","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133392313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060847
Wookyung Sun, H. Lim, Hyungsoon Shin, Wootae Lee
Power consumption of large-scale crossbar array architecture is investigated by the comprehensive crossbar array matrix model. The power dissipation is examined as functions of array size, leakage current of selector, and various bias schemes. The power consumption increases as the array size and the leakage current of selector increases. In addition, 1/3 bias scheme shows power consumption about 1~2 orders of magnitude larger than other bias schemes. This phenomenon is induced from the unselected cells which is delivered with voltage about Vdd/3, whereas the voltage of unselected cells are almost 0 V for 1/2 bias and floating bias schemes.
{"title":"Investigation of power dissipation for ReRAM in crossbar array architecture","authors":"Wookyung Sun, H. Lim, Hyungsoon Shin, Wootae Lee","doi":"10.1109/NVMTS.2014.7060847","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060847","url":null,"abstract":"Power consumption of large-scale crossbar array architecture is investigated by the comprehensive crossbar array matrix model. The power dissipation is examined as functions of array size, leakage current of selector, and various bias schemes. The power consumption increases as the array size and the leakage current of selector increases. In addition, 1/3 bias scheme shows power consumption about 1~2 orders of magnitude larger than other bias schemes. This phenomenon is induced from the unselected cells which is delivered with voltage about Vdd/3, whereas the voltage of unselected cells are almost 0 V for 1/2 bias and floating bias schemes.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134445488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060845
A. Schonhals, R. Waser, S. Menzel, V. Rana
Complementary switching mechanism allows for distinguishing between different physical orientations of the conductive filament. In addition to the multilevel capability of single layer Ta2O5 devices, 3-bit information can also be stored and read in a single device. In this report, we present a novel read scheme, allowing for distinguishing 8 different states only by using 4 different resistive states with the pulse measurements. Variability and cycle-to-cycle stability of the single layer Ta2O5 complementary switching are also discussed in details.
{"title":"3-bit read scheme for single layer Ta2O5 ReRAM","authors":"A. Schonhals, R. Waser, S. Menzel, V. Rana","doi":"10.1109/NVMTS.2014.7060845","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060845","url":null,"abstract":"Complementary switching mechanism allows for distinguishing between different physical orientations of the conductive filament. In addition to the multilevel capability of single layer Ta2O5 devices, 3-bit information can also be stored and read in a single device. In this report, we present a novel read scheme, allowing for distinguishing 8 different states only by using 4 different resistive states with the pulse measurements. Variability and cycle-to-cycle stability of the single layer Ta2O5 complementary switching are also discussed in details.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121478383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060849
Y. Jiang, C. C. Tan, E. Yeo, M. Li, W. He, V. Y. Zhuo, Z. Fang, B. Weng
A novel strained SiGe/TaOx/Ta RRAM device is successfully demonstrated via a fully CMOS compatible process. The bottom electrode (BE) is made of strained single crystalline SiGe layer where both n type and p type SiGe layer as the BE. Typical bipolar switching behavior is obtained for such RRAM devices. Cycle to cycle uniformity are investigated in this work, and it is found that n type SiGe as BE shows better uniformity due to the better dopant distribution for Arsenic than Boron in SiGe layer.
{"title":"Novel strained SiGe/TaOx/Ta RRAM device fabricated by fully CMOS compatible process","authors":"Y. Jiang, C. C. Tan, E. Yeo, M. Li, W. He, V. Y. Zhuo, Z. Fang, B. Weng","doi":"10.1109/NVMTS.2014.7060849","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060849","url":null,"abstract":"A novel strained SiGe/TaOx/Ta RRAM device is successfully demonstrated via a fully CMOS compatible process. The bottom electrode (BE) is made of strained single crystalline SiGe layer where both n type and p type SiGe layer as the BE. Typical bipolar switching behavior is obtained for such RRAM devices. Cycle to cycle uniformity are investigated in this work, and it is found that n type SiGe as BE shows better uniformity due to the better dopant distribution for Arsenic than Boron in SiGe layer.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124087659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060836
D. Kang, Song Yi Kim, Sang-su Park, S. Eun, Jong Whan Ma, Jae Hyun Park, Il Mok Park, K. Park, Jae-Hee Oh, Zhe Wu, Jeong hee Park, Sug-Woo Jung, Ho Kyun Ahn, Youngsoo Lim, Sunghee Cho, G. Jeong, D. Ahn, S. Nam, G. Jin, E. Jung
Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.
{"title":"Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications","authors":"D. Kang, Song Yi Kim, Sang-su Park, S. Eun, Jong Whan Ma, Jae Hyun Park, Il Mok Park, K. Park, Jae-Hee Oh, Zhe Wu, Jeong hee Park, Sug-Woo Jung, Ho Kyun Ahn, Youngsoo Lim, Sunghee Cho, G. Jeong, D. Ahn, S. Nam, G. Jin, E. Jung","doi":"10.1109/NVMTS.2014.7060836","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060836","url":null,"abstract":"Needs for the performance improvement of memory subsystem in big data and clouding computing era begin to open new markets for emerging memories such as phase change memory, spin-torque-transfer magnetic memory, and metal oxide memory. To fulfill these needs, a cost-effective and high-speed phase change memory cell scheme was introduced at 19nm technology node, which is directly scalable down to 1y or 1z nm nodes and can be extendable to stacked array for higher density. Here, key technologies such as self-aligned cell patterning and vertical poly-Si diode switch on metal word line were adopted. In addition, damascene Ge-Sb-Te technologies were optimized to improve programming speed and to show excellent cell performances.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124675863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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