Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060862
Gwihyun Kim, Sanghyun Lee, Seungwoo Hong, S. Baik, Hideki Hori, D. Ahn
Low voltage programming of multi-level-cell phase change random access memory (MLC PRAM) is important for future low power high density applications of PRAM devices [1]. We have characterized voltage dependent resistance switching characteristics of PRAM devices with various voltage pulses, based on which a dual-pulse programming method is systematically proposed to demonstrate some principles of low voltage MLC programming. A microstructural model is also introduced to provide a comprehensive explanation of resistance swiching for various voltage pulses.
{"title":"Adjustable voltage dependent switching characteristics of PRAM for low voltage programming of multi-level resistances","authors":"Gwihyun Kim, Sanghyun Lee, Seungwoo Hong, S. Baik, Hideki Hori, D. Ahn","doi":"10.1109/NVMTS.2014.7060862","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060862","url":null,"abstract":"Low voltage programming of multi-level-cell phase change random access memory (MLC PRAM) is important for future low power high density applications of PRAM devices [1]. We have characterized voltage dependent resistance switching characteristics of PRAM devices with various voltage pulses, based on which a dual-pulse programming method is systematically proposed to demonstrate some principles of low voltage MLC programming. A microstructural model is also introduced to provide a comprehensive explanation of resistance swiching for various voltage pulses.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130613273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060857
Seokjae Lim, Sangheon Lee, J. Woo, Daeseok Lee, Jaesung Park, Jeonghwan Song, Kibong Moon, Jaehyuk Park, A. Prakash, H. Hwang
We demonstrate the device characteristics of W/Cu/N-GST/Al2O3/Pt conductive-bridging RAM, focusing on the nitrogen-doped Ge2Sb2Te5 buffer layer to realize non-volatile memory applications. The on/off ratio of typical Cu/Al2O3-based CBRAM was improved from 102 to 105 with the N-GST buffer layer. The switching uniformity also improved compared to that of a non-buffer layer device. The improved properties that were realized are attributed to the effects of buffer layer such as controlled Cu-ion injection, internal resistor, and Joule heating confinement during the reset process. Furthermore, to verify the effect of nitrogen on the switching properties, we compared the GST and N-GST buffer layers. We believe that doped nitrogen helped to control Cu-ion injection into the resistive switching layer, and to confine the joule heating during the reset process, enabling a high on/off ratio and improved switching uniformity.
{"title":"Effect of nitrogen-doped GST buffer layer on switching characteristics of conductive-bridging RAM","authors":"Seokjae Lim, Sangheon Lee, J. Woo, Daeseok Lee, Jaesung Park, Jeonghwan Song, Kibong Moon, Jaehyuk Park, A. Prakash, H. Hwang","doi":"10.1109/NVMTS.2014.7060857","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060857","url":null,"abstract":"We demonstrate the device characteristics of W/Cu/N-GST/Al2O3/Pt conductive-bridging RAM, focusing on the nitrogen-doped Ge2Sb2Te5 buffer layer to realize non-volatile memory applications. The on/off ratio of typical Cu/Al2O3-based CBRAM was improved from 102 to 105 with the N-GST buffer layer. The switching uniformity also improved compared to that of a non-buffer layer device. The improved properties that were realized are attributed to the effects of buffer layer such as controlled Cu-ion injection, internal resistor, and Joule heating confinement during the reset process. Furthermore, to verify the effect of nitrogen on the switching properties, we compared the GST and N-GST buffer layers. We believe that doped nitrogen helped to control Cu-ion injection into the resistive switching layer, and to confine the joule heating during the reset process, enabling a high on/off ratio and improved switching uniformity.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125465585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060838
J. Muller, P. Polakowski, S. Riedel, S. Mueller, E. Yurchuk, T. Mikolajick
In this paper the potential of hafnium oxide as a CMOS-compatible ferroelectric for future memory applications is assessed. The high coercive field strength of ferroelectric hafnium oxide is identified as a key parameter being crucial to device performance. It provides the unique thickness and lateral scaling potential of this novel ferroelectric, while at the same time compromises its endurance properties due to large switching fields. Considering the ambivalent nature of this parameter as well as the emerging trade-off between retention and endurance, voltage controlled operation modes and different device concepts for ferroelectric hafnium oxide are discussed.
{"title":"Ferroelectric Hafnium Oxide A Game Changer to FRAM?","authors":"J. Muller, P. Polakowski, S. Riedel, S. Mueller, E. Yurchuk, T. Mikolajick","doi":"10.1109/NVMTS.2014.7060838","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060838","url":null,"abstract":"In this paper the potential of hafnium oxide as a CMOS-compatible ferroelectric for future memory applications is assessed. The high coercive field strength of ferroelectric hafnium oxide is identified as a key parameter being crucial to device performance. It provides the unique thickness and lateral scaling potential of this novel ferroelectric, while at the same time compromises its endurance properties due to large switching fields. Considering the ambivalent nature of this parameter as well as the emerging trade-off between retention and endurance, voltage controlled operation modes and different device concepts for ferroelectric hafnium oxide are discussed.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123019913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060855
Tomoaki Yamada, Chao Sun, K. Takeuchi
Currently, solid-state drives (SSDs) are replacing hard-disk drives (HDDs) in many applications. However, SSDs write performance is low because of the NAND flash memory's characteristics. Particularly, the garbage collection (GC) page-copy overhead for the valid data greatly degrades the SSD performance. To suppress this overhead with the address remapping technology, a middleware, LBA scrambler, is proposed [3]. We evaluated the effects of the LBA scrambler with the Ext4 file system (FS). From the experimental results, the SSD performance is boosted by 20.0% with the assistance of the LBA scrambler, compared with the conventional system without LBA scrambler. Moreover, the total SSD energy consumption is reduced by 4.33% while its lifetime is enhanced by 3.56%.
{"title":"A high-performance solid-state drive by garbage collection overhead suppression","authors":"Tomoaki Yamada, Chao Sun, K. Takeuchi","doi":"10.1109/NVMTS.2014.7060855","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060855","url":null,"abstract":"Currently, solid-state drives (SSDs) are replacing hard-disk drives (HDDs) in many applications. However, SSDs write performance is low because of the NAND flash memory's characteristics. Particularly, the garbage collection (GC) page-copy overhead for the valid data greatly degrades the SSD performance. To suppress this overhead with the address remapping technology, a middleware, LBA scrambler, is proposed [3]. We evaluated the effects of the LBA scrambler with the Ext4 file system (FS). From the experimental results, the SSD performance is boosted by 20.0% with the assistance of the LBA scrambler, compared with the conventional system without LBA scrambler. Moreover, the total SSD energy consumption is reduced by 4.33% while its lifetime is enhanced by 3.56%.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131655947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060861
Sangheon Lee, Daeseok Lee, J. Woo, E. Cha, Jeonghwan Song, Jaesung Park, Kibong Moon, Y. Koo, Seokjae Lim, Jaehyuk Park, A. Prakash, H. Hwang
In this paper, the effect of the titanium oxide-based tunnel barrier on the non-linearity and switching uniformity of resistive random access memory has been investigated with the object of achieving excellent device non-linearity and reliability for cross-point array applications. To form the tunnel barrier of titanium oxide, its thickness was engineered using the deposition time. The tunnel barrier effectively controls the current flow in the devices with a tunneling mechanism that modifies the tunnel barrier thickness for non-linearity and switching reliability of devices. The tunnel barrier controls the current behavior of the device because most of the bias is applied to the tunnel barrier owing to its dominant resistance state. In addition, the tunnel barrier can exhibit uniform resistive switching during the set operation with the controlled current flow.
{"title":"Effect of TiOx-based tunnel barrier on non-linearity and switching reliability of resistive random access memory","authors":"Sangheon Lee, Daeseok Lee, J. Woo, E. Cha, Jeonghwan Song, Jaesung Park, Kibong Moon, Y. Koo, Seokjae Lim, Jaehyuk Park, A. Prakash, H. Hwang","doi":"10.1109/NVMTS.2014.7060861","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060861","url":null,"abstract":"In this paper, the effect of the titanium oxide-based tunnel barrier on the non-linearity and switching uniformity of resistive random access memory has been investigated with the object of achieving excellent device non-linearity and reliability for cross-point array applications. To form the tunnel barrier of titanium oxide, its thickness was engineered using the deposition time. The tunnel barrier effectively controls the current flow in the devices with a tunneling mechanism that modifies the tunnel barrier thickness for non-linearity and switching reliability of devices. The tunnel barrier controls the current behavior of the device because most of the bias is applied to the tunnel barrier owing to its dominant resistance state. In addition, the tunnel barrier can exhibit uniform resistive switching during the set operation with the controlled current flow.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125528214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060848
K. Whang, H. Cheong, J. W. Kim
We have developed a new plasma reactor which can generate high density plasma at low neutral gas pressure. The ion current density in the new plasma reactor is more than ten times higher than that in the conventional inductively coupled plasma (ICP) reactor at neutral gas pressure lower than 1mTorr. It is remarkable that 25nm-thick magnetic tunnel junction (MTJ) stack can be etched and a 26nm-depth oxide recess can be formed within 40 seconds with the newly designed plasma reactor.
{"title":"A fast dry etching of magnetic tunnel junction using a new plasma source","authors":"K. Whang, H. Cheong, J. W. Kim","doi":"10.1109/NVMTS.2014.7060848","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060848","url":null,"abstract":"We have developed a new plasma reactor which can generate high density plasma at low neutral gas pressure. The ion current density in the new plasma reactor is more than ten times higher than that in the conventional inductively coupled plasma (ICP) reactor at neutral gas pressure lower than 1mTorr. It is remarkable that 25nm-thick magnetic tunnel junction (MTJ) stack can be etched and a 26nm-depth oxide recess can be formed within 40 seconds with the newly designed plasma reactor.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133537186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060859
Tae-Ho Lee, Young-Jun Kwon, Jae-Gwan Kim, Sung-Kun Park, I. Cho, K. Yoo, Ji-Song Lim, Da-Som Kim, W. Choi, G. Yoon
In this paper, the program and erase characteristics of a two-transistor (2T) SONOS nonvolatile memory (NVM) cell have been described by using one-shot simulations and device simulations. In addition, a mismatched charge distribution between electrons and holes has been verified through measurements and device simulations. The program and erase (P/E) operations are performed through channel hot electron injection (CHEI) and band to band tunneling induced hot hole injection (BTBT-HHI), respectively. Because a complete erase operation can't be achieved with longer control gate (CG) lengths, the optimized CG length is a key factor in the 2T SONOS device. The proposed cell uses the whole channel to achieve good reliability during the program and erase operations. Nevertheless, it is strongly suspected that excess electrons might gradually build up in the nitride layer toward the source junction because of spatial mismatches of the injected electrons and holes during P/E cycles. This phenomenon of electron build-up has been confirmed through both device simulations and real measurements of the gate length dependence of the program and erase speeds. As a result of gradual accumulation of electrons, the cell transconductance (Gm) continues to become reduced. The degraded Gm value is also observed to be noticeably improved after a process of bake retention.
{"title":"Charge trap length dependence and transconductance characteristics of a 2T SONOS cell","authors":"Tae-Ho Lee, Young-Jun Kwon, Jae-Gwan Kim, Sung-Kun Park, I. Cho, K. Yoo, Ji-Song Lim, Da-Som Kim, W. Choi, G. Yoon","doi":"10.1109/NVMTS.2014.7060859","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060859","url":null,"abstract":"In this paper, the program and erase characteristics of a two-transistor (2T) SONOS nonvolatile memory (NVM) cell have been described by using one-shot simulations and device simulations. In addition, a mismatched charge distribution between electrons and holes has been verified through measurements and device simulations. The program and erase (P/E) operations are performed through channel hot electron injection (CHEI) and band to band tunneling induced hot hole injection (BTBT-HHI), respectively. Because a complete erase operation can't be achieved with longer control gate (CG) lengths, the optimized CG length is a key factor in the 2T SONOS device. The proposed cell uses the whole channel to achieve good reliability during the program and erase operations. Nevertheless, it is strongly suspected that excess electrons might gradually build up in the nitride layer toward the source junction because of spatial mismatches of the injected electrons and holes during P/E cycles. This phenomenon of electron build-up has been confirmed through both device simulations and real measurements of the gate length dependence of the program and erase speeds. As a result of gradual accumulation of electrons, the cell transconductance (Gm) continues to become reduced. The degraded Gm value is also observed to be noticeably improved after a process of bake retention.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131827789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060853
J. Woo, Jeonghwan Song, Kibong Moon, Seokjae Lim, Daeseok Lee, Sangheon Lee, A. Prakash, H. Hwang, J. Baek, K. Kwon
In this paper, a bipolar resistive random access memory (RRAM) device with a fab-friendly materials stack (TiN/Ti/HfO2/TiN) and process in a via-hole substrate with 200 nm cell size was successfully demonstrated on an 8-inch wafer scale. Furthermore, the robust device characteristics with reliable switching uniformity and stability were experimentally confirmed at the wafer level. Finally, from the standpoint of array architecture, the fabricated memory cell was evaluated with various selector devices such as a conventional silicon-based transistor and a newly developed tunneling-based diode device.
{"title":"8-inch wafer-scale HfOx-based RRAM for 1S-1R cross-point memory applications","authors":"J. Woo, Jeonghwan Song, Kibong Moon, Seokjae Lim, Daeseok Lee, Sangheon Lee, A. Prakash, H. Hwang, J. Baek, K. Kwon","doi":"10.1109/NVMTS.2014.7060853","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060853","url":null,"abstract":"In this paper, a bipolar resistive random access memory (RRAM) device with a fab-friendly materials stack (TiN/Ti/HfO2/TiN) and process in a via-hole substrate with 200 nm cell size was successfully demonstrated on an 8-inch wafer scale. Furthermore, the robust device characteristics with reliable switching uniformity and stability were experimentally confirmed at the wafer level. Finally, from the standpoint of array architecture, the fabricated memory cell was evaluated with various selector devices such as a conventional silicon-based transistor and a newly developed tunneling-based diode device.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060844
Jungsik Kim, Bo Jin, M. Meyyappan, Hyeongwan Oh, Junyoung Lee, T. Rim, C. Baek, Jeong-Soo Lee
In this work, the oblique single grain boundary (oSGB) in 3D NAND unit cells is simulated with various temperatures to study threshold voltage (Vth) variation due to oSGB in 3D NAND unit cell of poly-Si channel. As the temperature increases, the overall Vth variations with oSGB decrease because of thermionic effect and more free carrier from generation effect. In addition, the difference of Vth variation become larger as the oSGB leans toward source or drain sides in poly-Si channel.
{"title":"The temperature dependence of threshold voltage variations due to oblique single grain boundary in 3D NAND unit cells","authors":"Jungsik Kim, Bo Jin, M. Meyyappan, Hyeongwan Oh, Junyoung Lee, T. Rim, C. Baek, Jeong-Soo Lee","doi":"10.1109/NVMTS.2014.7060844","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060844","url":null,"abstract":"In this work, the oblique single grain boundary (oSGB) in 3D NAND unit cells is simulated with various temperatures to study threshold voltage (Vth) variation due to oSGB in 3D NAND unit cell of poly-Si channel. As the temperature increases, the overall Vth variations with oSGB decrease because of thermionic effect and more free carrier from generation effect. In addition, the difference of Vth variation become larger as the oSGB leans toward source or drain sides in poly-Si channel.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123764582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060839
D. Ielmini, S. Ambrogio, S. Balatti
Emerging memory technologies are currently under deep investigation as possible replacements of Flash memory and possible new computing memories. Among these novel technologies, resistance switching memory (RRAM) offer fast switching, low voltage operation and low power consumption. On the other hand, important questions about the scaling of RRAM currently remain unanswered. This work addresses RRAM scalability from the viewpoint of switching and read fluctuations due to localized filamentary switching. Switching variability is discussed in terms of few-defect migration, while random current noise is described by bistable defect close to the conductive filament. Models for program/read noise allow to predict the tradeoff between scaling of device size/power and variability.
{"title":"Scaling of oxide-based resistive switching devices","authors":"D. Ielmini, S. Ambrogio, S. Balatti","doi":"10.1109/NVMTS.2014.7060839","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060839","url":null,"abstract":"Emerging memory technologies are currently under deep investigation as possible replacements of Flash memory and possible new computing memories. Among these novel technologies, resistance switching memory (RRAM) offer fast switching, low voltage operation and low power consumption. On the other hand, important questions about the scaling of RRAM currently remain unanswered. This work addresses RRAM scalability from the viewpoint of switching and read fluctuations due to localized filamentary switching. Switching variability is discussed in terms of few-defect migration, while random current noise is described by bistable defect close to the conductive filament. Models for program/read noise allow to predict the tradeoff between scaling of device size/power and variability.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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