Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060868
Jin Hwan Jeong, D. Choi
In this paper, a new screened plasma-enhanced atomic vapor deposition technique was studied for increasing trench covering ability of Sb-Te phase change film. Trench-structure cells of phase change random access memory can lower thermal energy loss and thermal cross-talk among adjacent memory cells. Using a plasma sheath effect with metallic mesh inside a reaction chamber, a step coverage was greatly increased in various experimental conditions. With consideration of a model of the plasma sheath, the trench covering ability of the films was evaluated and we expect this research to provide a new deposition method for the fine control of step coverage.
{"title":"New screened plasma-enhanced atomic vapor deposition to improve trench covering ability of SbTe films","authors":"Jin Hwan Jeong, D. Choi","doi":"10.1109/NVMTS.2014.7060868","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060868","url":null,"abstract":"In this paper, a new screened plasma-enhanced atomic vapor deposition technique was studied for increasing trench covering ability of Sb-Te phase change film. Trench-structure cells of phase change random access memory can lower thermal energy loss and thermal cross-talk among adjacent memory cells. Using a plasma sheath effect with metallic mesh inside a reaction chamber, a step coverage was greatly increased in various experimental conditions. With consideration of a model of the plasma sheath, the trench covering ability of the films was evaluated and we expect this research to provide a new deposition method for the fine control of step coverage.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060858
Sung-Kun Park, Nam-Yoon Kim, Kwang-il Choi, Jae-Gwan Kim, I. Cho, K. Yoo, Eun-Mee Kwon, Sangyong Kim
The novel select gate lateral coupling (SGLC) cell has a single poly structure and operates using a lateral coupling between the floating gate (FG) and the select gate (SG) without additional processes on a base platform. In this paper, we have fabricated a pure logic CMOS processed SGLC cell for the first time and compared it with an HVCMOS processed SGLC cell. Because of the thinner gate oxide, the pure logic process fabricated SGLC cell has a lower coupling value than that of the HVCMOS process fabricated cell. However, the logic CMOS process fabricated cell shows a higher current performance than the HVCMOS process fabricated cell having a thicker gate oxide. Thanks to the inverse relationship between the coupling ratio and cell current, and the additional back bias effect, the logic CMOS processed cell gives comparable performance in terms of the programming speed, program-erase threshold voltage (VT) window and cell current. Both types of cells show more than 10 years of data retention lifetime at 85°C.
{"title":"Characteristics comparison of standard logic and HVCMOS processed SGLC embedded NVM","authors":"Sung-Kun Park, Nam-Yoon Kim, Kwang-il Choi, Jae-Gwan Kim, I. Cho, K. Yoo, Eun-Mee Kwon, Sangyong Kim","doi":"10.1109/NVMTS.2014.7060858","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060858","url":null,"abstract":"The novel select gate lateral coupling (SGLC) cell has a single poly structure and operates using a lateral coupling between the floating gate (FG) and the select gate (SG) without additional processes on a base platform. In this paper, we have fabricated a pure logic CMOS processed SGLC cell for the first time and compared it with an HVCMOS processed SGLC cell. Because of the thinner gate oxide, the pure logic process fabricated SGLC cell has a lower coupling value than that of the HVCMOS process fabricated cell. However, the logic CMOS process fabricated cell shows a higher current performance than the HVCMOS process fabricated cell having a thicker gate oxide. Thanks to the inverse relationship between the coupling ratio and cell current, and the additional back bias effect, the logic CMOS processed cell gives comparable performance in terms of the programming speed, program-erase threshold voltage (VT) window and cell current. Both types of cells show more than 10 years of data retention lifetime at 85°C.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060834
Kejie Huang, Rong Zhao
The computing systems are scaling down 100 times every decade, while the processing power doubles every two years. As a result, the power density has been the one of the most critical issues that limit the modern processors. Therefore, new technologies and computer architectures are under tensed development to reduce the power consumption. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power issue. Meanwhile, it could be stacked on top of CMOS circuits to break the bottleneck of memory bandwidth limitation. This paper presents new designs of the non-volatile logic gates, which are compared with the conventional designs including non-volatile flip-flops, fully non-volatile logic gates, and hybrid non-volatile logic gates. The simulation results show that proposed non-volatile logic gates have the advantage of low power, especially at the low switching frequency. The proposed XOR has reduced the power consumption of XOR in the conventional load/save systems by 45% at high switching frequency, and 92% at 100 kHz. The proposed designs also show the advantage of reconfigurability, which makes the designs more flexible and robust.
{"title":"Low power computing using STT-MRAM","authors":"Kejie Huang, Rong Zhao","doi":"10.1109/NVMTS.2014.7060834","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060834","url":null,"abstract":"The computing systems are scaling down 100 times every decade, while the processing power doubles every two years. As a result, the power density has been the one of the most critical issues that limit the modern processors. Therefore, new technologies and computer architectures are under tensed development to reduce the power consumption. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power issue. Meanwhile, it could be stacked on top of CMOS circuits to break the bottleneck of memory bandwidth limitation. This paper presents new designs of the non-volatile logic gates, which are compared with the conventional designs including non-volatile flip-flops, fully non-volatile logic gates, and hybrid non-volatile logic gates. The simulation results show that proposed non-volatile logic gates have the advantage of low power, especially at the low switching frequency. The proposed XOR has reduced the power consumption of XOR in the conventional load/save systems by 45% at high switching frequency, and 92% at 100 kHz. The proposed designs also show the advantage of reconfigurability, which makes the designs more flexible and robust.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124753697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060843
W. Yoo, T. Ishigaki, T. Ueda, K. Kang, N. Kwak, D. Sheen, Sung Soon Kim, M. Ko, W. S. Shin, Byung-Seok Lee, S. Yeom, S. Park
Raman spectroscopy was used for characterizing poly-Si after thermal annealing of chemical vapor deposited (CVD) thin a-Si films in the vertical channel region of 3D V-NAND device wafers using various annealing conditions and techniques. Raman spectra, indicating crystallization of a-Si films and grain growth of poly-Si with respect to annealing conditions and techniques, was measured using a multiwavelength Raman spectroscopy system.
{"title":"Grain size monitoring of 3D flash memory channel poly-Si using multiwavelength Raman spectroscopy","authors":"W. Yoo, T. Ishigaki, T. Ueda, K. Kang, N. Kwak, D. Sheen, Sung Soon Kim, M. Ko, W. S. Shin, Byung-Seok Lee, S. Yeom, S. Park","doi":"10.1109/NVMTS.2014.7060843","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060843","url":null,"abstract":"Raman spectroscopy was used for characterizing poly-Si after thermal annealing of chemical vapor deposited (CVD) thin a-Si films in the vertical channel region of 3D V-NAND device wafers using various annealing conditions and techniques. Raman spectra, indicating crystallization of a-Si films and grain growth of poly-Si with respect to annealing conditions and techniques, was measured using a multiwavelength Raman spectroscopy system.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060842
E. Chua, C. C. Yeap, M. Li, K. Lim, L. Law, W. J. Wang, E. Yeo, F. Ernult
Varying ZrO2 doped GeTe phase change material of atomic percent greater than 10% were deposited and characterized. It was discovered that the crystallization of amorphous doped GeTe is suppressed by the incorporation of ZrO2 at lower concentration but the crystallization improves as the concentration increases as depicted by the activation energy for different concentration. Thus it resulted in an optimum concentration for highest activation energy for better stability. ZrO2 concentration at 11% which has the highest activation energy of 3.64 eV and crystallization temperature of 210 °C with 10 years retention of 135 °C was fabricated, tested and compared with GeTe. Doped GeTe achieved power reduction of 55% as compared to GeTe and achieved endurance of 104 cycles.
{"title":"ZrO2 doped GeTe for aerospace applications","authors":"E. Chua, C. C. Yeap, M. Li, K. Lim, L. Law, W. J. Wang, E. Yeo, F. Ernult","doi":"10.1109/NVMTS.2014.7060842","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060842","url":null,"abstract":"Varying ZrO2 doped GeTe phase change material of atomic percent greater than 10% were deposited and characterized. It was discovered that the crystallization of amorphous doped GeTe is suppressed by the incorporation of ZrO2 at lower concentration but the crystallization improves as the concentration increases as depicted by the activation energy for different concentration. Thus it resulted in an optimum concentration for highest activation energy for better stability. ZrO2 concentration at 11% which has the highest activation energy of 3.64 eV and crystallization temperature of 210 °C with 10 years retention of 135 °C was fabricated, tested and compared with GeTe. Doped GeTe achieved power reduction of 55% as compared to GeTe and achieved endurance of 104 cycles.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127450486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060864
V. Kumar, U. Ganguly
Traditionally, DC power reduction based on half-select based sneak-path leakage reduction has been the primary metric to evaluate the effectiveness of a selector technology in RRAM arrays. In this paper, we show that dynamic power is comparable and even dominant consideration. We compare MIM selector with NPN technology to compare DC and dynamic power. MIM selector has poor non-linearity and high capacitance due to the implementation with thin high-k dielectrics to ensure high on-current density. NPN selector has better non-linearity as well as lower capacitance as p-region can be thick without compromising non-linearity or on-current density. Consequently overall NPN has lower power based on both DC and dynamic power considerations. In NPN technology, dynamic power is comparable to DC power at sub-30nm nodes. It dominates at sub-15nm node at 100MHz while it dominates at sub-50nm nodes at 1GHz. Thus, selector technology needs to be evaluated and even optimized for dynamic power.
{"title":"Impact of MIM versus NPN selector on dynamic power in bipolar RRAM array","authors":"V. Kumar, U. Ganguly","doi":"10.1109/NVMTS.2014.7060864","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060864","url":null,"abstract":"Traditionally, DC power reduction based on half-select based sneak-path leakage reduction has been the primary metric to evaluate the effectiveness of a selector technology in RRAM arrays. In this paper, we show that dynamic power is comparable and even dominant consideration. We compare MIM selector with NPN technology to compare DC and dynamic power. MIM selector has poor non-linearity and high capacitance due to the implementation with thin high-k dielectrics to ensure high on-current density. NPN selector has better non-linearity as well as lower capacitance as p-region can be thick without compromising non-linearity or on-current density. Consequently overall NPN has lower power based on both DC and dynamic power considerations. In NPN technology, dynamic power is comparable to DC power at sub-30nm nodes. It dominates at sub-15nm node at 100MHz while it dominates at sub-50nm nodes at 1GHz. Thus, selector technology needs to be evaluated and even optimized for dynamic power.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128018571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060841
V. Zhuo, Y. Jiang, J. Robertson
Resistive switching behavior of TaOx-based resistive switching devices is investigated at temperatures of 25°C to 300°C. Both the set and reset voltages decrease with increasing temperature. Long retention (>10 years at 150°C) and good thermal stability were achieved for the TaOx-based RRAM. At elevated temperatures from 240°C to 300°C, the low resistance state exhibits no significant change with time. In contrast, the high resistance state (HRS) shows degradation followed by sudden failure. The HRS failure times for both TaOx and Ge/TaOx devices exhibit Arrhenius dependence with activation energies of 1.45 eV and 1.27 eV, respectively.
{"title":"Thermal stability investigation in highly- uniform and low-voltage tantalum oxide-based RRAM","authors":"V. Zhuo, Y. Jiang, J. Robertson","doi":"10.1109/NVMTS.2014.7060841","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060841","url":null,"abstract":"Resistive switching behavior of TaO<sub>x</sub>-based resistive switching devices is investigated at temperatures of 25°C to 300°C. Both the set and reset voltages decrease with increasing temperature. Long retention (>10 years at 150°C) and good thermal stability were achieved for the TaO<sub>x</sub>-based RRAM. At elevated temperatures from 240°C to 300°C, the low resistance state exhibits no significant change with time. In contrast, the high resistance state (HRS) shows degradation followed by sudden failure. The HRS failure times for both TaO<sub>x</sub> and Ge/TaO<sub>x</sub> devices exhibit Arrhenius dependence with activation energies of 1.45 eV and 1.27 eV, respectively.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115180254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060860
W. Kang, Yuanqing Cheng, Youguang Zhang, D. Ravelosona, Weisheng Zhao
Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend the Moore's Law beyond the CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide R&D attention. However as technology scales (e.g., below 40 nm), the process variations introduce big read reliability challenges for STT-MRAM due to the reduced sensing margin (SM) and the increased read disturbance (RD). Therefore the readability, rather than writability, will become an ultimate bottleneck of STT-MRAM at technology nodes below 40 nm. In this paper, we firstly analyze the technology scaling trends on the STT-MRAM read performance; and then we present a RD detection circuit for the case where read current is lower than the write current (e.g., >30 nm); finally we propose a reconfigurable cell design based on the differential sensing scheme to improve the SM and to reduce the RD simultaneously, for the case where read current approaches the write current (e.g., <;30 nm).
{"title":"Readability challenges in deeply scaled STT-MRAM","authors":"W. Kang, Yuanqing Cheng, Youguang Zhang, D. Ravelosona, Weisheng Zhao","doi":"10.1109/NVMTS.2014.7060860","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060860","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend the Moore's Law beyond the CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide R&D attention. However as technology scales (e.g., below 40 nm), the process variations introduce big read reliability challenges for STT-MRAM due to the reduced sensing margin (SM) and the increased read disturbance (RD). Therefore the readability, rather than writability, will become an ultimate bottleneck of STT-MRAM at technology nodes below 40 nm. In this paper, we firstly analyze the technology scaling trends on the STT-MRAM read performance; and then we present a RD detection circuit for the case where read current is lower than the write current (e.g., >30 nm); finally we propose a reconfigurable cell design based on the differential sensing scheme to improve the SM and to reduce the RD simultaneously, for the case where read current approaches the write current (e.g., <;30 nm).","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123005719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060840
Ki-Tae Park, D. Byeon, Doogon Kim
In this work, we present a 3D 128Gb 2bit/cell vertical-NAND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications. Also, extended endurance of 35K is achieved with 36MB/s of write throughput for data center and enterprise SSD applications. And 2nd generation of 3D V-NAND opens up a whole new world at SSD endurance, density and battery life for portables.
{"title":"A world's first product of three-dimensional vertical NAND Flash memory and beyond","authors":"Ki-Tae Park, D. Byeon, Doogon Kim","doi":"10.1109/NVMTS.2014.7060840","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060840","url":null,"abstract":"In this work, we present a 3D 128Gb 2bit/cell vertical-NAND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications. Also, extended endurance of 35K is achieved with 36MB/s of write throughput for data center and enterprise SSD applications. And 2nd generation of 3D V-NAND opens up a whole new world at SSD endurance, density and battery life for portables.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122330984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/NVMTS.2014.7060851
M. Li, Y. Jiang, V. Y. Zhuo, E. Yeo, L. Law, K. Lim
Ta/TaOx-based Resistive Random Access Memory (RRAM) is studied using current-sweeping (I-sweep) DC switching operation. The self-compliance SET program is achieved to prevent the device from current overshoot. The SET current and voltage are comparable with those measured by the conventional voltage-sweeping (V-sweep) operation, but better uniformity is realized. It is found that the high high-resistance-state (HRS) resistance results in lower I-sweep SET current but higher SET voltage. As opposed to the V-sweep switching process, the I-sweep SET is a gradual process. Therefore, the low-resistance-state (LRS) resistance can be controlled easily and reliably. It will be beneficial to a new multilevel cell design for high density memory applications.
{"title":"Self-compliance SET switching and multilevel TaOx resistive memory by current-sweep operation","authors":"M. Li, Y. Jiang, V. Y. Zhuo, E. Yeo, L. Law, K. Lim","doi":"10.1109/NVMTS.2014.7060851","DOIUrl":"https://doi.org/10.1109/NVMTS.2014.7060851","url":null,"abstract":"Ta/TaOx-based Resistive Random Access Memory (RRAM) is studied using current-sweeping (I-sweep) DC switching operation. The self-compliance SET program is achieved to prevent the device from current overshoot. The SET current and voltage are comparable with those measured by the conventional voltage-sweeping (V-sweep) operation, but better uniformity is realized. It is found that the high high-resistance-state (HRS) resistance results in lower I-sweep SET current but higher SET voltage. As opposed to the V-sweep switching process, the I-sweep SET is a gradual process. Therefore, the low-resistance-state (LRS) resistance can be controlled easily and reliably. It will be beneficial to a new multilevel cell design for high density memory applications.","PeriodicalId":275170,"journal":{"name":"2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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