Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145548
F. Garbuglia, D. Spina, Torsten Reuschel, C. Schuster, D. Deschrijver, T. Dhaene
In this paper, we present a novel technique to model wide-band scattering parameter (S-parameter) curves of high-speed digital interconnects. The proposed technique utilizes a new kernel function with periodic components for Gaussian process (GP) models. After proper training, the GP models are able to predict the S-parameter values at arbitrary frequency points inside the trained interval. The performance of the proposed technique is reviewed by means of correlation with standard Gaussian Processes with squared exponential kernel and Matern kernel. Results for the proposed technique show an increased prediction accuracy when applied to interconnects.
{"title":"Modeling S-parameters of Interconnects using Periodic Gaussian Process Kernels","authors":"F. Garbuglia, D. Spina, Torsten Reuschel, C. Schuster, D. Deschrijver, T. Dhaene","doi":"10.1109/SPI57109.2023.10145548","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145548","url":null,"abstract":"In this paper, we present a novel technique to model wide-band scattering parameter (S-parameter) curves of high-speed digital interconnects. The proposed technique utilizes a new kernel function with periodic components for Gaussian process (GP) models. After proper training, the GP models are able to predict the S-parameter values at arbitrary frequency points inside the trained interval. The performance of the proposed technique is reviewed by means of correlation with standard Gaussian Processes with squared exponential kernel and Matern kernel. Results for the proposed technique show an increased prediction accuracy when applied to interconnects.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122803593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145575
P. Manfredi
Machine learning methods are attracting a great interest as surrogate modeling tools for signal and power integrity problems. However, an open issue is that it is often difficult to assess the model trustworthiness in generalizing beyond the training data. In this regard, Gaussian process (GP) models notably provide an indication of the prediction confidence due to the limited amount of training samples. They are wildly used as surrogates in design exploration, optimization, and uncertainty quantification tasks. Nevertheless, their prediction confidence does not account for the uncertainty introduced by the estimation of the GP parameters, which is also part of the training process. In this paper, we discuss two improved GP formulations that take into account the additional uncertainty related to the estimation of (some) GP parameters, thereby leading to more reliable and conservative confidence levels. The proposed framework is applied to the uncertainty quantification of the maximum transient crosstalk in a microstrip interconnect.
{"title":"Conservative Surrogate Modeling of Crosstalk with Application to Uncertainty Quantification","authors":"P. Manfredi","doi":"10.1109/SPI57109.2023.10145575","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145575","url":null,"abstract":"Machine learning methods are attracting a great interest as surrogate modeling tools for signal and power integrity problems. However, an open issue is that it is often difficult to assess the model trustworthiness in generalizing beyond the training data. In this regard, Gaussian process (GP) models notably provide an indication of the prediction confidence due to the limited amount of training samples. They are wildly used as surrogates in design exploration, optimization, and uncertainty quantification tasks. Nevertheless, their prediction confidence does not account for the uncertainty introduced by the estimation of the GP parameters, which is also part of the training process. In this paper, we discuss two improved GP formulations that take into account the additional uncertainty related to the estimation of (some) GP parameters, thereby leading to more reliable and conservative confidence levels. The proposed framework is applied to the uncertainty quantification of the maximum transient crosstalk in a microstrip interconnect.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145555
G. Phung, U. Arz, T. D. Pham, D. Allal, K. Lahbacha, G. Miele, A. Maffucci
Reliable high-speed data transmission and high-speed electronic components require a high level of Signal Integrity (SI) to handle hundreds of channels and thousands of input/output connections on a single chip. Due to the increasing demand for high-density layouts on a single chip, crosstalk effects are becoming critical for the system performance. This paper investigates crosstalk effects for coupled thin-film microstrip lines (TFMSL) in the frequency range up to 50 GHz. Neighborhood effects on the propagation characteristics of the common and the differential modes and mode conversion losses are discussed, and furthermore recommendations for the mitigation of unwanted effects are provided.
{"title":"Recommendations for the Design of Differential Thin-Film Microstrip Lines","authors":"G. Phung, U. Arz, T. D. Pham, D. Allal, K. Lahbacha, G. Miele, A. Maffucci","doi":"10.1109/SPI57109.2023.10145555","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145555","url":null,"abstract":"Reliable high-speed data transmission and high-speed electronic components require a high level of Signal Integrity (SI) to handle hundreds of channels and thousands of input/output connections on a single chip. Due to the increasing demand for high-density layouts on a single chip, crosstalk effects are becoming critical for the system performance. This paper investigates crosstalk effects for coupled thin-film microstrip lines (TFMSL) in the frequency range up to 50 GHz. Neighborhood effects on the propagation characteristics of the common and the differential modes and mode conversion losses are discussed, and furthermore recommendations for the mitigation of unwanted effects are provided.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145544
V. Verma, J. N. Tripathi
This study discusses and introduces the impact of variability on power supply-induced jitter in integrated circuits. It presents an analytical approach to model timing uncertainty in the output response of CMOS inverters due to process variations as well as power supply noise. The proposed theory is verified with both simulation and measurement. The proposed approach is not only limited to jitter estimation but it can also be used to analyze the variability issues in CMOS circuits.
{"title":"Variability-Aware Modeling of Supply Induced Jitter in CMOS Inverters","authors":"V. Verma, J. N. Tripathi","doi":"10.1109/SPI57109.2023.10145544","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145544","url":null,"abstract":"This study discusses and introduces the impact of variability on power supply-induced jitter in integrated circuits. It presents an analytical approach to model timing uncertainty in the output response of CMOS inverters due to process variations as well as power supply noise. The proposed theory is verified with both simulation and measurement. The proposed approach is not only limited to jitter estimation but it can also be used to analyze the variability issues in CMOS circuits.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"630 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115111551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145577
Nicole Selezinski, Xiaomin Duan, Katharina Scharff, D. Kaller, H. Harrer
It has been shown previously that switching the polarity of differential vias can lead to a cancellation of differential crosstalk. In this paper a printed circuit board structure with different routing length differences between victim and aggressor is investigated, to determine the effect of length differences on the crosstalk cancellation. The differential crosstalk of the proposed design is simulated with the Finite Element Method and measured with a vector network analyzer. It is verified that the crosstalk cancellation depends on the length differences.
{"title":"Routing Length Impact on Differential Via Crosstalk Cancellation","authors":"Nicole Selezinski, Xiaomin Duan, Katharina Scharff, D. Kaller, H. Harrer","doi":"10.1109/SPI57109.2023.10145577","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145577","url":null,"abstract":"It has been shown previously that switching the polarity of differential vias can lead to a cancellation of differential crosstalk. In this paper a printed circuit board structure with different routing length differences between victim and aggressor is investigated, to determine the effect of length differences on the crosstalk cancellation. The differential crosstalk of the proposed design is simulated with the Finite Element Method and measured with a vector network analyzer. It is verified that the crosstalk cancellation depends on the length differences.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"444 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116407412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145552
Harini Manoharan, Frank Ebert
Power Distribution Networks (PDNs) in high-speed applications are very important for proper functioning of the IC's. In this paper, the impact of VRM, PCB, IC package and DIE parasitic on PDN is analyzed and how to optimize the PCB in order to achieve the target impedance for high current requirements. The holistic signal integrity approach of considering the coupling of DDR power noise on the parallel interface, affecting the timing and eye quality is studied.
{"title":"Power Integrity Analysis for High Current Digital Core & DDR Power and PDN Noise Impact on the LpDDR4 Timing Analysis for ADAS Automotive Application","authors":"Harini Manoharan, Frank Ebert","doi":"10.1109/SPI57109.2023.10145552","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145552","url":null,"abstract":"Power Distribution Networks (PDNs) in high-speed applications are very important for proper functioning of the IC's. In this paper, the impact of VRM, PCB, IC package and DIE parasitic on PDN is analyzed and how to optimize the PCB in order to achieve the target impedance for high current requirements. The holistic signal integrity approach of considering the coupling of DDR power noise on the parallel interface, affecting the timing and eye quality is studied.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"726 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145542
Robin Sercu, H. Barnes
Calculating the DC IR drop for a power distribution network with cascaded dc-dc converters presents some unique challenges. The buck regulator dc-dc converters have a very dynamic large signal switching behavior that is load dependent and must be averaged to DC for the DC IR drop calculation. When cascading multiple regulators in series, the downstream regulator acts as the load for the upstream regulator. An iterative approach can be used to calculate the state of the final regulator stage for a given sink load, and then use this regulator's input current as the sink for the calculation of the DC state of the upstream regulator. This iterative approach with a simplified model for the DC regulator can be as much as $40mathrm{x}$ faster than solving in the transient domain.
{"title":"DC IR Drop Steady State Estimate for Cascaded Switching Regulators","authors":"Robin Sercu, H. Barnes","doi":"10.1109/SPI57109.2023.10145542","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145542","url":null,"abstract":"Calculating the DC IR drop for a power distribution network with cascaded dc-dc converters presents some unique challenges. The buck regulator dc-dc converters have a very dynamic large signal switching behavior that is load dependent and must be averaged to DC for the DC IR drop calculation. When cascading multiple regulators in series, the downstream regulator acts as the load for the upstream regulator. An iterative approach can be used to calculate the state of the final regulator stage for a given sink load, and then use this regulator's input current as the sink for the calculation of the DC state of the upstream regulator. This iterative approach with a simplified model for the DC regulator can be as much as $40mathrm{x}$ faster than solving in the transient domain.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"41 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128484207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145545
A. Plot, Benoît Goral, P. Besnier
This article presents a methodology using machine learning techniques for defining printed circuit board (PCB) design rules in order to reduce signal integrity (SI) or electro-magnetic interference (EMI) issues. The scenario illustrating the situation for which these rules must be defined is modelled with a 3D EM solver available on the market and simulations are run with varying parameters in order to obtain a representative sample of the design space. This data set is then used to train a surrogate model (i.e. a metamodel) of the scenario based on kriging algorithm. Using this surrogate model, more than ten thousands of simulations are computed in a decent time. The surrogate model estimations allow to estimate the sensitivity of the varying parameters with respect to some specifications (crosstalk level and insertion loss). Finally, an analysis of output values for which some requirements (crosstalk level, insertion) loss are not fulfilled provide some insights about possible adjustment of guidelines in terms of parameter ranges. Finally, a practical design example is given to illustrate the methodology.
{"title":"Machine Learning Techniques for Defining Routing Rules for PCB Design","authors":"A. Plot, Benoît Goral, P. Besnier","doi":"10.1109/SPI57109.2023.10145545","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145545","url":null,"abstract":"This article presents a methodology using machine learning techniques for defining printed circuit board (PCB) design rules in order to reduce signal integrity (SI) or electro-magnetic interference (EMI) issues. The scenario illustrating the situation for which these rules must be defined is modelled with a 3D EM solver available on the market and simulations are run with varying parameters in order to obtain a representative sample of the design space. This data set is then used to train a surrogate model (i.e. a metamodel) of the scenario based on kriging algorithm. Using this surrogate model, more than ten thousands of simulations are computed in a decent time. The surrogate model estimations allow to estimate the sensitivity of the varying parameters with respect to some specifications (crosstalk level and insertion loss). Finally, an analysis of output values for which some requirements (crosstalk level, insertion) loss are not fulfilled provide some insights about possible adjustment of guidelines in terms of parameter ranges. Finally, a practical design example is given to illustrate the methodology.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133928554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145523
José Moreira, S. Churkin, O. Zhuravleva
This paper presents a calibration kit designed for a double-ridged waveguide. This custom designed double-ridged waveguide was developed to address the 5G-FR2 standard frequency band of 24 to 53 GHz. It is used as a blindmating interconnect in over-the-air high-volume manufacturing testing of antenna in package devices for 5G-FR2 applications. A TRL calibration kit design is presented together with the measured results obtained with a manufactured prototype of the calibration kit.
{"title":"A Calibration Kit for a 5G-FR2 Band Double-Ridged Waveguide","authors":"José Moreira, S. Churkin, O. Zhuravleva","doi":"10.1109/SPI57109.2023.10145523","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145523","url":null,"abstract":"This paper presents a calibration kit designed for a double-ridged waveguide. This custom designed double-ridged waveguide was developed to address the 5G-FR2 standard frequency band of 24 to 53 GHz. It is used as a blindmating interconnect in over-the-air high-volume manufacturing testing of antenna in package devices for 5G-FR2 applications. A TRL calibration kit design is presented together with the measured results obtained with a manufactured prototype of the calibration kit.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126049007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145565
Matthew B. Leslie, Justin Butterfield, Randy Wolff
The inclusion of a receiver decision feedback equalizer (DFE) to Double Data Rate 5(DDRS) synchronous dynamic random access memory (SDRAM)s has increased the complexity of signal integrity (SI) simulation compared to previous DDR technologies. In response, the I/O Buffer Information Specification (IBIS) version 7.1 enables an IBIS algorithmic modeling interface (IBIS-AMI) receiver model to accept an external clock signal. A novel simulation flow is developed which accounts for both DQ (data) signals and their associated DQS (clock/strobe) signal in the evaluation of DDR5 data write and read operations. The effects of including DQS into SI simulation of DDR5 systems are discussed by examining the resulting eye diagrams. It is observed that for system timing margins, the SI quality of the strobe signal becomes just as important as the data signals.
{"title":"Simulating DDR5 Systems with Clocked Receivers","authors":"Matthew B. Leslie, Justin Butterfield, Randy Wolff","doi":"10.1109/SPI57109.2023.10145565","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145565","url":null,"abstract":"The inclusion of a receiver decision feedback equalizer (DFE) to Double Data Rate 5(DDRS) synchronous dynamic random access memory (SDRAM)s has increased the complexity of signal integrity (SI) simulation compared to previous DDR technologies. In response, the I/O Buffer Information Specification (IBIS) version 7.1 enables an IBIS algorithmic modeling interface (IBIS-AMI) receiver model to accept an external clock signal. A novel simulation flow is developed which accounts for both DQ (data) signals and their associated DQS (clock/strobe) signal in the evaluation of DDR5 data write and read operations. The effects of including DQS into SI simulation of DDR5 systems are discussed by examining the resulting eye diagrams. It is observed that for system timing margins, the SI quality of the strobe signal becomes just as important as the data signals.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125967893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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