Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145573
M. Telescu, R. Trinchero, N. Tanguy, I. Stievano
This paper focuses on the generation of a compact and accurate model of the eye aperture for a differential textile interconnect. The considered eye metric is computed through a simple and effective procedure based on a polygonal approximation of the clean inner eye area. Least squares support vector machine regression is used, yielding a fast and accurate surrogate model of the link, providing a quantitative information of the data communication quality. The generated model turns out to be a parametric description which is used in the framework of stochastic analysis and uncertainty quantification, allowing to take into account the effects of the variation of the electrical and geometrical parameters of the link. The accuracy and convergence of the proposed machine learning solution are thoroughly discussed.
{"title":"Surrogate Eye Modeling for the Statistical Assessment of a Smart Textile Interconnect","authors":"M. Telescu, R. Trinchero, N. Tanguy, I. Stievano","doi":"10.1109/SPI57109.2023.10145573","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145573","url":null,"abstract":"This paper focuses on the generation of a compact and accurate model of the eye aperture for a differential textile interconnect. The considered eye metric is computed through a simple and effective procedure based on a polygonal approximation of the clean inner eye area. Least squares support vector machine regression is used, yielding a fast and accurate surrogate model of the link, providing a quantitative information of the data communication quality. The generated model turns out to be a parametric description which is used in the framework of stochastic analysis and uncertainty quantification, allowing to take into account the effects of the variation of the electrical and geometrical parameters of the link. The accuracy and convergence of the proposed machine learning solution are thoroughly discussed.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123998104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145539
Yi Zhou, Bobi Shi, J. Schutt-Ainé
Crosstalk in high-speed links is a serious concern as the operating frequencies becomes higher and with increasing levels of integration. Eye diagrams have revealed to be a useful tool for assessing the quality of a channel and as such, should include the effects of crosstalk. In this paper, we propose a fast and accurate eye diagram simulation method for crosstalk-included noise based on the latency insertion method (LIM). The simulation results and the speed are compared with those from commercial software.
{"title":"Fast Latency-Insertion-Method-Based Eye Diagram Simulation Incorporating Crosstalk","authors":"Yi Zhou, Bobi Shi, J. Schutt-Ainé","doi":"10.1109/SPI57109.2023.10145539","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145539","url":null,"abstract":"Crosstalk in high-speed links is a serious concern as the operating frequencies becomes higher and with increasing levels of integration. Eye diagrams have revealed to be a useful tool for assessing the quality of a channel and as such, should include the effects of crosstalk. In this paper, we propose a fast and accurate eye diagram simulation method for crosstalk-included noise based on the latency insertion method (LIM). The simulation results and the speed are compared with those from commercial software.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145521
Jose Enrique Hernandez Bonilla, G. Alavi, Cheng Yang, C. Schuster
In this study, the effect of harsh environments on the insertion loss profile of automotive-grade high-speed interconnects was studied. Measurements under three different use conditions were performed to study the effect of humidity and temperature in signal integrity performance. Measurements at nominal conditions were used to extract the insertion loss per inch using two different de-embedding methods. Temperature and humidity variations were applied to three printed circuit board stack-ups fabricated with different base materials and copper foils. The insertion loss was measured for the environment changes and compared between the boards. An increase in the insertion loss profile was observed for temperature and humidity variations in all the boards.
{"title":"Measurement of Temperature and Humidity Dependence of Automotive-Grade Interconnects","authors":"Jose Enrique Hernandez Bonilla, G. Alavi, Cheng Yang, C. Schuster","doi":"10.1109/SPI57109.2023.10145521","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145521","url":null,"abstract":"In this study, the effect of harsh environments on the insertion loss profile of automotive-grade high-speed interconnects was studied. Measurements under three different use conditions were performed to study the effect of humidity and temperature in signal integrity performance. Measurements at nominal conditions were used to extract the insertion loss per inch using two different de-embedding methods. Temperature and humidity variations were applied to three printed circuit board stack-ups fabricated with different base materials and copper foils. The insertion loss was measured for the environment changes and compared between the boards. An increase in the insertion loss profile was observed for temperature and humidity variations in all the boards.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133420642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145572
Martijn Huynen, R. Waeytens, Dries Bosman, M. Gossye, H. Rogier, D. Ginste
In this contribution we study the propagation constant of interconnects subject to line edge roughness by means of an efficient stochastic framework. By employing the stochastic testing method, we succeed in limiting the number of calls to the full-wave electromagnetic field solver at the core of the system. Additionally, the computationally burdensome solution of the eigenvalue problem is eased by reducing its order through projection on an appropriate basis. The resulting two-step accel-eration leads to an effective approach to assess the effect of line edge roughness on the characteristics of interconnects. The novel framework is applied to a rough rectangular waveguide and a microstrip.
{"title":"Reduced-Order Stochastic Testing of Interconnects Subject to Line Edge Roughness","authors":"Martijn Huynen, R. Waeytens, Dries Bosman, M. Gossye, H. Rogier, D. Ginste","doi":"10.1109/SPI57109.2023.10145572","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145572","url":null,"abstract":"In this contribution we study the propagation constant of interconnects subject to line edge roughness by means of an efficient stochastic framework. By employing the stochastic testing method, we succeed in limiting the number of calls to the full-wave electromagnetic field solver at the core of the system. Additionally, the computationally burdensome solution of the eigenvalue problem is eased by reducing its order through projection on an appropriate basis. The resulting two-step accel-eration leads to an effective approach to assess the effect of line edge roughness on the characteristics of interconnects. The novel framework is applied to a rough rectangular waveguide and a microstrip.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127511350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145547
F. de Paulis, Rick Rabinovich, M. Resso, Samuel Kocsis
The λ/4 resonance due to unwanted stub effect along the signal path can play a significant role for the Chip-to-Module interface running at 224 Gbps in PAM4 which involves a typical optical module connector. A OSFP connector example is considered in this paper and the impact of the residual stub given by the spring wipe is analyzed. The stub resonance is predicted analytically with acceptable error, and the stub notch resonance is extracted from full-wave simulations for several cases of wipe length. A length limit is derived in order to keep the notch frequency of the resonating stub outside the usable bandwidth practically set at 0.75 times the baud rate for the PAM 4 type of modulation.
{"title":"Bandwidth Limits of Connector Wipe Stub for Reliable 224 Gbps Signaling","authors":"F. de Paulis, Rick Rabinovich, M. Resso, Samuel Kocsis","doi":"10.1109/SPI57109.2023.10145547","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145547","url":null,"abstract":"The λ/4 resonance due to unwanted stub effect along the signal path can play a significant role for the Chip-to-Module interface running at 224 Gbps in PAM4 which involves a typical optical module connector. A OSFP connector example is considered in this paper and the impact of the residual stub given by the spring wipe is analyzed. The stub resonance is predicted analytically with acceptable error, and the stub notch resonance is extracted from full-wave simulations for several cases of wipe length. A length limit is derived in order to keep the notch frequency of the resonating stub outside the usable bandwidth practically set at 0.75 times the baud rate for the PAM 4 type of modulation.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114139867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145574
Daniel Uebach, Thomas Kühler, E. Griese
The field-assisted diffusion process is the commonly utilized manufacturing technology for fabricating integrated directional couplers that are used for bidirectional chip-to-chip communication in Electro-Optical Printed Circuit Boards (EOPCBs) [1]. Since an ion depletion occurs in regions where two waveguides approach each other due to superimposed fields, two techniques to compensate this ion depletion are introduced. Both methods are then investigated as an optimization approach for the design of an integrated directional coupler.
{"title":"Techniques to Compensate Ion Depletion in the Coupling Region of Directional Couplers Manufactured by Field-Assisted Diffusion","authors":"Daniel Uebach, Thomas Kühler, E. Griese","doi":"10.1109/SPI57109.2023.10145574","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145574","url":null,"abstract":"The field-assisted diffusion process is the commonly utilized manufacturing technology for fabricating integrated directional couplers that are used for bidirectional chip-to-chip communication in Electro-Optical Printed Circuit Boards (EOPCBs) [1]. Since an ion depletion occurs in regions where two waveguides approach each other due to superimposed fields, two techniques to compensate this ion depletion are introduced. Both methods are then investigated as an optimization approach for the design of an integrated directional coupler.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131676537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145570
Ta-Yeh Lin, Shuw-Guann Lin, Yin-Cheng Chang, Chaoping Hsieh, D. Chang
In this paper, a stacked transition of substrate-integrated waveguide (SIW)-to-SIW using flip-chip assembly technology is designed to connect two integrated passive device (IPD) substrates. A through-hole via structure constructed by through silicon vias (TSVs) of the IPD and gold bumps is appropriately designed to greatly improve the impedance bandwidth and reduce insertion loss. The bandwidth of the stacked transition is from 108.5 to 158 GHz (37.2%), and the de-embedded insertion loss is 0.28 dB at 133 GHz.
{"title":"A Broadband Sub-THz Band Stacked Transition of SIW-to-SIW","authors":"Ta-Yeh Lin, Shuw-Guann Lin, Yin-Cheng Chang, Chaoping Hsieh, D. Chang","doi":"10.1109/SPI57109.2023.10145570","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145570","url":null,"abstract":"In this paper, a stacked transition of substrate-integrated waveguide (SIW)-to-SIW using flip-chip assembly technology is designed to connect two integrated passive device (IPD) substrates. A through-hole via structure constructed by through silicon vias (TSVs) of the IPD and gold bumps is appropriately designed to greatly improve the impedance bandwidth and reduce insertion loss. The bandwidth of the stacked transition is from 108.5 to 158 GHz (37.2%), and the de-embedded insertion loss is 0.28 dB at 133 GHz.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125912042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-07DOI: 10.1109/SPI57109.2023.10145538
Francisco Cano, K. Lavery, Snehamay Sinha, T. Bandyopadhyay, Bill G. Mccracken, Shane Stelmach
Power Distribution Network (PDN) noise management is becoming increasingly challenging; increasing clock frequencies create faster current transients for the same application, shrinking die sizes crowd the current into a smaller area of the package increasing current density and effective inductance, and higher utilization of on die circuits results in less static circuit capacitance for decoupling. Thus, accurate prediction of PDN noise continues to be critical to the design process. In this paper, we will touch upon a range of strategies for verifying PDN noise simulation results. Novel aspects include use of on-chip Power Glitch Detector (PGD) to measure peak noise, direct simulation of realistic application code and comparison to on-die measurements, high resolution PDN frequency response characterization through parameterized application code, and findings for board and package model extraction tool selection.
{"title":"Techniques for Correlating Power Distribution Network Simulations with Physical Measurements","authors":"Francisco Cano, K. Lavery, Snehamay Sinha, T. Bandyopadhyay, Bill G. Mccracken, Shane Stelmach","doi":"10.1109/SPI57109.2023.10145538","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145538","url":null,"abstract":"Power Distribution Network (PDN) noise management is becoming increasingly challenging; increasing clock frequencies create faster current transients for the same application, shrinking die sizes crowd the current into a smaller area of the package increasing current density and effective inductance, and higher utilization of on die circuits results in less static circuit capacitance for decoupling. Thus, accurate prediction of PDN noise continues to be critical to the design process. In this paper, we will touch upon a range of strategies for verifying PDN noise simulation results. Novel aspects include use of on-chip Power Glitch Detector (PGD) to measure peak noise, direct simulation of realistic application code and comparison to on-die measurements, high resolution PDN frequency response characterization through parameterized application code, and findings for board and package model extraction tool selection.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133913398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/SPI57109.2023.10145530
J. Mendes, Luís Rodrigues, Sushmitha Kyatam, Luis N. Alves, L. Pereira
High power light emitting diodes (LEDs) are much more efficient than conventional light sources like filament bulbs. Nevertheless, heat is still generated, and this directly affects the reliability of these solid-state light (SSL) devices. In order to decrease the operating temperature, these LEDs can be assembled on metal core printed circuit boards (MCPCBs). However, in applications where stability/lifetime is a critical parameter, such as space applications, diamond plates may be considered. These plates are available from manufacturers with metallized tracks for direct assemblage of surface mount devices (SMD). In order to evaluate the impact of the board on SSL reliability, high power Cree LEDs were assembled on MCPCB and diamond plates. The case temperature was measured for different current ratings and the life-time increase induced by the diamond plate was estimated based on the calculation of the acceleration factor (AF). Diamond plates were shown to have a big impact on the life-time; for nominal current level, and depending on the activetion energy of the aging processes, the LED assembled on the MCPCB will age 2.5-8.8 times faster than the one assembled on the diamond plate. For high current ratings the spectrum radiated by the LED assembled on the diamond plate was also shown to be more stable than the one on the MCPCB.
{"title":"Improving the reliability of power LEDs with diamond boards","authors":"J. Mendes, Luís Rodrigues, Sushmitha Kyatam, Luis N. Alves, L. Pereira","doi":"10.1109/SPI57109.2023.10145530","DOIUrl":"https://doi.org/10.1109/SPI57109.2023.10145530","url":null,"abstract":"High power light emitting diodes (LEDs) are much more efficient than conventional light sources like filament bulbs. Nevertheless, heat is still generated, and this directly affects the reliability of these solid-state light (SSL) devices. In order to decrease the operating temperature, these LEDs can be assembled on metal core printed circuit boards (MCPCBs). However, in applications where stability/lifetime is a critical parameter, such as space applications, diamond plates may be considered. These plates are available from manufacturers with metallized tracks for direct assemblage of surface mount devices (SMD). In order to evaluate the impact of the board on SSL reliability, high power Cree LEDs were assembled on MCPCB and diamond plates. The case temperature was measured for different current ratings and the life-time increase induced by the diamond plate was estimated based on the calculation of the acceleration factor (AF). Diamond plates were shown to have a big impact on the life-time; for nominal current level, and depending on the activetion energy of the aging processes, the LED assembled on the MCPCB will age 2.5-8.8 times faster than the one assembled on the diamond plate. For high current ratings the spectrum radiated by the LED assembled on the diamond plate was also shown to be more stable than the one on the MCPCB.","PeriodicalId":281134,"journal":{"name":"2023 IEEE 27th Workshop on Signal and Power Integrity (SPI)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127999757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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