Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313330
W. Reohr, Y. Chan, D. Plass, A. Pelella, P. -. Wu
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<>
{"title":"Design SRAMs for burn-in","authors":"W. Reohr, Y. Chan, D. Plass, A. Pelella, P. -. Wu","doi":"10.1109/VTEST.1993.313330","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313330","url":null,"abstract":"SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131920946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313318
M. Arai, T. Nakagawa, H. Kitagawa
Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic gate to be mapped into real circuits directly, although the method needs a large number of neurons. In order to reduce the total number of neurons and computing cost, they propose a neural function called NIF, neural inverse function, for ATPG, automatic test pattern generation. A NIF is defined as a Boolean product form of sums. Simulation results of n-bit full-adder circuits show that the computational order of ATPG is approximately O(n/sup 0.5/) in parallel convergence, and O(n/sup 0.9/) in sequential. Compared with the former method, the new method is able to find a set of test patterns about n times faster than the former method, because NIF method needs a small amount of neurons.<>
{"title":"A neural inverse function for automatic test pattern generation using strictly digital neural networks","authors":"M. Arai, T. Nakagawa, H. Kitagawa","doi":"10.1109/VTEST.1993.313318","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313318","url":null,"abstract":"Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic gate to be mapped into real circuits directly, although the method needs a large number of neurons. In order to reduce the total number of neurons and computing cost, they propose a neural function called NIF, neural inverse function, for ATPG, automatic test pattern generation. A NIF is defined as a Boolean product form of sums. Simulation results of n-bit full-adder circuits show that the computational order of ATPG is approximately O(n/sup 0.5/) in parallel convergence, and O(n/sup 0.9/) in sequential. Compared with the former method, the new method is able to find a set of test patterns about n times faster than the former method, because NIF method needs a small amount of neurons.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"59 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313306
M. Nicolaidis
The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.<>
{"title":"Finitely self-checking circuits and their application on current sensors","authors":"M. Nicolaidis","doi":"10.1109/VTEST.1993.313306","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313306","url":null,"abstract":"The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123745866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313325
R. Marculescu
The testing problem of combinational circuits with pseudorandom patterns is investigated. Work by previous workers for single faults is extended to multiple faults situations; in addition, masking effects between disjoint/conjoint faults are considered. An analytical model based on Markov chains with any number of states is proposed for random/pseudorandom testing and relationships between test length and test confidence are developed. Evaluations of the model for double and triple faults are presented using well-known examples. The results presented in this paper are useful for BIST systems that use random/pseudorandom input patterns.<>
{"title":"Worst-case analysis for pseudorandom testing","authors":"R. Marculescu","doi":"10.1109/VTEST.1993.313325","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313325","url":null,"abstract":"The testing problem of combinational circuits with pseudorandom patterns is investigated. Work by previous workers for single faults is extended to multiple faults situations; in addition, masking effects between disjoint/conjoint faults are considered. An analytical model based on Markov chains with any number of states is proposed for random/pseudorandom testing and relationships between test length and test confidence are developed. Evaluations of the model for double and triple faults are presented using well-known examples. The results presented in this paper are useful for BIST systems that use random/pseudorandom input patterns.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313378
Erik H. Ingermann, J. Frenzel
Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>
{"title":"Sensitivity analysis of a radiation immune CMOS logic family under defect conditions","authors":"Erik H. Ingermann, J. Frenzel","doi":"10.1109/VTEST.1993.313378","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313378","url":null,"abstract":"Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128859389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313322
C. Dufaza, C. Chevalier, L. Voon
The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.<>
{"title":"LFSROM an algorithm for automatic design synthesis of hardware test pattern generator","authors":"C. Dufaza, C. Chevalier, L. Voon","doi":"10.1109/VTEST.1993.313322","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313322","url":null,"abstract":"The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313297
C. Di, J. Jess
CMOS bridge faults have very complex behavior and make the testing difficult. This paper proposes a new technique to model all types of bridges as faulty boolean expressions. The modeling is based on analyzing the affected subcircuits using a simplified transistor model. Experiments show that this way of modeling is a good tradeoff of accuracy versus efficiency and allows fast evaluation of test patterns for large circuits.<>
{"title":"On CMOS bridge fault modeling and test pattern evaluation","authors":"C. Di, J. Jess","doi":"10.1109/VTEST.1993.313297","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313297","url":null,"abstract":"CMOS bridge faults have very complex behavior and make the testing difficult. This paper proposes a new technique to model all types of bridges as faulty boolean expressions. The modeling is based on analyzing the affected subcircuits using a simplified transistor model. Experiments show that this way of modeling is a good tradeoff of accuracy versus efficiency and allows fast evaluation of test patterns for large circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115747560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313313
E. Isern, J. Figueras
An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.<>
{"title":"Analysis of redundant structures in combinational circuits","authors":"E. Isern, J. Figueras","doi":"10.1109/VTEST.1993.313313","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313313","url":null,"abstract":"An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129997655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313310
L. Whetsel
The concepts of a proposed IEEE 1149.1 based analog test device have been developed. This device can operate on the 1149.1 serial test bus to monitor and store analog signal data in much the same way as traditional analog test instruments. The primary advantage of this device is that it can be included on miniaturized printed circuit boards and within multi-chip modules to provide an embedded method of accessing and testing analog circuitry. This paper describes the proposed device and illustrates how it can be used in a system to monitor both static and dynamic analog signal types.<>
{"title":"An IEEE 1149.1 based voltmeter/oscilloscope in a chip","authors":"L. Whetsel","doi":"10.1109/VTEST.1993.313310","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313310","url":null,"abstract":"The concepts of a proposed IEEE 1149.1 based analog test device have been developed. This device can operate on the 1149.1 serial test bus to monitor and store analog signal data in much the same way as traditional analog test instruments. The primary advantage of this device is that it can be included on miniaturized printed circuit boards and within multi-chip modules to provide an embedded method of accessing and testing analog circuitry. This paper describes the proposed device and illustrates how it can be used in a system to monitor both static and dynamic analog signal types.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313362
S. Menon, A. Jayasumana, Y. Malaiya
BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<>
{"title":"Testable design for BiCMOS stuck-open fault detection","authors":"S. Menon, A. Jayasumana, Y. Malaiya","doi":"10.1109/VTEST.1993.313362","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313362","url":null,"abstract":"BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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