Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313330
W. Reohr, Y. Chan, D. Plass, A. Pelella, P. -. Wu
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<>
{"title":"Design SRAMs for burn-in","authors":"W. Reohr, Y. Chan, D. Plass, A. Pelella, P. -. Wu","doi":"10.1109/VTEST.1993.313330","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313330","url":null,"abstract":"SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131920946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313306
M. Nicolaidis
The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.<>
{"title":"Finitely self-checking circuits and their application on current sensors","authors":"M. Nicolaidis","doi":"10.1109/VTEST.1993.313306","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313306","url":null,"abstract":"The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123745866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313325
R. Marculescu
The testing problem of combinational circuits with pseudorandom patterns is investigated. Work by previous workers for single faults is extended to multiple faults situations; in addition, masking effects between disjoint/conjoint faults are considered. An analytical model based on Markov chains with any number of states is proposed for random/pseudorandom testing and relationships between test length and test confidence are developed. Evaluations of the model for double and triple faults are presented using well-known examples. The results presented in this paper are useful for BIST systems that use random/pseudorandom input patterns.<>
{"title":"Worst-case analysis for pseudorandom testing","authors":"R. Marculescu","doi":"10.1109/VTEST.1993.313325","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313325","url":null,"abstract":"The testing problem of combinational circuits with pseudorandom patterns is investigated. Work by previous workers for single faults is extended to multiple faults situations; in addition, masking effects between disjoint/conjoint faults are considered. An analytical model based on Markov chains with any number of states is proposed for random/pseudorandom testing and relationships between test length and test confidence are developed. Evaluations of the model for double and triple faults are presented using well-known examples. The results presented in this paper are useful for BIST systems that use random/pseudorandom input patterns.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313318
M. Arai, T. Nakagawa, H. Kitagawa
Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic gate to be mapped into real circuits directly, although the method needs a large number of neurons. In order to reduce the total number of neurons and computing cost, they propose a neural function called NIF, neural inverse function, for ATPG, automatic test pattern generation. A NIF is defined as a Boolean product form of sums. Simulation results of n-bit full-adder circuits show that the computational order of ATPG is approximately O(n/sup 0.5/) in parallel convergence, and O(n/sup 0.9/) in sequential. Compared with the former method, the new method is able to find a set of test patterns about n times faster than the former method, because NIF method needs a small amount of neurons.<>
{"title":"A neural inverse function for automatic test pattern generation using strictly digital neural networks","authors":"M. Arai, T. Nakagawa, H. Kitagawa","doi":"10.1109/VTEST.1993.313318","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313318","url":null,"abstract":"Presents a new method using 'k-out-of-n' design rule for neural networks to find out sets of diagnostic patterns to test VLSI circuits. The authors have already introduced a former method using neural logic gate to be mapped into real circuits directly, although the method needs a large number of neurons. In order to reduce the total number of neurons and computing cost, they propose a neural function called NIF, neural inverse function, for ATPG, automatic test pattern generation. A NIF is defined as a Boolean product form of sums. Simulation results of n-bit full-adder circuits show that the computational order of ATPG is approximately O(n/sup 0.5/) in parallel convergence, and O(n/sup 0.9/) in sequential. Compared with the former method, the new method is able to find a set of test patterns about n times faster than the former method, because NIF method needs a small amount of neurons.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"59 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313378
Erik H. Ingermann, J. Frenzel
Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>
{"title":"Sensitivity analysis of a radiation immune CMOS logic family under defect conditions","authors":"Erik H. Ingermann, J. Frenzel","doi":"10.1109/VTEST.1993.313378","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313378","url":null,"abstract":"Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128859389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313322
C. Dufaza, C. Chevalier, L. Voon
The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.<>
{"title":"LFSROM an algorithm for automatic design synthesis of hardware test pattern generator","authors":"C. Dufaza, C. Chevalier, L. Voon","doi":"10.1109/VTEST.1993.313322","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313322","url":null,"abstract":"The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313357
G. Edirisooriya, S. Edirisooriya, John P. Robinson
A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test length for a large class of signature registers. The authors identify the minimum register structure that falls into this class.<>
{"title":"Time and space correlated errors in signature analysis","authors":"G. Edirisooriya, S. Edirisooriya, John P. Robinson","doi":"10.1109/VTEST.1993.313357","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313357","url":null,"abstract":"A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test length for a large class of signature registers. The authors identify the minimum register structure that falls into this class.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313324
Ravishankar Kodavarti, D. Ross
Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.<>
{"title":"Signal probability calculations using partial functional manipulation","authors":"Ravishankar Kodavarti, D. Ross","doi":"10.1109/VTEST.1993.313324","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313324","url":null,"abstract":"Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"117 37","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120820601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313309
F. Busaba, P. Lala
Presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce single bit error or unidirectional multibit errors at the output are proposed. If there are no input faults which produce bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.<>
{"title":"Input and output encoding techniques for on-line error detection in combinational logic circuits","authors":"F. Busaba, P. Lala","doi":"10.1109/VTEST.1993.313309","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313309","url":null,"abstract":"Presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce single bit error or unidirectional multibit errors at the output are proposed. If there are no input faults which produce bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122725527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313354
S. Srinivasan, G. Swaminathan, J. Aylor, M. R. Mercer
The increasing size and complexity of current VLSI circuits has brought testing and design for testability into the mainstream of the design process. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. The problem has been shown to be NP-complete and most of the current research attempts to find efficient ways to generate tests for hard faults in a reasonable amount of time on the average. Hence, there remains a lot of interest in the testing world for efficient techniques to do combinational ATPG. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs.<>
{"title":"Combinational circuit ATPG using binary decision diagrams","authors":"S. Srinivasan, G. Swaminathan, J. Aylor, M. R. Mercer","doi":"10.1109/VTEST.1993.313354","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313354","url":null,"abstract":"The increasing size and complexity of current VLSI circuits has brought testing and design for testability into the mainstream of the design process. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. The problem has been shown to be NP-complete and most of the current research attempts to find efficient ways to generate tests for hard faults in a reasonable amount of time on the average. Hence, there remains a lot of interest in the testing world for efficient techniques to do combinational ATPG. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：