Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313311
F. Vargas, M. Nicolaidis, B. Hamdi
Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, for instance, minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution. This approach is exemplified with the characterization of an in-house developed cell library.<>
{"title":"Quiescent current estimation based on quality requirements","authors":"F. Vargas, M. Nicolaidis, B. Hamdi","doi":"10.1109/VTEST.1993.313311","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313311","url":null,"abstract":"Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, for instance, minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution. This approach is exemplified with the characterization of an in-house developed cell library.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313365
V. Agrawal, T. Chakraborty
Gives methods of test generation for partial scan circuits in which a single system clock controls all flip-flops in both functional and scan modes. Scan flip-flops are selected to break cycles. In comparison to circuits with separate scan clock, the single clock tests can cover most detectable faults with shorter test sequence. However, test generation time is increased.<>
{"title":"Partial scan testing with single clock control","authors":"V. Agrawal, T. Chakraborty","doi":"10.1109/VTEST.1993.313365","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313365","url":null,"abstract":"Gives methods of test generation for partial scan circuits in which a single system clock controls all flip-flops in both functional and scan modes. Scan flip-flops are selected to break cycles. In comparison to circuits with separate scan clock, the single clock tests can cover most detectable faults with shorter test sequence. However, test generation time is increased.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115514684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313337
K. K. Varma, P. Vishakantaiah, J. Abraham
Develops a synthesis-for-testability procedure wherein behavioral modeling techniques are used to generate testable designs. Knowledge about the accessibility of embedded modules is extracted from the behavioral design, analyzed, and any modification required subsequently incorporated in the behavioral design. Results show that when the resulting testable circuit is synthesized from this modified design using a high level synthesis tool, the overhead for testability is quite small, especially for large circuits.<>
{"title":"Generation of testable designs from behavioral descriptions using high level synthesis tools","authors":"K. K. Varma, P. Vishakantaiah, J. Abraham","doi":"10.1109/VTEST.1993.313337","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313337","url":null,"abstract":"Develops a synthesis-for-testability procedure wherein behavioral modeling techniques are used to generate testable designs. Knowledge about the accessibility of embedded modules is extracted from the behavioral design, analyzed, and any modification required subsequently incorporated in the behavioral design. Results show that when the resulting testable circuit is synthesized from this modified design using a high level synthesis tool, the overhead for testability is quite small, especially for large circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114502065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313375
C. A. Ryan, J. Tront
Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<>
{"title":"On parallel switch level fault simulation","authors":"C. A. Ryan, J. Tront","doi":"10.1109/VTEST.1993.313375","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313375","url":null,"abstract":"Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122007640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313336
S. Kundu, A. Pramanick
Synthesis proceeds through local transformations with various objectives. If testability is a concern, these transformations are limited to those that preserve or enhance testability. Such transformations are called testability preserving transformations. The fault model used is pivotal to the analysis of any such transformation. In this paper, the authors chose single-path-propagating hazard-free robust delay fault testability to qualify them. This model was chosen because it disambiguates results of delay testing which are often inconclusive (the presence of a fault can neither be ascertained nor be denied) and ensures stuck-at fault testability as well. Unfortunately, only a few transformations are known to obey testability requirements. This limitation is a serious handicap in attaining other synthesis goals such as area and performance optimization. In this paper the authors establish a relationship between testability properties of logic transformations and their Boolean duals, the application of which enlarges the existing number of testability preserving transforms. They demonstrate further that some of the new transformations thus achieved may actually enhance testability.<>
{"title":"Testability preserving Boolean transforms for logic synthesis","authors":"S. Kundu, A. Pramanick","doi":"10.1109/VTEST.1993.313336","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313336","url":null,"abstract":"Synthesis proceeds through local transformations with various objectives. If testability is a concern, these transformations are limited to those that preserve or enhance testability. Such transformations are called testability preserving transformations. The fault model used is pivotal to the analysis of any such transformation. In this paper, the authors chose single-path-propagating hazard-free robust delay fault testability to qualify them. This model was chosen because it disambiguates results of delay testing which are often inconclusive (the presence of a fault can neither be ascertained nor be denied) and ensures stuck-at fault testability as well. Unfortunately, only a few transformations are known to obey testability requirements. This limitation is a serious handicap in attaining other synthesis goals such as area and performance optimization. In this paper the authors establish a relationship between testability properties of logic transformations and their Boolean duals, the application of which enlarges the existing number of testability preserving transforms. They demonstrate further that some of the new transformations thus achieved may actually enhance testability.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131605763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313315
G. Edirisooriya, S. Edirisooriya, John P. Robinson
Built-in-self-test (BIST) schemes provide on-chip circuitry to generate test vectors and to analyze output responses so that testing can be performed without using expensive external testers. The authors present a unified approach to test pattern generation and output compaction. ISCAS benchmark circuits are used to show the applicability of the proposed method.<>
{"title":"A new built-in self-test method based on prestored testing","authors":"G. Edirisooriya, S. Edirisooriya, John P. Robinson","doi":"10.1109/VTEST.1993.313315","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313315","url":null,"abstract":"Built-in-self-test (BIST) schemes provide on-chip circuitry to generate test vectors and to analyze output responses so that testing can be performed without using expensive external testers. The authors present a unified approach to test pattern generation and output compaction. ISCAS benchmark circuits are used to show the applicability of the proposed method.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128109399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313319
W. Kao, J. Xia
Test development is without doubt the major bottleneck in the product delivery cycle of mixed signal ICs. One of the most time consuming tasks during the test development phase is the design of the DUT board where the IC is to be inserted to run on a mixed signal tester. This paper describes a new methodology of capturing test information for an IC through test module schematics and then using an automatic tool to synthesize the final load board circuitry to be used on mixed signal ATEs.<>
{"title":"Automatic synthesis of DUT board circuits for testing of mixed signal ICs","authors":"W. Kao, J. Xia","doi":"10.1109/VTEST.1993.313319","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313319","url":null,"abstract":"Test development is without doubt the major bottleneck in the product delivery cycle of mixed signal ICs. One of the most time consuming tasks during the test development phase is the design of the DUT board where the IC is to be inserted to run on a mixed signal tester. This paper describes a new methodology of capturing test information for an IC through test module schematics and then using an automatic tool to synthesize the final load board circuitry to be used on mixed signal ATEs.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-04-06DOI: 10.1109/VTEST.1993.313304
Kyuchull Kim, K. Saluja
A simple method which combines the efficiencies of an event driven implication method and speed of a compiled code implication is proposed for use in a sequential test pattern generator. This method, in conjunction with several other concepts and heuristics, is used to implement a sequential test pattern generator CCSTG based on the sequential test generation algorithm used in FASTEST. It is shown that the performance of a sequential test pattern generator improves substantially when methods proposed in this paper are incorporated in a test pattern generator. The authors verified this assertion by comparing the performances of test pattern generators, with and without these features, for ISCAS-89 benchmark sequential circuits.<>
{"title":"CCSTG: an efficient test pattern generator for sequential circuits","authors":"Kyuchull Kim, K. Saluja","doi":"10.1109/VTEST.1993.313304","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313304","url":null,"abstract":"A simple method which combines the efficiencies of an event driven implication method and speed of a compiled code implication is proposed for use in a sequential test pattern generator. This method, in conjunction with several other concepts and heuristics, is used to implement a sequential test pattern generator CCSTG based on the sequential test generation algorithm used in FASTEST. It is shown that the performance of a sequential test pattern generator improves substantially when methods proposed in this paper are incorporated in a test pattern generator. The authors verified this assertion by comparing the performances of test pattern generators, with and without these features, for ISCAS-89 benchmark sequential circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"266 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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