Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947119
Daehwan Lho, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Boogyo Sim, Kyungjune Son, Keeyoung Son, Jihun Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Kyubong Kong, Joungho Kim
In this paper, we propose the deterministic policy gradient-based reinforcement learning for DDR5 memory signaling architecture optimization considering signal integrity. We convert the complex DDR5 memory signaling architecture optimization to the Markov decision process (MDP). The key limitation factor was found through the analysis of the hierarchical channel, and MDP was configured to solve it. The deterministic policy is essential for optimizing high-dimensional problems that have many continuous design parameters. For verification, we compare the proposed method with conventional methods such as random search (RS) and Bayesian optimization (BO) and other reinforcement learning algorithms such as the advantage actor-critic (A2C) and proximal policy optimization (PPO). RS and BO could not be properly optimized even after 10000 iterations of 1000 times, respectively, and A2C and PPO failed to optimize. As a result of comparison, the proposed method has the highest optimality, low computing time, and reusability.
{"title":"Deterministic Policy Gradient-based Reinforcement Learning for DDR5 Memory Signaling Architecture Optimization considering Signal Integrity","authors":"Daehwan Lho, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Boogyo Sim, Kyungjune Son, Keeyoung Son, Jihun Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947119","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947119","url":null,"abstract":"In this paper, we propose the deterministic policy gradient-based reinforcement learning for DDR5 memory signaling architecture optimization considering signal integrity. We convert the complex DDR5 memory signaling architecture optimization to the Markov decision process (MDP). The key limitation factor was found through the analysis of the hierarchical channel, and MDP was configured to solve it. The deterministic policy is essential for optimizing high-dimensional problems that have many continuous design parameters. For verification, we compare the proposed method with conventional methods such as random search (RS) and Bayesian optimization (BO) and other reinforcement learning algorithms such as the advantage actor-critic (A2C) and proximal policy optimization (PPO). RS and BO could not be properly optimized even after 10000 iterations of 1000 times, respectively, and A2C and PPO failed to optimize. As a result of comparison, the proposed method has the highest optimality, low computing time, and reusability.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121685294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to aggressive storage capacity demands, multiple NAND Flash die are often stacked in a highly integrated, complex package system. As data-rate increases, bit time (UI) is shrinking, and accurate measurement of the data valid window and jitter become very important. Power distribution network (PDN) noise affects the overall system timing. The conventional way of PDN modeling approach in NAND Flash memory System level analysis, cannot accurately predict the system level jitter and deviates from the actual product level performance. In this paper, an accurate method for PDN-induced jitter analysis in NAND Flash system-level operation is described. Simulated PDN-induced jitter results are validated through characterization system and product level measurement jitter.
由于对存储容量的巨大需求，多个NAND闪存芯片通常堆叠在一个高度集成的复杂封装系统中。随着数据速率的提高，比特时间(UI)不断缩短，准确测量数据有效窗口和抖动变得非常重要。PDN (Power distribution network)噪声会影响整个系统的时序。传统的PDN建模方法在NAND闪存系统级分析中，不能准确预测系统级抖动，偏离实际产品级性能。本文描述了一种精确分析NAND闪存系统级工作中pdn引起的抖动的方法。通过表征系统和产品级测量抖动验证了模拟pdn引起的抖动结果。
{"title":"Distributed PDN Modeling Approach for Accurate Jitter Estimation in High-Speed NAND Flash Memory","authors":"Sayed Mobin, Pranav Balachander, Asha Sharma, Venkatesh Ramachandra","doi":"10.1109/EPEPS53828.2022.9947093","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947093","url":null,"abstract":"Due to aggressive storage capacity demands, multiple NAND Flash die are often stacked in a highly integrated, complex package system. As data-rate increases, bit time (UI) is shrinking, and accurate measurement of the data valid window and jitter become very important. Power distribution network (PDN) noise affects the overall system timing. The conventional way of PDN modeling approach in NAND Flash memory System level analysis, cannot accurately predict the system level jitter and deviates from the actual product level performance. In this paper, an accurate method for PDN-induced jitter analysis in NAND Flash system-level operation is described. Simulated PDN-induced jitter results are validated through characterization system and product level measurement jitter.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126607339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947122
Wonsuk Choi, S. Kwak, Jaeseok Park, Jiyoung Do, Byeongseon Yun, Yoo-Jeong Kwon, Dongho Kim, Kyu-Sik Lee, Tae Young Kim, Wonyoung Kim, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song
As the operation of server system is accelerated, the importance of signal integrity (SI) and power integrity (PI) measurement methodology and modeling of dual in line memory module (DIMM) products is increasing. In this paper, we introduce the advanced methodology for on-chip SI/PI measurement and DRAM signal recovery with the DDR5 probing package development. Comparing with the conventional interposer, a new method of probing package has proved to be advantageous for high-speed signal measurement and signal recovery, and it can also be used as a useful tool for DRAM on-chip SI measurement and signal prediction in post DDR5 speed (beyond 6.4 Gbps).
随着服务器系统运行速度的加快，信号完整性(SI)和功率完整性(PI)的测量方法和dual - in - line memory module (DIMM)产品的建模变得越来越重要。本文介绍了基于DDR5探测封装开发的片上SI/PI测量和DRAM信号恢复的先进方法。与传统的中介器相比，一种新的探测封装方法被证明具有高速信号测量和信号恢复的优势，它也可以作为DRAM片上SI测量和信号预测的有用工具，在DDR5之后的速度(超过6.4 Gbps)。
{"title":"Advanced Measurement and Simulation Approach for DDR5 On-chip SI/PI with the Probing Package","authors":"Wonsuk Choi, S. Kwak, Jaeseok Park, Jiyoung Do, Byeongseon Yun, Yoo-Jeong Kwon, Dongho Kim, Kyu-Sik Lee, Tae Young Kim, Wonyoung Kim, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song","doi":"10.1109/EPEPS53828.2022.9947122","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947122","url":null,"abstract":"As the operation of server system is accelerated, the importance of signal integrity (SI) and power integrity (PI) measurement methodology and modeling of dual in line memory module (DIMM) products is increasing. In this paper, we introduce the advanced methodology for on-chip SI/PI measurement and DRAM signal recovery with the DDR5 probing package development. Comparing with the conventional interposer, a new method of probing package has proved to be advantageous for high-speed signal measurement and signal recovery, and it can also be used as a useful tool for DRAM on-chip SI measurement and signal prediction in post DDR5 speed (beyond 6.4 Gbps).","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947201
Allan Sánchez-Masís, Sameer Shekhar
PDN optimization involves selection of capacitors to meet the target impedance. This paper uses reinforcement learning to solve decoupling stuffing problem based on impedance-based reward and then with both impedance & cost-based reward. It is shown how the agent can be biased when trained only on impedance-based reward. Key results including attainment of target impedance and overall achieving cost and impedance optimized solution are reported.
{"title":"Impedance and Cost based PDN Decoupling Optimization using Reinforcement Learning","authors":"Allan Sánchez-Masís, Sameer Shekhar","doi":"10.1109/EPEPS53828.2022.9947201","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947201","url":null,"abstract":"PDN optimization involves selection of capacitors to meet the target impedance. This paper uses reinforcement learning to solve decoupling stuffing problem based on impedance-based reward and then with both impedance & cost-based reward. It is shown how the agent can be biased when trained only on impedance-based reward. Key results including attainment of target impedance and overall achieving cost and impedance optimized solution are reported.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122637114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947128
H. Bakshi, R. Murugan, Sylvester Ankamah-Kusi
Radiation characteristics of on-chip patch antennas are limited by the metallization and dielectric properties of the back-end of line (BEOL) silicon manufacturing processes. A 300-GHz on-chip patch antenna is designed using a radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) process. The radiation efficiency, peak gain, and impedance bandwidth improve upon encapsulation of the antenna with IC packaging epoxy mold compounds (EMCs). In addition, high-frequency conduction and dielectric losses are analyzed, and their effects on antenna radiation efficiency are quantified in this paper. The overall radiation efficiency is shown to improve by 25%, peak gain by $sim 3 boldsymbol{text{dB}}$, and the-10-dB return loss bandwidth improves from 3 GHz to 18 GHz by encapsulating a 300-GHz on-chip patch antenna within commercially available EMCs.
{"title":"Improvement of Radiation Characteristics of a 300-GHz On-Chip Patch Antenna with Epoxy Mold Compound (EMC) Encapsulation","authors":"H. Bakshi, R. Murugan, Sylvester Ankamah-Kusi","doi":"10.1109/EPEPS53828.2022.9947128","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947128","url":null,"abstract":"Radiation characteristics of on-chip patch antennas are limited by the metallization and dielectric properties of the back-end of line (BEOL) silicon manufacturing processes. A 300-GHz on-chip patch antenna is designed using a radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) process. The radiation efficiency, peak gain, and impedance bandwidth improve upon encapsulation of the antenna with IC packaging epoxy mold compounds (EMCs). In addition, high-frequency conduction and dielectric losses are analyzed, and their effects on antenna radiation efficiency are quantified in this paper. The overall radiation efficiency is shown to improve by 25%, peak gain by $sim 3 boldsymbol{text{dB}}$, and the-10-dB return loss bandwidth improves from 3 GHz to 18 GHz by encapsulating a 300-GHz on-chip patch antenna within commercially available EMCs.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114288162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947131
O. Akinwande, O. W. Bhatti, Madhavan Swaminathan
Heterogeneous integration of voltage regulators in power delivery networks is a growing trend that employs em-bedded inductor as a key component in significantly improving the power distribution. In this work, we propose a neural network framework called the hierarchical invertible neural transport for the inverse design of an embedded inductor. With this invertible method, we obtain the probability distributions of the parameters of the embedded inductor design space that most likely satisfy the desired specifications. We also learn the impedance response for free in the forward design. In the forward design, our results show a 2.14% normalized mean square error when compared with the output response of a full wave EM simulator.
{"title":"Inverse Design of Embedded Inductor with Hierarchical Invertible Neural Transport Net","authors":"O. Akinwande, O. W. Bhatti, Madhavan Swaminathan","doi":"10.1109/EPEPS53828.2022.9947131","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947131","url":null,"abstract":"Heterogeneous integration of voltage regulators in power delivery networks is a growing trend that employs em-bedded inductor as a key component in significantly improving the power distribution. In this work, we propose a neural network framework called the hierarchical invertible neural transport for the inverse design of an embedded inductor. With this invertible method, we obtain the probability distributions of the parameters of the embedded inductor design space that most likely satisfy the desired specifications. We also learn the impedance response for free in the forward design. In the forward design, our results show a 2.14% normalized mean square error when compared with the output response of a full wave EM simulator.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121022427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947106
A. Carlucci, S. Grivet-Talocia, Scott Mongrain, Siddharth Kulasekaran, K. Radhakrishnan
This paper proposes a novel framework for power integrity verification of multicore systems, including voltage stabilization provided by multiple integrated voltage regulators at the core interfaces. The proposed framework adopts a two-stage macromodeling strategy to derive a compact representation of the full system dynamics as observed from each core. These dynamics are parameterized by the time-varying duty cycle provided by dedicated feedback controllers to each voltage regulator, here implemented through an averaged model. We show that the proposed simulation framework has the potential to outperform direct transient analysis based on SPICE engines.
{"title":"Towards Accelerated Transient Solvers for Full System Power Integrity Verification","authors":"A. Carlucci, S. Grivet-Talocia, Scott Mongrain, Siddharth Kulasekaran, K. Radhakrishnan","doi":"10.1109/EPEPS53828.2022.9947106","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947106","url":null,"abstract":"This paper proposes a novel framework for power integrity verification of multicore systems, including voltage stabilization provided by multiple integrated voltage regulators at the core interfaces. The proposed framework adopts a two-stage macromodeling strategy to derive a compact representation of the full system dynamics as observed from each core. These dynamics are parameterized by the time-varying duty cycle provided by dedicated feedback controllers to each voltage regulator, here implemented through an averaged model. We show that the proposed simulation framework has the potential to outperform direct transient analysis based on SPICE engines.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947141
A. Page, M. Cocchini, Zhaoqing Chen, Xu Chen
This paper demonstrates a method to extract impedance-attenuation corners of a stripline with user-prescribed confidence levels. This is done using a sparse-grid-based surrogate model to quickly generate vast Monte Carlo datasets from which the impedance-attenuation distribution is calculated. Ellipses are fit to this distribution as equi-density contours to enclose a proportion of the solution data. Appropriate corners can be read off these ellipses and applied to broadband simulation. The results are compared against three measured test coupons, showing capability to analyze a PCIe Gen. 5 link. Realistic modeling of geometries and material variations is emphasized.
本文演示了一种以用户规定的置信水平提取带状线的阻抗衰减角的方法。这是使用基于稀疏网格的代理模型来快速生成大量蒙特卡罗数据集，从中计算阻抗衰减分布。椭圆作为等密度轮廓适合于这种分布，以包围一定比例的解数据。可以从这些椭圆中读出适当的角，并应用于宽带仿真。结果与三个测量的测试券进行比较，显示了分析PCIe Gen. 5链路的能力。强调几何形状和材料变化的现实建模。
{"title":"Realistic Stripline Corner Modeling Using Surrogate Model and Topographic Fitting","authors":"A. Page, M. Cocchini, Zhaoqing Chen, Xu Chen","doi":"10.1109/EPEPS53828.2022.9947141","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947141","url":null,"abstract":"This paper demonstrates a method to extract impedance-attenuation corners of a stripline with user-prescribed confidence levels. This is done using a sparse-grid-based surrogate model to quickly generate vast Monte Carlo datasets from which the impedance-attenuation distribution is calculated. Ellipses are fit to this distribution as equi-density contours to enclose a proportion of the solution data. Appropriate corners can be read off these ellipses and applied to broadband simulation. The results are compared against three measured test coupons, showing capability to analyze a PCIe Gen. 5 link. Realistic modeling of geometries and material variations is emphasized.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130018513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947191
Katharina Scharff, Xiaomin Duan, M. Cocchini, Hung Nguyen, Nicole Selezinski, D. Kaller, H. Harrer
Coupling in dense via pinfields is known as a major contributor to crosstalk. In this work we present and verify a novel wiring strategy for links with a symmetrical pinfield-to-pinfield topology that reduces crosstalk significantly and requires no extra shielding vias. By twisting the orientation of the $p$ and $n$ wires of the differential stripline pair, a cancellation of the crosstalk between the differential via pairs is achieved. It can be implemented without any additional space requirements. The proposed design is fabricated and the crosstalk is measured with a vector network analyzer. It is shown that small changes in the orientation of the wiring in the pinfield region can reduce far-end crosstalk significantly.
{"title":"Hardware Verification of Via Crosstalk Cancellation for Differential BGA-to-BGA Links","authors":"Katharina Scharff, Xiaomin Duan, M. Cocchini, Hung Nguyen, Nicole Selezinski, D. Kaller, H. Harrer","doi":"10.1109/EPEPS53828.2022.9947191","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947191","url":null,"abstract":"Coupling in dense via pinfields is known as a major contributor to crosstalk. In this work we present and verify a novel wiring strategy for links with a symmetrical pinfield-to-pinfield topology that reduces crosstalk significantly and requires no extra shielding vias. By twisting the orientation of the $p$ and $n$ wires of the differential stripline pair, a cancellation of the crosstalk between the differential via pairs is achieved. It can be implemented without any additional space requirements. The proposed design is fabricated and the crosstalk is measured with a vector network analyzer. It is shown that small changes in the orientation of the wiring in the pinfield region can reduce far-end crosstalk significantly.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125254701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947151
T. Bradde, S. Grivet-Talocia
An approach for generating time-varying linearized macromodels of analog circuit blocks is presented. These models can be used to perform fast small-signal analyses characterized by nonstationary operating conditions, thanks to their certified stability. We validate the proposed approach by performing post-layout simulations of a Low DropOut (LDO) voltage regulator, in view of power integrity assessment applications.
{"title":"Fast LDO Simulations via Parameter-Varying Linearized Macromodels","authors":"T. Bradde, S. Grivet-Talocia","doi":"10.1109/EPEPS53828.2022.9947151","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947151","url":null,"abstract":"An approach for generating time-varying linearized macromodels of analog circuit blocks is presented. These models can be used to perform fast small-signal analyses characterized by nonstationary operating conditions, thanks to their certified stability. We validate the proposed approach by performing post-layout simulations of a Low DropOut (LDO) voltage regulator, in view of power integrity assessment applications.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122320172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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