Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947166
Hyunwook Park, Taein Shin, Seongguk Kim, Daehwan Lho, Boogyo Sim, Jinwook Song, Kyubong Kong, Joungho Kim
In this paper, we first propose a scalable transformer network-based reinforcement learning (RL) method for power supply induced jitter (PSIJ) optimization in high bandwidth memory (HBM). The proposed method can provide an optimal power distribution network (PDN) decoupling capacitor (decap) design to satisfy the target PSIJ with the minimum number of NMOS decaps. For the given number of decaps, the network is trained to maximize the impedance reduction from 10 MHz to 20 GHz compared to the initial PDN. Also, the network has scalability on the number of decap assignments. Therefore, for given any number of decaps, the scalable network can provide minimized PDN impedance profiles by one inference without re-training. Then, by increasing the decap assignments, the network can find out the minimum number to meet the given target PSIJ. For verification, the proposed network is applied to the HBM2 I/O interface. The network successfully provides the optimized decap designs to satisfy the given target PSIJ values.
{"title":"Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM","authors":"Hyunwook Park, Taein Shin, Seongguk Kim, Daehwan Lho, Boogyo Sim, Jinwook Song, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947166","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947166","url":null,"abstract":"In this paper, we first propose a scalable transformer network-based reinforcement learning (RL) method for power supply induced jitter (PSIJ) optimization in high bandwidth memory (HBM). The proposed method can provide an optimal power distribution network (PDN) decoupling capacitor (decap) design to satisfy the target PSIJ with the minimum number of NMOS decaps. For the given number of decaps, the network is trained to maximize the impedance reduction from 10 MHz to 20 GHz compared to the initial PDN. Also, the network has scalability on the number of decap assignments. Therefore, for given any number of decaps, the scalable network can provide minimized PDN impedance profiles by one inference without re-training. Then, by increasing the decap assignments, the network can find out the minimum number to meet the given target PSIJ. For verification, the proposed network is applied to the HBM2 I/O interface. The network successfully provides the optimized decap designs to satisfy the given target PSIJ values.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947123
Keunwoo Kim, Jung-Hyun Lee, Seokwoo Hong, Hyunwoo Kim, Boogyo Sim, Kyungjune Son, Taein Shin, Keeyoung Son, Jinyoung Kim, Kyubong Kong, Joungho Kim
In this paper, we propose a new board-to-board connector design for 5G mmWave and high-speed signaling. The proposed board-to-board connector has a socket shield and mid-plate between pins. The socket shell reduces electromagnetic interference (EMI), emitted to the outside and the mid-plate reduces crosstalk between terminals. We verified the signal integrity performance and EMI reduction effect of the newly added ground structures through EM simulation. However, due to the increased ground structure, the return current path of the signal is split, and resonances are generated. We analyzed the resonances through the J-field change according to the frequencies.
{"title":"A Low EMI Board-to-board Connector Design for 5G mmWave and High-speed Signaling","authors":"Keunwoo Kim, Jung-Hyun Lee, Seokwoo Hong, Hyunwoo Kim, Boogyo Sim, Kyungjune Son, Taein Shin, Keeyoung Son, Jinyoung Kim, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947123","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947123","url":null,"abstract":"In this paper, we propose a new board-to-board connector design for 5G mmWave and high-speed signaling. The proposed board-to-board connector has a socket shield and mid-plate between pins. The socket shell reduces electromagnetic interference (EMI), emitted to the outside and the mid-plate reduces crosstalk between terminals. We verified the signal integrity performance and EMI reduction effect of the newly added ground structures through EM simulation. However, due to the increased ground structure, the return current path of the signal is split, and resonances are generated. We analyzed the resonances through the J-field change according to the frequencies.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116123225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947193
C. Cho, Kwangho Kim, Manho Lee, Jaeyoung Shin, Sungjin Yoon, Youngjae Lee, Chayoung Song, Wooshin Choi, M. Kwak, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko
In high-speed SerDes channels, it becomes more important to reduce impedance mismatches to minimize signal return. Most of the mismatches are due to the differential via on PCB which is essential component to make up the PCIe Gen 5 system, and this mismatch should be reduced for the high-speed signal quality. To effectively minimize the mismatch, this paper presents an equation based TDR estimation model of the differential via, and the model is verified to commercial model of the coupled transmission line. And this paper also proposes a method for optimizing the design parameters of the differential via by applying a reward based on TDR impedance to PSO algorithm. The optimization procedure is then applied to one of the actual PCB designs to verify the optimized design parameters.
{"title":"Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm","authors":"C. Cho, Kwangho Kim, Manho Lee, Jaeyoung Shin, Sungjin Yoon, Youngjae Lee, Chayoung Song, Wooshin Choi, M. Kwak, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko","doi":"10.1109/EPEPS53828.2022.9947193","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947193","url":null,"abstract":"In high-speed SerDes channels, it becomes more important to reduce impedance mismatches to minimize signal return. Most of the mismatches are due to the differential via on PCB which is essential component to make up the PCIe Gen 5 system, and this mismatch should be reduced for the high-speed signal quality. To effectively minimize the mismatch, this paper presents an equation based TDR estimation model of the differential via, and the model is verified to commercial model of the coupled transmission line. And this paper also proposes a method for optimizing the design parameters of the differential via by applying a reward based on TDR impedance to PSO algorithm. The optimization procedure is then applied to one of the actual PCB designs to verify the optimized design parameters.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947115
Qinghao Zhang, Ruoyi Xie, F. Guo, Shashwat Sharma, Damian Marek, P. Triverio
We present a complete methodology to import and mesh the layout of complex interconnect networks for electromag-netic analysis. At first glance, these tasks may seem straightfor-ward. In reality, they require complex geometrical operations, which are not trivial to perform efficiently and robustly for realistic layouts. The methodology is based on publicly-available libraries and generates a conformal surface mesh suitable for the boundary element method. The method is tested on an entire IC package from the Packaging Benchmark Suite.
{"title":"An Efficient Methodology to Parse and Mesh Large Interconnect Layouts for Electromagnetic Analysis","authors":"Qinghao Zhang, Ruoyi Xie, F. Guo, Shashwat Sharma, Damian Marek, P. Triverio","doi":"10.1109/EPEPS53828.2022.9947115","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947115","url":null,"abstract":"We present a complete methodology to import and mesh the layout of complex interconnect networks for electromag-netic analysis. At first glance, these tasks may seem straightfor-ward. In reality, they require complex geometrical operations, which are not trivial to perform efficiently and robustly for realistic layouts. The methodology is based on publicly-available libraries and generates a conformal surface mesh suitable for the boundary element method. The method is tested on an entire IC package from the Packaging Benchmark Suite.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"226 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132074904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947108
Dries Bosman, Martijn Huynen, D. De Zutter, Xiao Sun, N. Pantano, G. van der Plas, E. Beyne, D. Ginste
In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.
{"title":"Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method","authors":"Dries Bosman, Martijn Huynen, D. De Zutter, Xiao Sun, N. Pantano, G. van der Plas, E. Beyne, D. Ginste","doi":"10.1109/EPEPS53828.2022.9947108","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947108","url":null,"abstract":"In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947140
Boogyo Sim, Keunwoo Kim, Taein Shin, Hyunwook Park, Seongguk Kim, Daehwan Lho, Keeyoung Son, Kyubong Kong, Seungtaek Jeong, Seonguk Choi, Jihun Kim, Joungho Kim
In this paper, the coaxial and shielded-twisted pair (STP) cables with intra-pair skew was analyzed by frequency domain analysis method by the equations in close-to-real intra-pair skew setup for high definition multimedia interface (HDMI) interface. For the high-speed interface, the intra-pair skew has become critical factor in terms of signal integrity. Heretofore, the intra-pair skew has not been commonly investigated in frequency domain for the high-speed data rate. To verify the intra-pair skew impact on the high-speed interface, the intra-pair skew location was distributed in the coaxial and STP cable assemblies for the real cable setup. Next, the skew impact was verified using frequency domain analysis and the eye-diagram. As the result, by the frequency-domain analysis, the differential loss and the mode conversion of coaxial cable assembly deteriorated due to the intra-pair skew, but STP did not deteriorate. Furthermore, the eye-diagram of the coaxial cable assembly with skew had smaller opening than without any skew, but of STP had little change.
{"title":"Intra-pair Skew Impact Analysis of High-speed Cables for HDMI Interface","authors":"Boogyo Sim, Keunwoo Kim, Taein Shin, Hyunwook Park, Seongguk Kim, Daehwan Lho, Keeyoung Son, Kyubong Kong, Seungtaek Jeong, Seonguk Choi, Jihun Kim, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947140","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947140","url":null,"abstract":"In this paper, the coaxial and shielded-twisted pair (STP) cables with intra-pair skew was analyzed by frequency domain analysis method by the equations in close-to-real intra-pair skew setup for high definition multimedia interface (HDMI) interface. For the high-speed interface, the intra-pair skew has become critical factor in terms of signal integrity. Heretofore, the intra-pair skew has not been commonly investigated in frequency domain for the high-speed data rate. To verify the intra-pair skew impact on the high-speed interface, the intra-pair skew location was distributed in the coaxial and STP cable assemblies for the real cable setup. Next, the skew impact was verified using frequency domain analysis and the eye-diagram. As the result, by the frequency-domain analysis, the differential loss and the mode conversion of coaxial cable assembly deteriorated due to the intra-pair skew, but STP did not deteriorate. Furthermore, the eye-diagram of the coaxial cable assembly with skew had smaller opening than without any skew, but of STP had little change.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947172
Ahsan Javaid, R. Achar, J. N. Tripathi
In this paper, analytical expressions are developed for estimating random jitter (RJ) in the presence of stochastic power supply noise for CMOS inverter circuits. The proposed approach employs probability density function of the propagation delay associated with a CMOS inverter in the presence of supply variations with normal distribution. The closed-form relations are further advanced to include the effects of load. The proposed model demonstrates a reasonably accurate prediction of RJ and yields significant speed-up compared to using a circuit simulator (HSPICE) for a case study with 22nm CMOS technology.
{"title":"Efficient Modeling of Random Jitter Due to Stochastic Power Supply Noise in CMOS Inverters","authors":"Ahsan Javaid, R. Achar, J. N. Tripathi","doi":"10.1109/EPEPS53828.2022.9947172","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947172","url":null,"abstract":"In this paper, analytical expressions are developed for estimating random jitter (RJ) in the presence of stochastic power supply noise for CMOS inverter circuits. The proposed approach employs probability density function of the propagation delay associated with a CMOS inverter in the presence of supply variations with normal distribution. The closed-form relations are further advanced to include the effects of load. The proposed model demonstrates a reasonably accurate prediction of RJ and yields significant speed-up compared to using a circuit simulator (HSPICE) for a case study with 22nm CMOS technology.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947152
Damian Marek, P. Triverio
An efficient parallel solver is proposed for extracting port parameters from electrical interconnects with many ports. We demonstrate that block iterative methods can be used to improve convergence rate and parallel efficiency. The proposed method is up to $16times$ faster than an existing method on structures with up to 128 ports and 3 million unknowns.
{"title":"An Efficient Parallel Electromagnetic Solver for Extracting Scattering Parameters from Large Electrical Interconnects With Many Ports","authors":"Damian Marek, P. Triverio","doi":"10.1109/EPEPS53828.2022.9947152","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947152","url":null,"abstract":"An efficient parallel solver is proposed for extracting port parameters from electrical interconnects with many ports. We demonstrate that block iterative methods can be used to improve convergence rate and parallel efficiency. The proposed method is up to $16times$ faster than an existing method on structures with up to 128 ports and 3 million unknowns.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947116
Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Hassan Ali, R. Murugan, Tony Tang
Radiation pattern measurements of a millimeter wave (mmWave) antenna integrated in a package possesses several challenges due to its miniaturized size, available feeding methods, and inherent structural limitations of the package that calls for an innovative solution. This paper discusses two novel approaches to feed a wideband antenna fabricated inside a flip-chip enhanced QFN (FCeQFN) using a standard waveguide in the frequency range of 140GHz to 220GHz. The two approaches support the proposed antenna characterization methodology by achieving a 41.25% and 100% of −10dB bandwidth with a maximum attenuation of 3dB and 3.34dB, respectively. Further, we discuss the performance comparison of these transitions along with their implementation feasibility. A brief description of measurement structures and antenna radiation pattern analysis for a slot bow-tie antenna is reported.
{"title":"Methods to Characterize Radiation Patterns of WR5 Band Integrated Antennas in a Flip-Chip Enhanced QFN Package","authors":"Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Hassan Ali, R. Murugan, Tony Tang","doi":"10.1109/EPEPS53828.2022.9947116","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947116","url":null,"abstract":"Radiation pattern measurements of a millimeter wave (mmWave) antenna integrated in a package possesses several challenges due to its miniaturized size, available feeding methods, and inherent structural limitations of the package that calls for an innovative solution. This paper discusses two novel approaches to feed a wideband antenna fabricated inside a flip-chip enhanced QFN (FCeQFN) using a standard waveguide in the frequency range of 140GHz to 220GHz. The two approaches support the proposed antenna characterization methodology by achieving a 41.25% and 100% of −10dB bandwidth with a maximum attenuation of 3dB and 3.34dB, respectively. Further, we discuss the performance comparison of these transitions along with their implementation feasibility. A brief description of measurement structures and antenna radiation pattern analysis for a slot bow-tie antenna is reported.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124654742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947103
P. Paladhi, Yanyan Zhang, Xianbo Yang, N. Pham, Megan Nguyen, M. Bohra, Junyan Tang, S. Chun, Joshua Myers, W. Becker, D. Dreps
With increasing bandwidth and higher transmission data rates in each generation, routing density in motherboards especially under module area have also increased proportionally. Maintaining signal integrity of high-speed channels under such dense routing conditions is becoming more challenging in each new product generation. This paper shows how via to trace coupling in under LGA area can give rise to increased NEXT values thereby causing channel margin loss and failure at high data rates.
{"title":"NEXT Effect in Pin-area Routing at Receiver End from Via to Trace Coupling in a 32 Gb/s Channel","authors":"P. Paladhi, Yanyan Zhang, Xianbo Yang, N. Pham, Megan Nguyen, M. Bohra, Junyan Tang, S. Chun, Joshua Myers, W. Becker, D. Dreps","doi":"10.1109/EPEPS53828.2022.9947103","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947103","url":null,"abstract":"With increasing bandwidth and higher transmission data rates in each generation, routing density in motherboards especially under module area have also increased proportionally. Maintaining signal integrity of high-speed channels under such dense routing conditions is becoming more challenging in each new product generation. This paper shows how via to trace coupling in under LGA area can give rise to increased NEXT values thereby causing channel margin loss and failure at high data rates.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：