Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947165
Chad M. Smutzer, Jordan R. Keuseman, C. Haider, B. Gilbert
Power delivery network (PDN) model development is often simplified using superports or pin-groups for high pin count devices. This approach significantly reduces model complexity but can compromise accuracy in holistic time- and frequency-domain analyses. In the context of the non-invasive current estimation (NICE) technique for packaged, high-performance integrated circuits (ICs), this paper describes the limitations of using pin-group PDN models in distributed impedance applications. DC error calibration factors are calculated, and tuned AC error compensation networks are proposed. These fundamental techniques for working with overly simplified models in highly distributed power integrity applications are derived and demonstrated through simulation and measurement on exemplar hardware.
{"title":"Network Model Compensation For Single-Point Measurements Of Multi-Pin Devices When Using Non-Invasive Current Estimation","authors":"Chad M. Smutzer, Jordan R. Keuseman, C. Haider, B. Gilbert","doi":"10.1109/EPEPS53828.2022.9947165","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947165","url":null,"abstract":"Power delivery network (PDN) model development is often simplified using superports or pin-groups for high pin count devices. This approach significantly reduces model complexity but can compromise accuracy in holistic time- and frequency-domain analyses. In the context of the non-invasive current estimation (NICE) technique for packaged, high-performance integrated circuits (ICs), this paper describes the limitations of using pin-group PDN models in distributed impedance applications. DC error calibration factors are calculated, and tuned AC error compensation networks are proposed. These fundamental techniques for working with overly simplified models in highly distributed power integrity applications are derived and demonstrated through simulation and measurement on exemplar hardware.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"35 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133043419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947123
Keunwoo Kim, Jung-Hyun Lee, Seokwoo Hong, Hyunwoo Kim, Boogyo Sim, Kyungjune Son, Taein Shin, Keeyoung Son, Jinyoung Kim, Kyubong Kong, Joungho Kim
In this paper, we propose a new board-to-board connector design for 5G mmWave and high-speed signaling. The proposed board-to-board connector has a socket shield and mid-plate between pins. The socket shell reduces electromagnetic interference (EMI), emitted to the outside and the mid-plate reduces crosstalk between terminals. We verified the signal integrity performance and EMI reduction effect of the newly added ground structures through EM simulation. However, due to the increased ground structure, the return current path of the signal is split, and resonances are generated. We analyzed the resonances through the J-field change according to the frequencies.
{"title":"A Low EMI Board-to-board Connector Design for 5G mmWave and High-speed Signaling","authors":"Keunwoo Kim, Jung-Hyun Lee, Seokwoo Hong, Hyunwoo Kim, Boogyo Sim, Kyungjune Son, Taein Shin, Keeyoung Son, Jinyoung Kim, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947123","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947123","url":null,"abstract":"In this paper, we propose a new board-to-board connector design for 5G mmWave and high-speed signaling. The proposed board-to-board connector has a socket shield and mid-plate between pins. The socket shell reduces electromagnetic interference (EMI), emitted to the outside and the mid-plate reduces crosstalk between terminals. We verified the signal integrity performance and EMI reduction effect of the newly added ground structures through EM simulation. However, due to the increased ground structure, the return current path of the signal is split, and resonances are generated. We analyzed the resonances through the J-field change according to the frequencies.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116123225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947193
C. Cho, Kwangho Kim, Manho Lee, Jaeyoung Shin, Sungjin Yoon, Youngjae Lee, Chayoung Song, Wooshin Choi, M. Kwak, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko
In high-speed SerDes channels, it becomes more important to reduce impedance mismatches to minimize signal return. Most of the mismatches are due to the differential via on PCB which is essential component to make up the PCIe Gen 5 system, and this mismatch should be reduced for the high-speed signal quality. To effectively minimize the mismatch, this paper presents an equation based TDR estimation model of the differential via, and the model is verified to commercial model of the coupled transmission line. And this paper also proposes a method for optimizing the design parameters of the differential via by applying a reward based on TDR impedance to PSO algorithm. The optimization procedure is then applied to one of the actual PCB designs to verify the optimized design parameters.
{"title":"Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm","authors":"C. Cho, Kwangho Kim, Manho Lee, Jaeyoung Shin, Sungjin Yoon, Youngjae Lee, Chayoung Song, Wooshin Choi, M. Kwak, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko","doi":"10.1109/EPEPS53828.2022.9947193","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947193","url":null,"abstract":"In high-speed SerDes channels, it becomes more important to reduce impedance mismatches to minimize signal return. Most of the mismatches are due to the differential via on PCB which is essential component to make up the PCIe Gen 5 system, and this mismatch should be reduced for the high-speed signal quality. To effectively minimize the mismatch, this paper presents an equation based TDR estimation model of the differential via, and the model is verified to commercial model of the coupled transmission line. And this paper also proposes a method for optimizing the design parameters of the differential via by applying a reward based on TDR impedance to PSO algorithm. The optimization procedure is then applied to one of the actual PCB designs to verify the optimized design parameters.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947115
Qinghao Zhang, Ruoyi Xie, F. Guo, Shashwat Sharma, Damian Marek, P. Triverio
We present a complete methodology to import and mesh the layout of complex interconnect networks for electromag-netic analysis. At first glance, these tasks may seem straightfor-ward. In reality, they require complex geometrical operations, which are not trivial to perform efficiently and robustly for realistic layouts. The methodology is based on publicly-available libraries and generates a conformal surface mesh suitable for the boundary element method. The method is tested on an entire IC package from the Packaging Benchmark Suite.
{"title":"An Efficient Methodology to Parse and Mesh Large Interconnect Layouts for Electromagnetic Analysis","authors":"Qinghao Zhang, Ruoyi Xie, F. Guo, Shashwat Sharma, Damian Marek, P. Triverio","doi":"10.1109/EPEPS53828.2022.9947115","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947115","url":null,"abstract":"We present a complete methodology to import and mesh the layout of complex interconnect networks for electromag-netic analysis. At first glance, these tasks may seem straightfor-ward. In reality, they require complex geometrical operations, which are not trivial to perform efficiently and robustly for realistic layouts. The methodology is based on publicly-available libraries and generates a conformal surface mesh suitable for the boundary element method. The method is tested on an entire IC package from the Packaging Benchmark Suite.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"226 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132074904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947108
Dries Bosman, Martijn Huynen, D. De Zutter, Xiao Sun, N. Pantano, G. van der Plas, E. Beyne, D. Ginste
In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.
{"title":"Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method","authors":"Dries Bosman, Martijn Huynen, D. De Zutter, Xiao Sun, N. Pantano, G. van der Plas, E. Beyne, D. Ginste","doi":"10.1109/EPEPS53828.2022.9947108","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947108","url":null,"abstract":"In this contribution, we propose a novel approach to rigorously model interconnect structures with an arbitrary convex polygonal cross-section and general, piecewise homogeneous, material parameters. A full-wave boundary integral equation formulation is combined with a differential surface admittance approach, invoking an extended form of the numerically fast Fokas method to construct the pertinent operator. Several examples validate our method and demonstrate its applicability to per-unit-of-length resistance and inductance characterization.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947140
Boogyo Sim, Keunwoo Kim, Taein Shin, Hyunwook Park, Seongguk Kim, Daehwan Lho, Keeyoung Son, Kyubong Kong, Seungtaek Jeong, Seonguk Choi, Jihun Kim, Joungho Kim
In this paper, the coaxial and shielded-twisted pair (STP) cables with intra-pair skew was analyzed by frequency domain analysis method by the equations in close-to-real intra-pair skew setup for high definition multimedia interface (HDMI) interface. For the high-speed interface, the intra-pair skew has become critical factor in terms of signal integrity. Heretofore, the intra-pair skew has not been commonly investigated in frequency domain for the high-speed data rate. To verify the intra-pair skew impact on the high-speed interface, the intra-pair skew location was distributed in the coaxial and STP cable assemblies for the real cable setup. Next, the skew impact was verified using frequency domain analysis and the eye-diagram. As the result, by the frequency-domain analysis, the differential loss and the mode conversion of coaxial cable assembly deteriorated due to the intra-pair skew, but STP did not deteriorate. Furthermore, the eye-diagram of the coaxial cable assembly with skew had smaller opening than without any skew, but of STP had little change.
{"title":"Intra-pair Skew Impact Analysis of High-speed Cables for HDMI Interface","authors":"Boogyo Sim, Keunwoo Kim, Taein Shin, Hyunwook Park, Seongguk Kim, Daehwan Lho, Keeyoung Son, Kyubong Kong, Seungtaek Jeong, Seonguk Choi, Jihun Kim, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947140","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947140","url":null,"abstract":"In this paper, the coaxial and shielded-twisted pair (STP) cables with intra-pair skew was analyzed by frequency domain analysis method by the equations in close-to-real intra-pair skew setup for high definition multimedia interface (HDMI) interface. For the high-speed interface, the intra-pair skew has become critical factor in terms of signal integrity. Heretofore, the intra-pair skew has not been commonly investigated in frequency domain for the high-speed data rate. To verify the intra-pair skew impact on the high-speed interface, the intra-pair skew location was distributed in the coaxial and STP cable assemblies for the real cable setup. Next, the skew impact was verified using frequency domain analysis and the eye-diagram. As the result, by the frequency-domain analysis, the differential loss and the mode conversion of coaxial cable assembly deteriorated due to the intra-pair skew, but STP did not deteriorate. Furthermore, the eye-diagram of the coaxial cable assembly with skew had smaller opening than without any skew, but of STP had little change.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947172
Ahsan Javaid, R. Achar, J. N. Tripathi
In this paper, analytical expressions are developed for estimating random jitter (RJ) in the presence of stochastic power supply noise for CMOS inverter circuits. The proposed approach employs probability density function of the propagation delay associated with a CMOS inverter in the presence of supply variations with normal distribution. The closed-form relations are further advanced to include the effects of load. The proposed model demonstrates a reasonably accurate prediction of RJ and yields significant speed-up compared to using a circuit simulator (HSPICE) for a case study with 22nm CMOS technology.
{"title":"Efficient Modeling of Random Jitter Due to Stochastic Power Supply Noise in CMOS Inverters","authors":"Ahsan Javaid, R. Achar, J. N. Tripathi","doi":"10.1109/EPEPS53828.2022.9947172","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947172","url":null,"abstract":"In this paper, analytical expressions are developed for estimating random jitter (RJ) in the presence of stochastic power supply noise for CMOS inverter circuits. The proposed approach employs probability density function of the propagation delay associated with a CMOS inverter in the presence of supply variations with normal distribution. The closed-form relations are further advanced to include the effects of load. The proposed model demonstrates a reasonably accurate prediction of RJ and yields significant speed-up compared to using a circuit simulator (HSPICE) for a case study with 22nm CMOS technology.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947116
Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Hassan Ali, R. Murugan, Tony Tang
Radiation pattern measurements of a millimeter wave (mmWave) antenna integrated in a package possesses several challenges due to its miniaturized size, available feeding methods, and inherent structural limitations of the package that calls for an innovative solution. This paper discusses two novel approaches to feed a wideband antenna fabricated inside a flip-chip enhanced QFN (FCeQFN) using a standard waveguide in the frequency range of 140GHz to 220GHz. The two approaches support the proposed antenna characterization methodology by achieving a 41.25% and 100% of −10dB bandwidth with a maximum attenuation of 3dB and 3.34dB, respectively. Further, we discuss the performance comparison of these transitions along with their implementation feasibility. A brief description of measurement structures and antenna radiation pattern analysis for a slot bow-tie antenna is reported.
{"title":"Methods to Characterize Radiation Patterns of WR5 Band Integrated Antennas in a Flip-Chip Enhanced QFN Package","authors":"Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Hassan Ali, R. Murugan, Tony Tang","doi":"10.1109/EPEPS53828.2022.9947116","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947116","url":null,"abstract":"Radiation pattern measurements of a millimeter wave (mmWave) antenna integrated in a package possesses several challenges due to its miniaturized size, available feeding methods, and inherent structural limitations of the package that calls for an innovative solution. This paper discusses two novel approaches to feed a wideband antenna fabricated inside a flip-chip enhanced QFN (FCeQFN) using a standard waveguide in the frequency range of 140GHz to 220GHz. The two approaches support the proposed antenna characterization methodology by achieving a 41.25% and 100% of −10dB bandwidth with a maximum attenuation of 3dB and 3.34dB, respectively. Further, we discuss the performance comparison of these transitions along with their implementation feasibility. A brief description of measurement structures and antenna radiation pattern analysis for a slot bow-tie antenna is reported.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124654742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947122
Wonsuk Choi, S. Kwak, Jaeseok Park, Jiyoung Do, Byeongseon Yun, Yoo-Jeong Kwon, Dongho Kim, Kyu-Sik Lee, Tae Young Kim, Wonyoung Kim, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song
As the operation of server system is accelerated, the importance of signal integrity (SI) and power integrity (PI) measurement methodology and modeling of dual in line memory module (DIMM) products is increasing. In this paper, we introduce the advanced methodology for on-chip SI/PI measurement and DRAM signal recovery with the DDR5 probing package development. Comparing with the conventional interposer, a new method of probing package has proved to be advantageous for high-speed signal measurement and signal recovery, and it can also be used as a useful tool for DRAM on-chip SI measurement and signal prediction in post DDR5 speed (beyond 6.4 Gbps).
随着服务器系统运行速度的加快，信号完整性(SI)和功率完整性(PI)的测量方法和dual - in - line memory module (DIMM)产品的建模变得越来越重要。本文介绍了基于DDR5探测封装开发的片上SI/PI测量和DRAM信号恢复的先进方法。与传统的中介器相比，一种新的探测封装方法被证明具有高速信号测量和信号恢复的优势，它也可以作为DRAM片上SI测量和信号预测的有用工具，在DDR5之后的速度(超过6.4 Gbps)。
{"title":"Advanced Measurement and Simulation Approach for DDR5 On-chip SI/PI with the Probing Package","authors":"Wonsuk Choi, S. Kwak, Jaeseok Park, Jiyoung Do, Byeongseon Yun, Yoo-Jeong Kwon, Dongho Kim, Kyu-Sik Lee, Tae Young Kim, Wonyoung Kim, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song","doi":"10.1109/EPEPS53828.2022.9947122","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947122","url":null,"abstract":"As the operation of server system is accelerated, the importance of signal integrity (SI) and power integrity (PI) measurement methodology and modeling of dual in line memory module (DIMM) products is increasing. In this paper, we introduce the advanced methodology for on-chip SI/PI measurement and DRAM signal recovery with the DDR5 probing package development. Comparing with the conventional interposer, a new method of probing package has proved to be advantageous for high-speed signal measurement and signal recovery, and it can also be used as a useful tool for DRAM on-chip SI measurement and signal prediction in post DDR5 speed (beyond 6.4 Gbps).","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947119
Daehwan Lho, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Boogyo Sim, Kyungjune Son, Keeyoung Son, Jihun Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Kyubong Kong, Joungho Kim
In this paper, we propose the deterministic policy gradient-based reinforcement learning for DDR5 memory signaling architecture optimization considering signal integrity. We convert the complex DDR5 memory signaling architecture optimization to the Markov decision process (MDP). The key limitation factor was found through the analysis of the hierarchical channel, and MDP was configured to solve it. The deterministic policy is essential for optimizing high-dimensional problems that have many continuous design parameters. For verification, we compare the proposed method with conventional methods such as random search (RS) and Bayesian optimization (BO) and other reinforcement learning algorithms such as the advantage actor-critic (A2C) and proximal policy optimization (PPO). RS and BO could not be properly optimized even after 10000 iterations of 1000 times, respectively, and A2C and PPO failed to optimize. As a result of comparison, the proposed method has the highest optimality, low computing time, and reusability.
{"title":"Deterministic Policy Gradient-based Reinforcement Learning for DDR5 Memory Signaling Architecture Optimization considering Signal Integrity","authors":"Daehwan Lho, Hyunwook Park, Keunwoo Kim, Seongguk Kim, Boogyo Sim, Kyungjune Son, Keeyoung Son, Jihun Kim, Seonguk Choi, Joonsang Park, Haeyeon Kim, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947119","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947119","url":null,"abstract":"In this paper, we propose the deterministic policy gradient-based reinforcement learning for DDR5 memory signaling architecture optimization considering signal integrity. We convert the complex DDR5 memory signaling architecture optimization to the Markov decision process (MDP). The key limitation factor was found through the analysis of the hierarchical channel, and MDP was configured to solve it. The deterministic policy is essential for optimizing high-dimensional problems that have many continuous design parameters. For verification, we compare the proposed method with conventional methods such as random search (RS) and Bayesian optimization (BO) and other reinforcement learning algorithms such as the advantage actor-critic (A2C) and proximal policy optimization (PPO). RS and BO could not be properly optimized even after 10000 iterations of 1000 times, respectively, and A2C and PPO failed to optimize. As a result of comparison, the proposed method has the highest optimality, low computing time, and reusability.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121685294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：