Photonic technology is increasingly used in applications in medicine, life and environmental science. Whereas currently many of these applications are implemented using some form of discrete (free-space) optics, much can be gained from a transition to Photonics Integrated Circuits. This follows the trends in the electronics industry where highly integrated electronic circuits have allowed the combination of many different functions in a small form factor. Just as it has done for the electronics industry, integrated optics will lead to smaller, cheaper, more reliable and more user friendly devices.
{"title":"Control the light where you need it: new development in accurate delivery of visible laser light","authors":"D. Geuzebroek, Joost van Kerkhof, A. Leinse","doi":"10.1117/12.2249030","DOIUrl":"https://doi.org/10.1117/12.2249030","url":null,"abstract":"Photonic technology is increasingly used in applications in medicine, life and environmental science. Whereas currently many of these applications are implemented using some form of discrete (free-space) optics, much can be gained from a transition to Photonics Integrated Circuits. This follows the trends in the electronics industry where highly integrated electronic circuits have allowed the combination of many different functions in a small form factor. Just as it has done for the electronics industry, integrated optics will lead to smaller, cheaper, more reliable and more user friendly devices.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the early phases of technology development, designers and process engineers have to converge toward efficient design rules. Their calculations are based on process assumptions and result in a design rule based on known process variability capabilities while taking into account enough margin to be safe not only for yield but especially for reliability. Unfortunately, even if designs tend to be regular, efficient design densities are still requiring aggressive configurations from which it is difficult to estimate dimension variabilities. Indeed, for a process engineer it is rather straightforward to estimate or even measure simple one-dimensional features (arrays of Lines & Spaces at various CD and pitches), but it starts to be less obvious for complex multidimensional features. After a context description related to the process assumptions, we will outline the work flow which is under evaluation to enable robust metrology of 2 dimensional complex features. Enabling new metrology possibilities reveals that process hotspots are showing complex behavior from lithography to etch pattern transfer. In this work we studied the interaction of lithography variability and etching for a mature 28 nm CMOS process. To study this interaction we used a test feature that has been found very sensitive to lithography process variations. This so-called “golden” hotspot shows edge-to-edge geometries from 88nm to 150nm, thus comprising all the through pitch physics in the lithography pattern transfer [1, 2]. It consists of three trenches. From previous work it was known that through trench there is a systematic variation in best focus due to the Mask 3D effects. At a given chosen focus, there is a distinct difference in profiles for the three trenches that will lead to pattern displacement effects during the etch transfer.
{"title":"Translation of lithography variability into after-etch performance: monitoring of golden hotspot","authors":"J. Finders, T. Kiers, B. Le Gratiet, A. Lakcher","doi":"10.1117/12.2249565","DOIUrl":"https://doi.org/10.1117/12.2249565","url":null,"abstract":"In the early phases of technology development, designers and process engineers have to converge toward efficient design rules. Their calculations are based on process assumptions and result in a design rule based on known process variability capabilities while taking into account enough margin to be safe not only for yield but especially for reliability. Unfortunately, even if designs tend to be regular, efficient design densities are still requiring aggressive configurations from which it is difficult to estimate dimension variabilities. Indeed, for a process engineer it is rather straightforward to estimate or even measure simple one-dimensional features (arrays of Lines & Spaces at various CD and pitches), but it starts to be less obvious for complex multidimensional features. After a context description related to the process assumptions, we will outline the work flow which is under evaluation to enable robust metrology of 2 dimensional complex features. Enabling new metrology possibilities reveals that process hotspots are showing complex behavior from lithography to etch pattern transfer. In this work we studied the interaction of lithography variability and etching for a mature 28 nm CMOS process. To study this interaction we used a test feature that has been found very sensitive to lithography process variations. This so-called “golden” hotspot shows edge-to-edge geometries from 88nm to 150nm, thus comprising all the through pitch physics in the lithography pattern transfer [1, 2]. It consists of three trenches. From previous work it was known that through trench there is a systematic variation in best focus due to the Mask 3D effects. At a given chosen focus, there is a distinct difference in profiles for the three trenches that will lead to pattern displacement effects during the etch transfer.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114772211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Teyssèdre, S. Landis, C. Thanner, V. Schauer, M. Laure, W. Zorbach, L. Pain, S. Bos, M. Eibelhuber, M. Wimplinger
In this paper a first Critical Dimension (CD) uniformity assessment onto 200 mm wafers printed with the SmartNILTM technology available in the HERCULES® NIL equipment platform is proposed. The work brings focus on sub micrometer resolution features with a depth between 220 and 433 nm. The silicon masters were manufactured with 193 optical lithography and dry etching. A complete Scanning Electron Microscopy (SEM) characterizations were performed over the full masters surface prior to the imprint process. Repeatability tests were performed over 25 wafers first and then on 100 wafers to collect statistics and the CD distribution within a wafer and also wafer to wafer. The data revealed that the CD is evolving imprint after imprint and an explanation based on polymer shrinkage is proposed.
{"title":"Critical dimension uniformity characterization of nanoimprinted trenches for high volume manufacturing qualification","authors":"H. Teyssèdre, S. Landis, C. Thanner, V. Schauer, M. Laure, W. Zorbach, L. Pain, S. Bos, M. Eibelhuber, M. Wimplinger","doi":"10.1117/12.2250194","DOIUrl":"https://doi.org/10.1117/12.2250194","url":null,"abstract":"In this paper a first Critical Dimension (CD) uniformity assessment onto 200 mm wafers printed with the SmartNILTM technology available in the HERCULES® NIL equipment platform is proposed. The work brings focus on sub micrometer resolution features with a depth between 220 and 433 nm. The silicon masters were manufactured with 193 optical lithography and dry etching. A complete Scanning Electron Microscopy (SEM) characterizations were performed over the full masters surface prior to the imprint process. Repeatability tests were performed over 25 wafers first and then on 100 wafers to collect statistics and the CD distribution within a wafer and also wafer to wafer. The data revealed that the CD is evolving imprint after imprint and an explanation based on polymer shrinkage is proposed.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129792456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the specific requirements of the 14nm and 20nm site applications a new CD map approach was developed at the AMTC. This approach relies on a well established machine learning technique called recursive partitioning. Recursive partitioning is a powerful technique which creates a decision tree by successively testing whether the quantity of interest can be explained by one of the supplied covariates. The test performed is generally a statistical test with a pre-supplied significance level. Once the test indicates significant association between the variable of interest and a covariate a split performed at a threshold value which minimizes the variation within the newly attained groups. This partitioning is recurred until either no significant association can be detected or the resulting sub group size falls below a pre-supplied level.
{"title":"CD process control through machine learning","authors":"C. Utzny","doi":"10.1117/12.2248903","DOIUrl":"https://doi.org/10.1117/12.2248903","url":null,"abstract":"For the specific requirements of the 14nm and 20nm site applications a new CD map approach was developed at the AMTC. This approach relies on a well established machine learning technique called recursive partitioning. Recursive partitioning is a powerful technique which creates a decision tree by successively testing whether the quantity of interest can be explained by one of the supplied covariates. The test performed is generally a statistical test with a pre-supplied significance level. Once the test indicates significant association between the variable of interest and a covariate a split performed at a threshold value which minimizes the variation within the newly attained groups. This partitioning is recurred until either no significant association can be detected or the resulting sub group size falls below a pre-supplied level.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"403 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121794919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Bottiglieri, T. Last, Albert Colina, E. van Setten, G. Rispens, J. van Schoot, K. van Ingen Schenau
This paper presents some of the main imaging properties introduced with the design of a possible new EUV High-NA (NA > 0.5) exposure system with anamorphic projection lens, a concept not new in optics but applied for the first time in semiconductor lithography. The system is projected to use a demagnification of 4 in the X-direction and of 8 in the Y-direction. We show that a new definition of the Mask Error Factor needs to be used in order to describe correctly the property introduced by the anamorphic optics. Moreover, for both 1-Dimensional (1D) and 2-Dimensional (2D) features the reticle writing error in the low demagnification direction X is more critical than the error in high demagnification direction Y. The effects of the change in demagnification on imaging are described on an elementary case, and are ultimately linked to the basic physical phenomenon of diffraction.
本文介绍了一种可能的新型EUV高NA (NA > 0.5)失真投影透镜曝光系统的主要成像特性，这一概念在光学上并不新鲜，但首次应用于半导体光刻。该系统预计在x方向使用4倍的减倍倍率，在y方向使用8倍的减倍倍率。为了正确地描述变形光学引入的特性，需要使用新的掩模误差因子的定义。此外，对于一维(1D)和二维(2D)特征而言，低退倍方向X上的光栅书写误差比高退倍方向y上的误差更为关键。本文从一个基本情况描述了退倍变化对成像的影响，并最终将其与衍射的基本物理现象联系起来。
{"title":"Anamorphic imaging at high-NA EUV: mask error factor and interaction between demagnification and lithographic metrics","authors":"G. Bottiglieri, T. Last, Albert Colina, E. van Setten, G. Rispens, J. van Schoot, K. van Ingen Schenau","doi":"10.1117/12.2250630","DOIUrl":"https://doi.org/10.1117/12.2250630","url":null,"abstract":"This paper presents some of the main imaging properties introduced with the design of a possible new EUV High-NA (NA > 0.5) exposure system with anamorphic projection lens, a concept not new in optics but applied for the first time in semiconductor lithography. The system is projected to use a demagnification of 4 in the X-direction and of 8 in the Y-direction. We show that a new definition of the Mask Error Factor needs to be used in order to describe correctly the property introduced by the anamorphic optics. Moreover, for both 1-Dimensional (1D) and 2-Dimensional (2D) features the reticle writing error in the low demagnification direction X is more critical than the error in high demagnification direction Y. The effects of the change in demagnification on imaging are described on an elementary case, and are ultimately linked to the basic physical phenomenon of diffraction.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134182213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the process of semicondutcor fabrication the translation of the final product requirements into specific targets for each component of the manufacturing process is one of the most demanding tasks. This involves the careful assessment of the error budgets of each component as well as the sensible balancing of the costs implied by the requirements. Photolithographic masks play a pivotal role in the semiconductor fabrication. This attributes a crucial role to mask error budgeting within the overall wafer production process. Masks with borderline performance with respect to the wafer fabrication requirements have a detrimental effect on the wafer process window thus inducing delays and costs. However, prohibitively strict mask specifications will induce large costs and delays in the mask manufacturing process. Thus setting smart control mechanisms for mask quality assessment is highly relevant for an efficient production flow. To this end GLOBALFOUNDRIES and the AMTC have set up a new mask specification check to enable a smart ship to control process for mask manufacturing. Within this process the mask CD distribution is checked as to whether it is commensurable with the advanced dose control capabilities of the stepper in the wafer factory. If this is the case, masks with borderline CD performance will be usable within the manufacturing process as the signatures can be compensated. In this paper we give a detailed explanation of the smart ship control approach with its implications for mask quality.
{"title":"Smart mask ship to control for enhanced on wafer CD performance","authors":"C. Utzny, K. Schumacher, R. Seltmann","doi":"10.1117/12.2248889","DOIUrl":"https://doi.org/10.1117/12.2248889","url":null,"abstract":"In the process of semicondutcor fabrication the translation of the final product requirements into specific targets for each component of the manufacturing process is one of the most demanding tasks. This involves the careful assessment of the error budgets of each component as well as the sensible balancing of the costs implied by the requirements. Photolithographic masks play a pivotal role in the semiconductor fabrication. This attributes a crucial role to mask error budgeting within the overall wafer production process. Masks with borderline performance with respect to the wafer fabrication requirements have a detrimental effect on the wafer process window thus inducing delays and costs. However, prohibitively strict mask specifications will induce large costs and delays in the mask manufacturing process. Thus setting smart control mechanisms for mask quality assessment is highly relevant for an efficient production flow. To this end GLOBALFOUNDRIES and the AMTC have set up a new mask specification check to enable a smart ship to control process for mask manufacturing. Within this process the mask CD distribution is checked as to whether it is commensurable with the advanced dose control capabilities of the stepper in the wafer factory. If this is the case, masks with borderline CD performance will be usable within the manufacturing process as the signatures can be compensated. In this paper we give a detailed explanation of the smart ship control approach with its implications for mask quality.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Bolten, T. Wahlbrink, A. Prinzen, C. Porschatis, H. Lerch, A. Giesecke
In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today’s low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.
{"title":"Photonic integrated circuits: new challenges for lithography","authors":"J. Bolten, T. Wahlbrink, A. Prinzen, C. Porschatis, H. Lerch, A. Giesecke","doi":"10.1117/12.2248325","DOIUrl":"https://doi.org/10.1117/12.2248325","url":null,"abstract":"In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today’s low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115801736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Soni, Sankaranarayanan Paninjath, Mark Pereira, P. Buck, P. Thwaite
EUV Defect avoidance techniques will play a vital role in extreme ultraviolet lithography (EUVL) photomask fabrication with the anticipation that defect free mask blanks won’t be available and that cost effective techniques will not be available for defect repairing. In addition, mask shops may not have a large inventory of expensive EUV mask blanks. Given these facts, defect avoidance can be used as cost effective technique to optimize the mask blank and design data (mask data) pair selection across mask blank manufacturers and mask shops so that overall mask blank utilization can be enhanced. In previous work, it was determined that the pattern shift based solution increases the chance that a defective mask blank can be used that would otherwise be discarded [1]. In pattern shift, design data is shifted such that defects are either moved to isolated regions or hidden under the patterns that are written. However pattern shifts techniques don’t perform well with masks with higher defect counts. Pattern shift techniques in this form assume all defects to be equally critical. In addition, a defect is critical or important only if it lands on the main pattern. A defect landing on fill, sub-resolution assist feature (SRAF) or fiducial areas may not be critical. In this paper we assess the performance of pattern shift techniques assuming defects that are not critical based upon size or type, as well as defects landing in non-critical areas (smart shift) can be ignored. In a production mask manufacturing environment it is necessary to co-optimize and prioritize blank-design pairing for multiple mask layouts in the queue with the available blanks. A blank-design pairing tool maximizes the utilization of blanks by finding the best pairing between blanks and design data so that the maximum number of mask blanks can be used. In this paper we also propose a novel process which would optimize the usage of costly EUV mask blanks across mask blank manufacturers and mask shops which write masks.
{"title":"Enhancing EUV mask blanks usability through smart shift and blank-design pairing optimization","authors":"R. Soni, Sankaranarayanan Paninjath, Mark Pereira, P. Buck, P. Thwaite","doi":"10.1117/12.2250106","DOIUrl":"https://doi.org/10.1117/12.2250106","url":null,"abstract":"EUV Defect avoidance techniques will play a vital role in extreme ultraviolet lithography (EUVL) photomask fabrication with the anticipation that defect free mask blanks won’t be available and that cost effective techniques will not be available for defect repairing. In addition, mask shops may not have a large inventory of expensive EUV mask blanks. Given these facts, defect avoidance can be used as cost effective technique to optimize the mask blank and design data (mask data) pair selection across mask blank manufacturers and mask shops so that overall mask blank utilization can be enhanced. In previous work, it was determined that the pattern shift based solution increases the chance that a defective mask blank can be used that would otherwise be discarded [1]. In pattern shift, design data is shifted such that defects are either moved to isolated regions or hidden under the patterns that are written. However pattern shifts techniques don’t perform well with masks with higher defect counts. Pattern shift techniques in this form assume all defects to be equally critical. In addition, a defect is critical or important only if it lands on the main pattern. A defect landing on fill, sub-resolution assist feature (SRAF) or fiducial areas may not be critical. In this paper we assess the performance of pattern shift techniques assuming defects that are not critical based upon size or type, as well as defects landing in non-critical areas (smart shift) can be ignored. In a production mask manufacturing environment it is necessary to co-optimize and prioritize blank-design pairing for multiple mask layouts in the queue with the available blanks. A blank-design pairing tool maximizes the utilization of blanks by finding the best pairing between blanks and design data so that the maximum number of mask blanks can be used. In this paper we also propose a novel process which would optimize the usage of costly EUV mask blanks across mask blank manufacturers and mask shops which write masks.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128096441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Laforge, Caroline Rabot, Ningning Wang, Z. Pavlović, P. McCloskey, C. O'Mathúna
Epoxy-based resist SU-8 is widely used in the development and fabrication of high-aspect-ratio (HAR) MEMS structures. It has proven to be a suitable photoresist combining thick layer coating and good adhesion on silicon substrates as well as possessing good mechanical and chemical stability. However, the trend towards minia- turization and increasing packaging density has pushed the demand for challenging micro-machining processes. As an example, a novel design of a MEMS microinductor requires a dielectric permanent layer coated in deep silicon trenches in order to insulate copper windings from the magnetic material deposited in these trenches. This requires the development of a photolithography process which enables the coating of a void-free layer filling the trenches. In this paper, the use of thick SU-8 photoresist for filling deep silicon trenches is investigated. Different SU-8 formulations are analyzed, processed and results are compared. As a result, an optimized process is developed to achieve void-free filled trenches and a uniform planar layer above them, with near vertical sidewall patterns.
{"title":"A study of SU-8 photoresist in deep trenches for silicon-embedded microinductors","authors":"E. Laforge, Caroline Rabot, Ningning Wang, Z. Pavlović, P. McCloskey, C. O'Mathúna","doi":"10.1117/12.2247894","DOIUrl":"https://doi.org/10.1117/12.2247894","url":null,"abstract":"Epoxy-based resist SU-8 is widely used in the development and fabrication of high-aspect-ratio (HAR) MEMS structures. It has proven to be a suitable photoresist combining thick layer coating and good adhesion on silicon substrates as well as possessing good mechanical and chemical stability. However, the trend towards minia- turization and increasing packaging density has pushed the demand for challenging micro-machining processes. As an example, a novel design of a MEMS microinductor requires a dielectric permanent layer coated in deep silicon trenches in order to insulate copper windings from the magnetic material deposited in these trenches. This requires the development of a photolithography process which enables the coating of a void-free layer filling the trenches. In this paper, the use of thick SU-8 photoresist for filling deep silicon trenches is investigated. Different SU-8 formulations are analyzed, processed and results are compared. As a result, an optimized process is developed to achieve void-free filled trenches and a uniform planar layer above them, with near vertical sidewall patterns.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 – 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.
{"title":"SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution","authors":"R. Voorkamp, M. Verschuuren, R. van Brakel","doi":"10.1117/12.2246787","DOIUrl":"https://doi.org/10.1117/12.2246787","url":null,"abstract":"Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 – 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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