A numerical study of EUV Bragg mirrors with superstructures is presented. These modifications of the standard Mo/Si mirror are periodic superlattices as well as depth grading of the superlattice multilayers. The main results concern a narrowing of the normal incidence peak and all-angle reflection at 13.5 nm. Best results are obtained with a combination of superlattices with 4 and 5 superperiods and depth grading. The effect of the spectral width of the EUV source is also taken into account.
{"title":"Photonic superlattice multilayers for EUV lithography infrastructure","authors":"F. Kuchar, R. Meisels","doi":"10.1117/12.2322410","DOIUrl":"https://doi.org/10.1117/12.2322410","url":null,"abstract":"A numerical study of EUV Bragg mirrors with superstructures is presented. These modifications of the standard Mo/Si mirror are periodic superlattices as well as depth grading of the superlattice multilayers. The main results concern a narrowing of the normal incidence peak and all-angle reflection at 13.5 nm. Best results are obtained with a combination of superlattices with 4 and 5 superperiods and depth grading. The effect of the spectral width of the EUV source is also taken into account.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133172974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Gilgenkrantz, Stephen Kim, Wooil Han, Minyoung Park, Min Tsao
With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.
{"title":"Maximizing utilization of large-scale mask data preparation clusters","authors":"P. Gilgenkrantz, Stephen Kim, Wooil Han, Minyoung Park, Min Tsao","doi":"10.1117/12.2326553","DOIUrl":"https://doi.org/10.1117/12.2326553","url":null,"abstract":"With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128727039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clyde Browning, S. Postnikov, M. Milléquant, S. Bayle, P. Schiavone
Designs for photonic devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles. Reticle Enhancement Techniques (RET) that are commonly used for CMOS manufacturing now are applied to curvilinear data patterns for the same reasons of enhancing pattern fidelity. Common techniques for curvilinear data processing include Manhattanization, jog removal, and jog alignment. We propose a novel method of describing curvilinear shapes in terms of curves reconstructed between control points. Such representation of curvilinear shapes brings many benefits in terms of pattern description (improved fidelity, file compaction), correction and verification. For example, it allows smooth displacements during the design correction procedure for process effects. The conventional correction by biasing each fragment illustrates the curve-based biasing where only the control points have been moved and the corrected shape was then reconstructed by connecting the control points in their new positions by the new curves. This method results in faster computation because there are fewer locations to adjust geometry, easier convergence and intrinsic continuity between edges. It also affords significant reduction of the design file size. Besides processing curvilinear pattern data, verification is also required after any original pattern modifications. Mask Rule Checks (MRC) are considered as standard step in any design data preparation flows, but the conventional MRC algorithms are conceived for Manhattan designs and as such they often result in numerous false errors or even missing errors when applied to photonics or ILT (Inverse Lithography Technology) designs. In addition, MRC for photonic layouts require much more than basic width and space checking. We developed a verification technology compliant with curvilinear layouts. The new MRC technique is also based on curve representation of the original design comparing directly the curves instead of the straight fragments. It permits to have only one error flag per curve instead of multiple errors seen in fragment-by-fragment MRC.
{"title":"Curvilinear data processing methods and verification","authors":"Clyde Browning, S. Postnikov, M. Milléquant, S. Bayle, P. Schiavone","doi":"10.1117/12.2326599","DOIUrl":"https://doi.org/10.1117/12.2326599","url":null,"abstract":"Designs for photonic devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles. Reticle Enhancement Techniques (RET) that are commonly used for CMOS manufacturing now are applied to curvilinear data patterns for the same reasons of enhancing pattern fidelity. Common techniques for curvilinear data processing include Manhattanization, jog removal, and jog alignment. We propose a novel method of describing curvilinear shapes in terms of curves reconstructed between control points. Such representation of curvilinear shapes brings many benefits in terms of pattern description (improved fidelity, file compaction), correction and verification. For example, it allows smooth displacements during the design correction procedure for process effects. The conventional correction by biasing each fragment illustrates the curve-based biasing where only the control points have been moved and the corrected shape was then reconstructed by connecting the control points in their new positions by the new curves. This method results in faster computation because there are fewer locations to adjust geometry, easier convergence and intrinsic continuity between edges. It also affords significant reduction of the design file size. Besides processing curvilinear pattern data, verification is also required after any original pattern modifications. Mask Rule Checks (MRC) are considered as standard step in any design data preparation flows, but the conventional MRC algorithms are conceived for Manhattan designs and as such they often result in numerous false errors or even missing errors when applied to photonics or ILT (Inverse Lithography Technology) designs. In addition, MRC for photonic layouts require much more than basic width and space checking. We developed a verification technology compliant with curvilinear layouts. The new MRC technique is also based on curve representation of the original design comparing directly the curves instead of the straight fragments. It permits to have only one error flag per curve instead of multiple errors seen in fragment-by-fragment MRC.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127914144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ducoté, A. Lakcher, L. Bidault, Antoine-Regis Philipot, A. Ostrovsky, E. Mortini, B. Le-Gratiet
The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.
{"title":"Microlens under melt in-line monitoring based on application of neural network automatic defect classification","authors":"J. Ducoté, A. Lakcher, L. Bidault, Antoine-Regis Philipot, A. Ostrovsky, E. Mortini, B. Le-Gratiet","doi":"10.1117/12.2326397","DOIUrl":"https://doi.org/10.1117/12.2326397","url":null,"abstract":"The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132750447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Schneider, D. Kaiser, N. Morgana, M. Heller, H. Feick
Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.
{"title":"Revival of grayscale technique in power semiconductor processing under low-cost manufacturing constraints","authors":"J. Schneider, D. Kaiser, N. Morgana, M. Heller, H. Feick","doi":"10.1117/12.2326006","DOIUrl":"https://doi.org/10.1117/12.2326006","url":null,"abstract":"Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the substantial surge in the need for high-end masks it becomes increasingly important to raise the capacity of the corresponding production lines. To this end the efficient qualification of matching tools and processes within a production line is of utmost relevance. Matching is typically judged by the processing of dedicated lots on the new tool and process. The amount of qualification lots should on the one hand be very small, as the production of qualification plates is expensive and uses capacity of the production corridor. On the other hand the strict requirements of high-end products induce very tight specification limits on the matching criteria. It is thus often very difficult to assess tool or process matching on the basis of a small amount of lots. In this paper we expound on a machine learning based strategy which assesses the mask characteristics of a qualification plate by learning the typical behavior of these characteristics within the production line variations. We show that by careful selection of reference production plates as well as by setting specification limits based on the production behavior we can manage the qualification tasks efficiently by using a small number of masks. The specification characteristics as well as the specific limits are selected and determined using a Naïve Bayes learner. The resulting performance for prediction of tool and process matching is assessed by considering the resulting receiving operator curve. As a result we obtain an approach towards the assessment of qualification data which enables engineers to assess the tool and process matching using a small amount of matching data under the constraint of substantial measurement uncertainties. As an outlook we discuss how this approach can be used to examine the reverse question of detecting process failures, i.e. the automated ability to raise a flag when the current production characteristics start to deviate from their typical characteristics. Overall, in this paper we show how the rapidly evolving field of machine learning increasingly impacts the semiconductor production process.
{"title":"Machine learning methods applied to process qualification","authors":"M. Herrmann, Stefan Meusemann, C. Utzny","doi":"10.1117/12.2323605","DOIUrl":"https://doi.org/10.1117/12.2323605","url":null,"abstract":"With the substantial surge in the need for high-end masks it becomes increasingly important to raise the capacity of the corresponding production lines. To this end the efficient qualification of matching tools and processes within a production line is of utmost relevance. Matching is typically judged by the processing of dedicated lots on the new tool and process. The amount of qualification lots should on the one hand be very small, as the production of qualification plates is expensive and uses capacity of the production corridor. On the other hand the strict requirements of high-end products induce very tight specification limits on the matching criteria. It is thus often very difficult to assess tool or process matching on the basis of a small amount of lots. In this paper we expound on a machine learning based strategy which assesses the mask characteristics of a qualification plate by learning the typical behavior of these characteristics within the production line variations. We show that by careful selection of reference production plates as well as by setting specification limits based on the production behavior we can manage the qualification tasks efficiently by using a small number of masks. The specification characteristics as well as the specific limits are selected and determined using a Naïve Bayes learner. The resulting performance for prediction of tool and process matching is assessed by considering the resulting receiving operator curve. As a result we obtain an approach towards the assessment of qualification data which enables engineers to assess the tool and process matching using a small amount of matching data under the constraint of substantial measurement uncertainties. As an outlook we discuss how this approach can be used to examine the reverse question of detecting process failures, i.e. the automated ability to raise a flag when the current production characteristics start to deviate from their typical characteristics. Overall, in this paper we show how the rapidly evolving field of machine learning increasingly impacts the semiconductor production process.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ushkov, M. Bichotte, I. Verrier, T. Kampfe, Y. Jourlin
We present both modeling and experimental results devoted to design, fabrication and characterization of metal covered hexagonal diffraction gratings. Variation of exposition and development time allow to modify the shape of the elementary cell, leaving the depth and periodicity unchanged. The fabrication process was modeled using real parameters of the lithography bench and the photoresist, substantially improving experimental results. The high quality of metal covered gratings is confirmed by excitation of plasmonic resonances, which are in a good agreement with theoretical predictions. The described approach allows to better understand plasmonic effects in 2D periodic structures and leads to an optimized design of plasmonic sensors.
{"title":"Plasmonic resonances in metal covered 2D hexagonal gratings fabricated by interference lithography","authors":"A. Ushkov, M. Bichotte, I. Verrier, T. Kampfe, Y. Jourlin","doi":"10.1117/12.2323763","DOIUrl":"https://doi.org/10.1117/12.2323763","url":null,"abstract":"We present both modeling and experimental results devoted to design, fabrication and characterization of metal covered hexagonal diffraction gratings. Variation of exposition and development time allow to modify the shape of the elementary cell, leaving the depth and periodicity unchanged. The fabrication process was modeled using real parameters of the lithography bench and the photoresist, substantially improving experimental results. The high quality of metal covered gratings is confirmed by excitation of plasmonic resonances, which are in a good agreement with theoretical predictions. The described approach allows to better understand plasmonic effects in 2D periodic structures and leads to an optimized design of plasmonic sensors.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Timmermans, C. van Lare, J. McNamara, E. van Setten, J. Finders
Mitigation of mask 3D effects is essential for EUV imaging of high resolution features. The 3D EUV masks give rise to phase effects over the diffracted orders and potentially distort the image on the wafer. These phase effects may reduce contrast, result in pattern shifts and result in best focus variations on wafer. Two variations on the current absorber are investigated to their impact on reduction of M3D effects and impact on image quality. Use of high-k absorber materials allows for thinner masks to be used and helps to reduce averse M3D effects. Attenuated phase shift masks work by allowing a higher optical transmission while giving a phase shift to the transmitted light, which further improves image contrast on wafer and also enables thinner absorbers to be used. Attenuated PSM absorbers show a stronger variation in imaging performance through incidence angle onto the reticle. It has been shown that this results in a variation in imaging performance for varying features and pitches. Specifically of interest is how NILS through focus is influenced by the different absorbers. Phase shift masks show better performance for NILS through focus on contact holes, and high-k masks work well for dense lines.
{"title":"Alternative absorber materials for mitigation of mask 3D effects in high NA EUV lithography","authors":"F. Timmermans, C. van Lare, J. McNamara, E. van Setten, J. Finders","doi":"10.1117/12.2326805","DOIUrl":"https://doi.org/10.1117/12.2326805","url":null,"abstract":"Mitigation of mask 3D effects is essential for EUV imaging of high resolution features. The 3D EUV masks give rise to phase effects over the diffracted orders and potentially distort the image on the wafer. These phase effects may reduce contrast, result in pattern shifts and result in best focus variations on wafer. Two variations on the current absorber are investigated to their impact on reduction of M3D effects and impact on image quality. Use of high-k absorber materials allows for thinner masks to be used and helps to reduce averse M3D effects. Attenuated phase shift masks work by allowing a higher optical transmission while giving a phase shift to the transmitted light, which further improves image contrast on wafer and also enables thinner absorbers to be used. Attenuated PSM absorbers show a stronger variation in imaging performance through incidence angle onto the reticle. It has been shown that this results in a variation in imaging performance for varying features and pitches. Specifically of interest is how NILS through focus is influenced by the different absorbers. Phase shift masks show better performance for NILS through focus on contact holes, and high-k masks work well for dense lines.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SEM metrology is widely used in microelectronics to control patterns dimensions after many processes, especially patterning. Process control is achieved by verifying that experimental dimensions match targeted ones. However SEM metrology may give erroneous measurements if strong charging occurs. Charging effect impacts on the SEM image contrast and introduces artefacts. This article intends to report on the modeling of the physical phenomena occurring when the electron gun scans a sample and how charging effect occurs. For this, charge dynamics are modeled by taking into account the drift kinetics and the diffusion of electrons. The corresponding Partial Differential Equation system is solved using FEniCS open software. First, we show that when only top view measurement are modeled, the typical contrast of SEM pictures can not be predicted. Second, cross section views are modeled. This time, the expected contrast behavior is obtained. Finally, a full 3D simulation is presented.
{"title":"FEM simulation of charging effect during SEM metrology","authors":"D. Nguyen, J. Tortai, M. Abaidi, P. Schiavone","doi":"10.1117/12.2326609","DOIUrl":"https://doi.org/10.1117/12.2326609","url":null,"abstract":"SEM metrology is widely used in microelectronics to control patterns dimensions after many processes, especially patterning. Process control is achieved by verifying that experimental dimensions match targeted ones. However SEM metrology may give erroneous measurements if strong charging occurs. Charging effect impacts on the SEM image contrast and introduces artefacts. This article intends to report on the modeling of the physical phenomena occurring when the electron gun scans a sample and how charging effect occurs. For this, charge dynamics are modeled by taking into account the drift kinetics and the diffusion of electrons. The corresponding Partial Differential Equation system is solved using FEniCS open software. First, we show that when only top view measurement are modeled, the typical contrast of SEM pictures can not be predicted. Second, cross section views are modeled. This time, the expected contrast behavior is obtained. Finally, a full 3D simulation is presented.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121123619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jordan Belissard, J. Hazart, S. Labbé, Faouzi Triki
Although the critical dimension (CD) is getting smaller following the ITRS roadmap, the scanning electron microscope (CD-SEM) is still the most general purpose tool used for non-destructive metrology in the semiconductor industry. However, we are now dealing with patterns whose dimensions are of the same order of magnitude as the electron interaction volume and therefore, the usual edge-based metrology methods fail. Like scatterometry has extended the resolution of optical imaging metrology through complex modeling of light-matter interaction, some electrons-matter simulation models have been proposed. They could be used to improve accuracy and precision of CD-SEM metrology. However, these model-based approaches also face to fundamental limits mainly due to probe size with respect to the considered structure and noise. This paper analyses these limits assuming the model is perfect and the microscope has no systematic defect. In this simulation study, we have used the model proposed by D. Nyyssonen, assuming to perfectly represent the SEM effects in the image. The feature of interest is limited to isolated trapezoidal lines with various CD, sidewall angles (SWA) and heights. We have carried out the study with several beam energies, tilts and probe sizes. Surprisingly enough, sensitivity analysis shows that with typical noise amplitude, sidewall angle can be determined with a reasonable precision using SEM images. Single tilted beam SEM images can also bring advantage to measure patterns height. Since these precision figures depend on the geometries, we provide useful graphs giving the ultimate precision for various dimensions (CD, height, SWA).
{"title":"Limits of model-based CD-SEM metrology","authors":"Jordan Belissard, J. Hazart, S. Labbé, Faouzi Triki","doi":"10.1117/12.2323696","DOIUrl":"https://doi.org/10.1117/12.2323696","url":null,"abstract":"Although the critical dimension (CD) is getting smaller following the ITRS roadmap, the scanning electron microscope (CD-SEM) is still the most general purpose tool used for non-destructive metrology in the semiconductor industry. However, we are now dealing with patterns whose dimensions are of the same order of magnitude as the electron interaction volume and therefore, the usual edge-based metrology methods fail. Like scatterometry has extended the resolution of optical imaging metrology through complex modeling of light-matter interaction, some electrons-matter simulation models have been proposed. They could be used to improve accuracy and precision of CD-SEM metrology. However, these model-based approaches also face to fundamental limits mainly due to probe size with respect to the considered structure and noise. This paper analyses these limits assuming the model is perfect and the microscope has no systematic defect. In this simulation study, we have used the model proposed by D. Nyyssonen, assuming to perfectly represent the SEM effects in the image. The feature of interest is limited to isolated trapezoidal lines with various CD, sidewall angles (SWA) and heights. We have carried out the study with several beam energies, tilts and probe sizes. Surprisingly enough, sensitivity analysis shows that with typical noise amplitude, sidewall angle can be determined with a reasonable precision using SEM images. Single tilted beam SEM images can also bring advantage to measure patterns height. Since these precision figures depend on the geometries, we provide useful graphs giving the ultimate precision for various dimensions (CD, height, SWA).","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125788205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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