In this work we address the capability of an alternative overlay evaluation method for the entire BEOL-Process of IHP’s standard 0.25 and 0.13 μm SiGe:C BiCMOS technology. A dual lithography platform NIKON® NSR 210D/207D scanners and NIKON® NSR SF-150 i-Line stepper layer crossing and wafer bow related overlay issues will be discussed. Stack alignment marks, which serves the exposure alignment and overlay determination were introduced. A mismatch for overlay (x/y) |mean| + 3σ values below 8 nm between the KLA® ARCHER 100 overlay and both lithography tools could be demonstrated.
{"title":"Dual platform stepper/scanner-based overlay evaluation method","authors":"P. Kulse, S. Jätzlau, K. Schulz, M. Wietstruck","doi":"10.1117/12.2535629","DOIUrl":"https://doi.org/10.1117/12.2535629","url":null,"abstract":"In this work we address the capability of an alternative overlay evaluation method for the entire BEOL-Process of IHP’s standard 0.25 and 0.13 μm SiGe:C BiCMOS technology. A dual lithography platform NIKON® NSR 210D/207D scanners and NIKON® NSR SF-150 i-Line stepper layer crossing and wafer bow related overlay issues will be discussed. Stack alignment marks, which serves the exposure alignment and overlay determination were introduced. A mismatch for overlay (x/y) |mean| + 3σ values below 8 nm between the KLA® ARCHER 100 overlay and both lithography tools could be demonstrated.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weiming Ren, Xuedong Liu, Xuerang Hu, Xinan Luo, Xiaoyu Ji, Qingpo Xi, K. Chou, M. Ebert, E. Ma
Pattern defects and uninvited particles (residuals) probably appear on Mask and Wafer in any manufacturing process of integrated circuits (ICs) and impact the final yield of IC chips. To ensure a high yield, defect inspection of Mask and Wafer has been broadly adopted for monitoring many processes in high volume manufacturing (HVM) and shortening development cycle-times of critical processes in R&D. In HVM optical inspection tools have played a major role, and in R&D e-beam inspection tools have been a critical role. For the 7nm technology node and beyond, minimum size killer defects are going to be invisible for optical inspection tools, and e-beam inspection tools are too slow to capture smaller killer defects in an acceptable throughput. Accordingly, enhancing e-beam inspection tools in throughput has become an issue demanding prompt attention, and one promising solution is multi-beam inspection (MBI) technology. We are developing a MBI tool, which combines our cutting edge technologies in multi-beam electron optics, sample stage, scanning strategy and computational architecture. In this paper we will introduce MBI technology and development progress of our MBI tool, and will discuss future application of MBI technology.
{"title":"Multi-beam technology for defect inspection of wafer and mask","authors":"Weiming Ren, Xuedong Liu, Xuerang Hu, Xinan Luo, Xiaoyu Ji, Qingpo Xi, K. Chou, M. Ebert, E. Ma","doi":"10.1117/12.2536565","DOIUrl":"https://doi.org/10.1117/12.2536565","url":null,"abstract":"Pattern defects and uninvited particles (residuals) probably appear on Mask and Wafer in any manufacturing process of integrated circuits (ICs) and impact the final yield of IC chips. To ensure a high yield, defect inspection of Mask and Wafer has been broadly adopted for monitoring many processes in high volume manufacturing (HVM) and shortening development cycle-times of critical processes in R&D. In HVM optical inspection tools have played a major role, and in R&D e-beam inspection tools have been a critical role. For the 7nm technology node and beyond, minimum size killer defects are going to be invisible for optical inspection tools, and e-beam inspection tools are too slow to capture smaller killer defects in an acceptable throughput. Accordingly, enhancing e-beam inspection tools in throughput has become an issue demanding prompt attention, and one promising solution is multi-beam inspection (MBI) technology. We are developing a MBI tool, which combines our cutting edge technologies in multi-beam electron optics, sample stage, scanning strategy and computational architecture. In this paper we will introduce MBI technology and development progress of our MBI tool, and will discuss future application of MBI technology.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133149629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leon van Dijk, A. Charley, M. Stokhof, Ronald Otten, S. Van Elshocht, Bert Jongbloed, P. Leray, Richard J. F. van Haren
Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.
{"title":"Detection and mitigation of furnace anneal induced distortions at the wafer edge","authors":"Leon van Dijk, A. Charley, M. Stokhof, Ronald Otten, S. Van Elshocht, Bert Jongbloed, P. Leray, Richard J. F. van Haren","doi":"10.1117/12.2535636","DOIUrl":"https://doi.org/10.1117/12.2535636","url":null,"abstract":"Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132785356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Indykiewicz, B. Paszkiewicz, A. Zawadzka, R. Paszkiewicz
The goal of the conducted work was to fabricate chrome masks on Al2O3 substrates, which could be successfully applied to UV and DUV lithography. The technique is based on electron beam lithography and wet chrome etching in an ceric ammonium nitrate solution. The main advantage of the proposed fabrication method is a major decrease in exposition time due to more effective usage of electron energy. We will demonstrate the use of low electron energy exposition methods with PMMA/MA resist with applied doses of a few μC/cm2. To the best of the author’s knowledge, sapphire substrates have not been previously used in photomasks fabrication. So far, full photomasks sets based on Al2O3 substrates have been manufactured and applied to fabricate the pilot series of acoustic transducers in the AlGaN/GaN heterostructure for piezotronics applications.
{"title":"Chrome mask fabrication on Al2O3 substrate for new generation devices based on AlGaN/GaN heterostructure","authors":"K. Indykiewicz, B. Paszkiewicz, A. Zawadzka, R. Paszkiewicz","doi":"10.1117/12.2535689","DOIUrl":"https://doi.org/10.1117/12.2535689","url":null,"abstract":"The goal of the conducted work was to fabricate chrome masks on Al2O3 substrates, which could be successfully applied to UV and DUV lithography. The technique is based on electron beam lithography and wet chrome etching in an ceric ammonium nitrate solution. The main advantage of the proposed fabrication method is a major decrease in exposition time due to more effective usage of electron energy. We will demonstrate the use of low electron energy exposition methods with PMMA/MA resist with applied doses of a few μC/cm2. To the best of the author’s knowledge, sapphire substrates have not been previously used in photomasks fabrication. So far, full photomasks sets based on Al2O3 substrates have been manufactured and applied to fabricate the pilot series of acoustic transducers in the AlGaN/GaN heterostructure for piezotronics applications.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Mitteramskogler, M. Haslinger, A. Shoshi, S. Schrittwieser, J. Schotter, H. Brueckl, M. Muehlberger
A novel technique to realize large quantities of stacked multifunctional anisotropic nanoparticles with narrow size distribution is presented. Through the combination of Ultraviolet Nano-Imprint Lithography (UV-NIL), physical vapor deposition and subsequent lift-off processes we fabricate and disperse these particles in solution for the use in biomolecular sensing applications. Compared to chemical nanoparticle synthesis our approach holds several advantages. First, one can control the nanoparticle shape by choosing an appropriate nanopattern for the UV-NIL process. Second, we can choose the composition of the nanoparticles as the materials are deposited layer-wise by sputter deposition. Third, we can fabricate nanoparticles with very small geometrical variations. This is in contrast to chemical synthesis methods where the layer thicknesses and particle size distribution are harder to control.
{"title":"Fabrication of nanoparticles for biosensing using UV-NIL and lift-off","authors":"T. Mitteramskogler, M. Haslinger, A. Shoshi, S. Schrittwieser, J. Schotter, H. Brueckl, M. Muehlberger","doi":"10.1117/12.2323700","DOIUrl":"https://doi.org/10.1117/12.2323700","url":null,"abstract":"A novel technique to realize large quantities of stacked multifunctional anisotropic nanoparticles with narrow size distribution is presented. Through the combination of Ultraviolet Nano-Imprint Lithography (UV-NIL), physical vapor deposition and subsequent lift-off processes we fabricate and disperse these particles in solution for the use in biomolecular sensing applications. Compared to chemical nanoparticle synthesis our approach holds several advantages. First, one can control the nanoparticle shape by choosing an appropriate nanopattern for the UV-NIL process. Second, we can choose the composition of the nanoparticles as the materials are deposited layer-wise by sputter deposition. Third, we can fabricate nanoparticles with very small geometrical variations. This is in contrast to chemical synthesis methods where the layer thicknesses and particle size distribution are harder to control.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125044350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lithographical hotspot (LH) detection using deep learning (DL) has received much attention in the recent years. It happens mainly due to the facts the DL approach leads to a better accuracy over the traditional, state-of- the-art programming approaches. The purpose of this study is to compare existing data augmentation (DA) techniques for the integrated circuit (IC) mask data using DL methods. DA is a method which refers to the process of creating new samples similar to the training set, thereby helping to reduce the gap between classes as well as improving the performance of the DL system. Experimental results suggest that the DA methods increase overall DL models performance for the hotspot detection tasks.
{"title":"Research on data augmentation for lithography hotspot detection using deep learning","authors":"V. Borisov, J. Scheible","doi":"10.1117/12.2326563","DOIUrl":"https://doi.org/10.1117/12.2326563","url":null,"abstract":"Lithographical hotspot (LH) detection using deep learning (DL) has received much attention in the recent years. It happens mainly due to the facts the DL approach leads to a better accuracy over the traditional, state-of- the-art programming approaches. The purpose of this study is to compare existing data augmentation (DA) techniques for the integrated circuit (IC) mask data using DL methods. DA is a method which refers to the process of creating new samples similar to the training set, thereby helping to reduce the gap between classes as well as improving the performance of the DL system. Experimental results suggest that the DA methods increase overall DL models performance for the hotspot detection tasks.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123009666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Popescu, A. McClelland, D. Kazazis, G. Dawson, J. Roth, Y. Ekinci, W. Theis, A. Robinson
The multi-trigger resist (MTR) is a new negative tone molecular resist platform for electron beam lithography, as well as extreme ultraviolet and optical lithography. The performance of xMT resist, the precursor to MTR resist, which shows a good combination of sensitivity, low line edge roughness and high-resolution patterning has previously been reported.[1] In order to overcome limitations induced by acid diffusion, a new mechanism - the multi-trigger concept - has been introduced. The results obtained so far as the behaviour of the resist is driven towards the multi-trigger regime by manipulating the resist formulation are presented. A feature size of 13 nm in semi-dense (1:1.5 line/space) patterns, and 22nm diameter pillar patterns are demonstrated in electron beam, and 16 nm half-pitch resolution patterns are demonstrated in (extreme ultraviolet) EUV. An improvement in the LER value is seen in the higher MTR formulations.
{"title":"Multi-trigger resist for electron beam and extreme ultraviolet lithography","authors":"C. Popescu, A. McClelland, D. Kazazis, G. Dawson, J. Roth, Y. Ekinci, W. Theis, A. Robinson","doi":"10.1117/12.2316628","DOIUrl":"https://doi.org/10.1117/12.2316628","url":null,"abstract":"The multi-trigger resist (MTR) is a new negative tone molecular resist platform for electron beam lithography, as well as extreme ultraviolet and optical lithography. The performance of xMT resist, the precursor to MTR resist, which shows a good combination of sensitivity, low line edge roughness and high-resolution patterning has previously been reported.[1] In order to overcome limitations induced by acid diffusion, a new mechanism - the multi-trigger concept - has been introduced. The results obtained so far as the behaviour of the resist is driven towards the multi-trigger regime by manipulating the resist formulation are presented. A feature size of 13 nm in semi-dense (1:1.5 line/space) patterns, and 22nm diameter pillar patterns are demonstrated in electron beam, and 16 nm half-pitch resolution patterns are demonstrated in (extreme ultraviolet) EUV. An improvement in the LER value is seen in the higher MTR formulations.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123334062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jens Seyfert, L. Albinus, J. Arnold, S. Fritsche, Steffen Habel, M. Mitrach, Mario Stephan
A fundamental aspect for the economic success of a semiconductor production is a low level of costs per wafer. A substantial part of these costs per wafer is accounted by personnel costs. For this reason, it is desirable to reach the lowest possible level of personnel costs. Mainly this is achieved by increasing the degree of the factory automation. To increase the degree of factory automation, various approaches are conceivable and in use. We were at the time the first 12”-fab worldwide and we were equipped with an OHT (Overhead Hoist Transfer) system of the first generation to transport to and load wafer pods on process equipment and wafer stockers. That means, that the complete wafer handling took place automatically. Viewed with a certain distance, the fab as a whole showed a high level of automation. However, in the lithography it was necessary to handle reticles manually. Figure 1 shows the distribution between the automated wafer handling and the manual done parts reticle handling and necessary tool assist. The efforts for manual reticle handling and the resulting personnel costs contradicted the requirements of a highly automated manufacturing. An investigation about possible reticle automation scenarios by using AGV (Automated Guided Vehicles) or OHT to improve the lithography automation level resulted in non-acceptable investments in relation to the saved personnel costs. As a result, further activities to automate reticle handling have been avoided. But driven by the end of live situation of the used OHT system, a retrofit of the system in 2017 offered the possibility to install additionally to the lot OHT system a reticle OHT option. In conjunction with the findings of the above investigation, this new situation led to the decision to install this option to save the personnel costs of manual reticle handling. Introductory in this paper, we would like to compare briefly conceivable automation scenarios by using AGV and OHT systems. We describe the advantages and disadvantages of both systems arising from our present situation. We justify why only the use of an OHT makes sense for us. The main part of the paper is dedicated to the way from the ended OHT hardware startup to the running automated reticle handling. First of all, we introduce the machinery used. The majority of the exposure equipment was not intended for OHT loading by tool manufacturer. We explain the modifications needed to allow a reticle loading of the exposure tools by OHT. One key factor in getting the system up and running is the control of the exposure tools by host commands. These sequences are used to enable the tool operation without operator-tool interaction. Based on the reticle load and unload strategy, we explain basics of our used exposure tool control. Another key factor is the system control algorithm. The whole reticle operation is controlled by a rule based dispatching system. The rules used combine robustness and necessary performance emphasizing the ro
{"title":"The (almost) completely automated 12”-lithography","authors":"Jens Seyfert, L. Albinus, J. Arnold, S. Fritsche, Steffen Habel, M. Mitrach, Mario Stephan","doi":"10.1117/12.2325837","DOIUrl":"https://doi.org/10.1117/12.2325837","url":null,"abstract":"A fundamental aspect for the economic success of a semiconductor production is a low level of costs per wafer. A substantial part of these costs per wafer is accounted by personnel costs. For this reason, it is desirable to reach the lowest possible level of personnel costs. Mainly this is achieved by increasing the degree of the factory automation. To increase the degree of factory automation, various approaches are conceivable and in use. We were at the time the first 12”-fab worldwide and we were equipped with an OHT (Overhead Hoist Transfer) system of the first generation to transport to and load wafer pods on process equipment and wafer stockers. That means, that the complete wafer handling took place automatically. Viewed with a certain distance, the fab as a whole showed a high level of automation. However, in the lithography it was necessary to handle reticles manually. Figure 1 shows the distribution between the automated wafer handling and the manual done parts reticle handling and necessary tool assist. The efforts for manual reticle handling and the resulting personnel costs contradicted the requirements of a highly automated manufacturing. An investigation about possible reticle automation scenarios by using AGV (Automated Guided Vehicles) or OHT to improve the lithography automation level resulted in non-acceptable investments in relation to the saved personnel costs. As a result, further activities to automate reticle handling have been avoided. But driven by the end of live situation of the used OHT system, a retrofit of the system in 2017 offered the possibility to install additionally to the lot OHT system a reticle OHT option. In conjunction with the findings of the above investigation, this new situation led to the decision to install this option to save the personnel costs of manual reticle handling. Introductory in this paper, we would like to compare briefly conceivable automation scenarios by using AGV and OHT systems. We describe the advantages and disadvantages of both systems arising from our present situation. We justify why only the use of an OHT makes sense for us. The main part of the paper is dedicated to the way from the ended OHT hardware startup to the running automated reticle handling. First of all, we introduce the machinery used. The majority of the exposure equipment was not intended for OHT loading by tool manufacturer. We explain the modifications needed to allow a reticle loading of the exposure tools by OHT. One key factor in getting the system up and running is the control of the exposure tools by host commands. These sequences are used to enable the tool operation without operator-tool interaction. Based on the reticle load and unload strategy, we explain basics of our used exposure tool control. Another key factor is the system control algorithm. The whole reticle operation is controlled by a rule based dispatching system. The rules used combine robustness and necessary performance emphasizing the ro","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124572238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For advanced technology nodes, the patterning of integrated circuits requires not only a very good control of critical dimensions but also a very accurate control of the alignment between layers. These two factors combine to define the metric of inter-layer edge placement error (EPE) that quantifies the quality of the pattern placement critical for yield. In this work, we consider the inter-layer EPE between a contact layer with respect to a poly layer measured with SEM contours. Inter-layer EPE was measured across wafer for various critical features to assess the importance of dimensional and overlay variability. Area of overlap between contact and poly as well as contact centroid distribution were considered to further characterize the interaction between poly and contact patterns.
{"title":"Measuring inter-layer edge placement error with SEM contours","authors":"F. Weisbuch, Jirka Schatz, M. Ruhm","doi":"10.1117/12.2326529","DOIUrl":"https://doi.org/10.1117/12.2326529","url":null,"abstract":"For advanced technology nodes, the patterning of integrated circuits requires not only a very good control of critical dimensions but also a very accurate control of the alignment between layers. These two factors combine to define the metric of inter-layer edge placement error (EPE) that quantifies the quality of the pattern placement critical for yield. In this work, we consider the inter-layer EPE between a contact layer with respect to a poly layer measured with SEM contours. Inter-layer EPE was measured across wafer for various critical features to assess the importance of dimensional and overlay variability. Area of overlap between contact and poly as well as contact centroid distribution were considered to further characterize the interaction between poly and contact patterns.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Faegheh Hasibi, Leon van Dijk, M. Larrañaga, A. Pastol, A. Lam, Richard J. F. van Haren
Overlay is a one of the most critical design specifications in semiconductor device manufacturing. Any state-of- the-art production facility has overlay metrology in place to monitor overlay performance during manufacturing and to use the measurements for overlay control. Especially since the introduction of multi-patterning, with its tight overlay requirements and increased number of process steps, there has been an increased need for additional metrology. Overlay metrology brings cost-added value to semiconductor device manufacturing and it should be reduced to a minimum to keep costs at acceptable levels, which can be a challenge in the multi-patterning era. Replacing some real overlay measurements with predicted values, referred to as virtual overlay metrology, could be a viable solution to address this challenge. In this work, we develop virtual overlay metrology and aim at predicting the overlay for a series of implant layers. To this end, we apply machine learning algorithms, and neural networks in particular, to build a complex non-linear model directly from data. Our model takes a set of features that are designed based on the physical concepts of overlay and outputs the overlay map of a target layer. The features include overlay of another implant layer of the same wafer, exposure tool fingerprints, scanner logging, and process data. We evaluate our model using production data and we show the prediction performance for the raw overlay, as well as for the correctable and non-correctable overlay errors.
{"title":"Towards fab cycle time reduction by machine learning-based overlay metrology","authors":"Faegheh Hasibi, Leon van Dijk, M. Larrañaga, A. Pastol, A. Lam, Richard J. F. van Haren","doi":"10.1117/12.2500239","DOIUrl":"https://doi.org/10.1117/12.2500239","url":null,"abstract":"Overlay is a one of the most critical design specifications in semiconductor device manufacturing. Any state-of- the-art production facility has overlay metrology in place to monitor overlay performance during manufacturing and to use the measurements for overlay control. Especially since the introduction of multi-patterning, with its tight overlay requirements and increased number of process steps, there has been an increased need for additional metrology. Overlay metrology brings cost-added value to semiconductor device manufacturing and it should be reduced to a minimum to keep costs at acceptable levels, which can be a challenge in the multi-patterning era. Replacing some real overlay measurements with predicted values, referred to as virtual overlay metrology, could be a viable solution to address this challenge. In this work, we develop virtual overlay metrology and aim at predicting the overlay for a series of implant layers. To this end, we apply machine learning algorithms, and neural networks in particular, to build a complex non-linear model directly from data. Our model takes a set of features that are designed based on the physical concepts of overlay and outputs the overlay map of a target layer. The features include overlay of another implant layer of the same wafer, exposure tool fingerprints, scanner logging, and process data. We evaluate our model using production data and we show the prediction performance for the raw overlay, as well as for the correctable and non-correctable overlay errors.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131684291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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