Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804163
W. Arfaoui, X. Federspiel, P. Mora, M. Rafik, D. Roy, A. Bravaix
We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.
{"title":"Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes","authors":"W. Arfaoui, X. Federspiel, P. Mora, M. Rafik, D. Roy, A. Bravaix","doi":"10.1109/IIRW.2013.6804163","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804163","url":null,"abstract":"We present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation modes and BTI. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature. Hence, we point out the necessity of new appropriate reliability modeling specially for recent ultra-short channel technologies.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804177
R. Coppeta, H. Ceric, D. Holec, T. Grasser
The critical thickness is the smallest thickness of a uniformly strained thin layer on a substrate for which it becomes energetically possible for a misfit dislocation to form spontaneously at the interface between the layer and the substrate. The critical thickness can be calculated by different criterions. The most used criterions assume that both the thin layer and the substrate isotropic with the same elastic properties. Recently a new criterion was developed to describe the formation of a misfit dislocation buried at a distance h below the free surface, assuming different elastic constants of the thin film and the substrate with hexagonal symmetry. We compared the results of this criterion for an Al1-xGaxN film on an AlN substrate with the result obtained by the isotropic criterions. After this, we calculated the critical thickness for the Al1-xGaxN on an AlN substrate for different temperatures.
{"title":"Critical thickness for GaN thin film on AlN substrate","authors":"R. Coppeta, H. Ceric, D. Holec, T. Grasser","doi":"10.1109/IIRW.2013.6804177","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804177","url":null,"abstract":"The critical thickness is the smallest thickness of a uniformly strained thin layer on a substrate for which it becomes energetically possible for a misfit dislocation to form spontaneously at the interface between the layer and the substrate. The critical thickness can be calculated by different criterions. The most used criterions assume that both the thin layer and the substrate isotropic with the same elastic properties. Recently a new criterion was developed to describe the formation of a misfit dislocation buried at a distance h below the free surface, assuming different elastic constants of the thin film and the substrate with hexagonal symmetry. We compared the results of this criterion for an Al1-xGaxN film on an AlN substrate with the result obtained by the isotropic criterions. After this, we calculated the critical thickness for the Al1-xGaxN on an AlN substrate for different temperatures.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804189
Zia Abbas, U. Khalid, M. Olivieri
The yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations.
{"title":"Sizing and optimization of low power process variation aware standard cells","authors":"Zia Abbas, U. Khalid, M. Olivieri","doi":"10.1109/IIRW.2013.6804189","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804189","url":null,"abstract":"The yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133226522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804170
T. Diokh, E. Le-Roux, S. Jeannot, P. Candelier, L. Perniola, J. Nodin, V. Jousseaume, T. Cabout, H. Grampei, E. Jalaguier, B. De Salvo
In this paper, the failure acceleration behavior of HfO2 based ReRAM under constant voltage and high temperature stresses is studied. We extract the activation energy from disturb measurements in the High Resistance State (HRS) for different dielectrics. Various Reset conditions are studied and correlated to the failure mechanism. Low activation energy is obtained in thin dielectric oxides. Based on the hypothesis that the activation energy is linked to the number of oxygen vacancies (i.e. residual conductive filament) in the oxide film, we show that an optimal Reset condition (in terms of voltage stop) can reduce the activation energy in thin HfO2. On the other hand, the activation energy is higher in thick dielectrics films and it is also tunable thanks to the voltage stop of previous Reset operation.
{"title":"On the impact of the oxide thickness and reset conditions on activation energy of HfO2 based ReRAM extracted through disturb measurements","authors":"T. Diokh, E. Le-Roux, S. Jeannot, P. Candelier, L. Perniola, J. Nodin, V. Jousseaume, T. Cabout, H. Grampei, E. Jalaguier, B. De Salvo","doi":"10.1109/IIRW.2013.6804170","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804170","url":null,"abstract":"In this paper, the failure acceleration behavior of HfO2 based ReRAM under constant voltage and high temperature stresses is studied. We extract the activation energy from disturb measurements in the High Resistance State (HRS) for different dielectrics. Various Reset conditions are studied and correlated to the failure mechanism. Low activation energy is obtained in thin dielectric oxides. Based on the hypothesis that the activation energy is linked to the number of oxygen vacancies (i.e. residual conductive filament) in the oxide film, we show that an optimal Reset condition (in terms of voltage stop) can reduce the activation energy in thin HfO2. On the other hand, the activation energy is higher in thick dielectrics films and it is also tunable thanks to the voltage stop of previous Reset operation.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127335783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804180
Abhishek A. Sharma, M. Noman, M. Skowronski, J. Bain
Oxide based resistive switching memories are considered to be one of the front-runners for the next generation non-volatile memories. Forming, the critical one time programming process, is not well understood. In this work, we try to understand the dynamics of forming process in two model systems - TaOx and TiOx, and compare the similarities and the universality in its control parameters. After comparing the time, voltage and temperature dependent dynamics, we find that a 1/E (E being electric field) dependence causes the activation energy to reduce by more than an order of magnitude.
{"title":"Comparison of electric field dependent activation energy for electroformation in TaOx and TiOx based RRAMs","authors":"Abhishek A. Sharma, M. Noman, M. Skowronski, J. Bain","doi":"10.1109/IIRW.2013.6804180","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804180","url":null,"abstract":"Oxide based resistive switching memories are considered to be one of the front-runners for the next generation non-volatile memories. Forming, the critical one time programming process, is not well understood. In this work, we try to understand the dynamics of forming process in two model systems - TaOx and TiOx, and compare the similarities and the universality in its control parameters. After comparing the time, voltage and temperature dependent dynamics, we find that a 1/E (E being electric field) dependence causes the activation energy to reduce by more than an order of magnitude.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122532604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804143
T. Klarr, D. Austin, N. Alimardani, J. F. Conley
Bilayer metal/insulator/insulator/metal (MIIM) diodes of HfO2 and Al2O3 using asymmetric metal gates are investigated for their susceptibility to trap charge. Comparing the effects of constant current electrical stressing for varying thicknesses of insulators, the authors have formulated an adaptation of the Fowler-Nordheim derivative method such that an estimate of the charge centroid location can be obtained for bilayer insulators. In this work it has been found the addition of an HfO2 layer into an Al2O3 MIM device leads to increased charge trapping and greater shifts in the I-V characteristic.
{"title":"Electrical stressing of bilayer insulator HfO2/Al2O3 metal-insulator-insulator-metal (MIIM) diodes","authors":"T. Klarr, D. Austin, N. Alimardani, J. F. Conley","doi":"10.1109/IIRW.2013.6804143","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804143","url":null,"abstract":"Bilayer metal/insulator/insulator/metal (MIIM) diodes of HfO2 and Al2O3 using asymmetric metal gates are investigated for their susceptibility to trap charge. Comparing the effects of constant current electrical stressing for varying thicknesses of insulators, the authors have formulated an adaptation of the Fowler-Nordheim derivative method such that an estimate of the charge centroid location can be obtained for bilayer insulators. In this work it has been found the addition of an HfO2 layer into an Al2O3 MIM device leads to increased charge trapping and greater shifts in the I-V characteristic.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116365723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804192
Minhua Lu
Pb-free solders are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based Pb-free solders, due to the differences in microstructures and Sn-grain orientation. Rapid depletion of intermetallic-compounds and Under-Bump-Metallurgy are caused by fast diffusion of Cu and Ni along the c-axis of Sn crystals. When c-axis of Sn-grain is not aligned with the current direction, electromigration damage is dominated by Sn self-diffusion, which takes longer to occur. In general, the EM damage in SnCu solder is driven by the fast interstitial diffusion of Ni and Cu away from solder/UBM interface resulting in early fails; while the damage in SnAg solders is mostly dominated by Sn-self diffusion resulting in longer lifetime. The effective activation energy is 0.95 eV for SnAg solder and 0.54 eV for SnCu solder. The power exponent is 2 for SnAg and 1.2 for SnCu. Blech effect is observed only in the solders with Sn-self diffusion dominated failures, not in fast diffusion dominated failures. Therefore, optimizing and control solder microstructure is important to the solder reliability.
{"title":"Effect of microstructure and alloy doping on electromigration in Pb-free solder interconnect","authors":"Minhua Lu","doi":"10.1109/IIRW.2013.6804192","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804192","url":null,"abstract":"Pb-free solders are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based Pb-free solders, due to the differences in microstructures and Sn-grain orientation. Rapid depletion of intermetallic-compounds and Under-Bump-Metallurgy are caused by fast diffusion of Cu and Ni along the c-axis of Sn crystals. When c-axis of Sn-grain is not aligned with the current direction, electromigration damage is dominated by Sn self-diffusion, which takes longer to occur. In general, the EM damage in SnCu solder is driven by the fast interstitial diffusion of Ni and Cu away from solder/UBM interface resulting in early fails; while the damage in SnAg solders is mostly dominated by Sn-self diffusion resulting in longer lifetime. The effective activation energy is 0.95 eV for SnAg solder and 0.54 eV for SnCu solder. The power exponent is 2 for SnAg and 1.2 for SnCu. Blech effect is observed only in the solders with Sn-self diffusion dominated failures, not in fast diffusion dominated failures. Therefore, optimizing and control solder microstructure is important to the solder reliability.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804187
Xuemei Liu, L. Pan, X. Zhao, Fengying Qiao, Dong Wu, Jun Xu
The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.
{"title":"A novel soft error immunity SRAM cell","authors":"Xuemei Liu, L. Pan, X. Zhao, Fengying Qiao, Dong Wu, Jun Xu","doi":"10.1109/IIRW.2013.6804187","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804187","url":null,"abstract":"The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122956338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804185
H. Ceric, A. Singulani, R. L. de Orio, S. Selberherr
Solder bumps are important interconnect components for three-dimensional (3D) integration. Their mechanical and electrical properties influence the overall reliability of 3D ICs. A particular characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation influences the operation of 3D ICs and, in connection with electromigration, may cause failures. We present a model for describing the growth of intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.
{"title":"Electromigration enhanced growth of intermetallic compound in solder bumps","authors":"H. Ceric, A. Singulani, R. L. de Orio, S. Selberherr","doi":"10.1109/IIRW.2013.6804185","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804185","url":null,"abstract":"Solder bumps are important interconnect components for three-dimensional (3D) integration. Their mechanical and electrical properties influence the overall reliability of 3D ICs. A particular characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation influences the operation of 3D ICs and, in connection with electromigration, may cause failures. We present a model for describing the growth of intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"21 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113964972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804147
P. Shrestha, K. Cheung, J. Campbell, J. Ryan, H. Baumgart
Fast-CV measurements are frequently being used to study transient phenomena associated with advanced devices. In this study, we show that many artifacts plague this measurement and then provide a proper method to legitimize fast-CV measurements as trustworthy. We show a remarkably accurate correspondence between a complete fast CV measurement, from accumulation to inversion, and a conventional CV measurement on the same device. The results distinguish fast-CV as a powerful tool for device characterization and reliability measurements.
{"title":"Fast-capacitance for advanced device characterization","authors":"P. Shrestha, K. Cheung, J. Campbell, J. Ryan, H. Baumgart","doi":"10.1109/IIRW.2013.6804147","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804147","url":null,"abstract":"Fast-CV measurements are frequently being used to study transient phenomena associated with advanced devices. In this study, we show that many artifacts plague this measurement and then provide a proper method to legitimize fast-CV measurements as trustworthy. We show a remarkably accurate correspondence between a complete fast CV measurement, from accumulation to inversion, and a conventional CV measurement on the same device. The results distinguish fast-CV as a powerful tool for device characterization and reliability measurements.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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