Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804147
P. Shrestha, K. Cheung, J. Campbell, J. Ryan, H. Baumgart
Fast-CV measurements are frequently being used to study transient phenomena associated with advanced devices. In this study, we show that many artifacts plague this measurement and then provide a proper method to legitimize fast-CV measurements as trustworthy. We show a remarkably accurate correspondence between a complete fast CV measurement, from accumulation to inversion, and a conventional CV measurement on the same device. The results distinguish fast-CV as a powerful tool for device characterization and reliability measurements.
{"title":"Fast-capacitance for advanced device characterization","authors":"P. Shrestha, K. Cheung, J. Campbell, J. Ryan, H. Baumgart","doi":"10.1109/IIRW.2013.6804147","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804147","url":null,"abstract":"Fast-CV measurements are frequently being used to study transient phenomena associated with advanced devices. In this study, we show that many artifacts plague this measurement and then provide a proper method to legitimize fast-CV measurements as trustworthy. We show a remarkably accurate correspondence between a complete fast CV measurement, from accumulation to inversion, and a conventional CV measurement on the same device. The results distinguish fast-CV as a powerful tool for device characterization and reliability measurements.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804172
Nico Hellwege, N. Heidmann, D. Peters-Drolshagen, S. Paul
Effects like NBTI and HCI are degrading the characteristics of analog circuits. Available countermeasures to maintain system performances often include the use of optimizers or other external tools to size devices appropriately, which give no insight in relations between degradation and circuit parameters for the designer. This paper proposes an extension of the gm/ID sizing method by considering aged transistor parameters for fresh circuit design. A possible usage scenario for this investigation is given by optimizing a simple circuit towards higher reliability. The degradation in amplification of a common source amplifier is reduced by 19 % for a full time operation of 10 years.
{"title":"Using operating point-dependent degradation and gm/ID method for aging-aware design","authors":"Nico Hellwege, N. Heidmann, D. Peters-Drolshagen, S. Paul","doi":"10.1109/IIRW.2013.6804172","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804172","url":null,"abstract":"Effects like NBTI and HCI are degrading the characteristics of analog circuits. Available countermeasures to maintain system performances often include the use of optimizers or other external tools to size devices appropriately, which give no insight in relations between degradation and circuit parameters for the designer. This paper proposes an extension of the gm/ID sizing method by considering aged transistor parameters for fresh circuit design. A possible usage scenario for this investigation is given by optimizing a simple circuit towards higher reliability. The degradation in amplification of a common source amplifier is reduced by 19 % for a full time operation of 10 years.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125165690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804185
H. Ceric, A. Singulani, R. L. de Orio, S. Selberherr
Solder bumps are important interconnect components for three-dimensional (3D) integration. Their mechanical and electrical properties influence the overall reliability of 3D ICs. A particular characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation influences the operation of 3D ICs and, in connection with electromigration, may cause failures. We present a model for describing the growth of intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.
{"title":"Electromigration enhanced growth of intermetallic compound in solder bumps","authors":"H. Ceric, A. Singulani, R. L. de Orio, S. Selberherr","doi":"10.1109/IIRW.2013.6804185","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804185","url":null,"abstract":"Solder bumps are important interconnect components for three-dimensional (3D) integration. Their mechanical and electrical properties influence the overall reliability of 3D ICs. A particular characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation influences the operation of 3D ICs and, in connection with electromigration, may cause failures. We present a model for describing the growth of intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"21 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113964972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804173
Y. Tkachev, A. Kotov
A new simple and fast method for separation of cycling-induced degradation components in split-gate SuperFlash® cell is proposed. The method is based on the effect of tunneling current stabilization during linearly ramped erase voltage.
{"title":"A new method for analysis of cycling-induced degradation components in split-gate flash memory cells","authors":"Y. Tkachev, A. Kotov","doi":"10.1109/IIRW.2013.6804173","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804173","url":null,"abstract":"A new simple and fast method for separation of cycling-induced degradation components in split-gate SuperFlash® cell is proposed. The method is based on the effect of tunneling current stabilization during linearly ramped erase voltage.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124714173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804146
J. Ryan, J. Campbell, J. Zou, K. Cheung, R. Southwick, A. Oates, R. Huang
We examine the seemingly frequency-dependent gate leakage current component of frequency-modulated charge pumping and show it to be a measurement artifact. If untreated, this results in erroneous defect density extractions. We present a constant shape factor methodology to suppress this component such that frequency-modulated charge pumping is well positioned for advanced device defect characterization.
{"title":"Constant shape factor frequency modulated charge pumping (FMCP)","authors":"J. Ryan, J. Campbell, J. Zou, K. Cheung, R. Southwick, A. Oates, R. Huang","doi":"10.1109/IIRW.2013.6804146","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804146","url":null,"abstract":"We examine the seemingly frequency-dependent gate leakage current component of frequency-modulated charge pumping and show it to be a measurement artifact. If untreated, this results in erroneous defect density extractions. We present a constant shape factor methodology to suppress this component such that frequency-modulated charge pumping is well positioned for advanced device defect characterization.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804156
Andreas Martin
In this work digital MOS transistors of three different process nodes are investigated for reliability degradation from plasma induced charging (PID). It is demonstrated that a charging of triple well/dual well configurations lead to significantly increased gate oxide leakage currents of connected MOS transistors which are placed in adjacent well regions. This has not been yet investigated in such detail with test structures which are product relevant over a wide range of well sizes and different areas of large metal antenna. The characterization of well charging requires a new definition of the antenna ratio for the comparison of experimental reliability degradation results between process nodes. Findings can be directly applied to product layout.
{"title":"Circuit relevant well charging from metal antenna and its degradation on digital MOS transistor reliability","authors":"Andreas Martin","doi":"10.1109/IIRW.2013.6804156","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804156","url":null,"abstract":"In this work digital MOS transistors of three different process nodes are investigated for reliability degradation from plasma induced charging (PID). It is demonstrated that a charging of triple well/dual well configurations lead to significantly increased gate oxide leakage currents of connected MOS transistors which are placed in adjacent well regions. This has not been yet investigated in such detail with test structures which are product relevant over a wide range of well sizes and different areas of large metal antenna. The characterization of well charging requires a new definition of the antenna ratio for the comparison of experimental reliability degradation results between process nodes. Findings can be directly applied to product layout.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131089790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804151
G. Roll, M. Egard, Sofia Johannson, L. Ohlsson, L. Wernersson, E. Lind
A complete reliability study of the high-frequency characteristics for nMOSFETs on InGaAs channel with Al2O3/HfO2 gate dielectric is presented. DC gate voltage stress causes an increase in the transconductance frequency dispersion. Stress induced border traps degrade the maximum DC-transconductance, but do not react at high frequencies. The main degradation characteristics of the high-frequency measurements can be modeled by the threshold voltage related transconductance shift. The maximum of the cut-off frequency is shifted with stress to higher or lower gate biases, but not decreased.
{"title":"RF reliability of gate last InGaAs nMOSFETs with high-k dielectric","authors":"G. Roll, M. Egard, Sofia Johannson, L. Ohlsson, L. Wernersson, E. Lind","doi":"10.1109/IIRW.2013.6804151","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804151","url":null,"abstract":"A complete reliability study of the high-frequency characteristics for nMOSFETs on InGaAs channel with Al2O3/HfO2 gate dielectric is presented. DC gate voltage stress causes an increase in the transconductance frequency dispersion. Stress induced border traps degrade the maximum DC-transconductance, but do not react at high frequencies. The main degradation characteristics of the high-frequency measurements can be modeled by the threshold voltage related transconductance shift. The maximum of the cut-off frequency is shifted with stress to higher or lower gate biases, but not decreased.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131482831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804183
K. Kambour, D. Nguyen, C. Kouhestani, R. Devine
The generation of interface states created by depassivating dangling bonds at the interface between the gate dielectric and silicon substrate is important for both the growth of Negative Bias Temperature Instability threshold voltage shift in MOSFETs and the radiation sensitivity of the devices. In this paper we present results comparing the generation of interface states for both processes and their possible annealing at high temperatures.
{"title":"Comparison of NTBI and irradiation induced interface states","authors":"K. Kambour, D. Nguyen, C. Kouhestani, R. Devine","doi":"10.1109/IIRW.2013.6804183","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804183","url":null,"abstract":"The generation of interface states created by depassivating dangling bonds at the interface between the gate dielectric and silicon substrate is important for both the growth of Negative Bias Temperature Instability threshold voltage shift in MOSFETs and the radiation sensitivity of the devices. In this paper we present results comparing the generation of interface states for both processes and their possible annealing at high temperatures.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126270748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804181
D. Nguyen, C. Kouhestani, K. Kambour, R. Devine
This paper reports new high temperature measurements of Negative Bias Temperature Instability induced interface states in both NMOS and PMOS devices. Evidence of annealing of the interface states, previously thought to be “permanent”, is presented for measurements including a methodology which allows the direct measurement of the time dependent growth/recovery of the interface state component.
{"title":"On the nature of “permanent” degradation in NBTI","authors":"D. Nguyen, C. Kouhestani, K. Kambour, R. Devine","doi":"10.1109/IIRW.2013.6804181","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804181","url":null,"abstract":"This paper reports new high temperature measurements of Negative Bias Temperature Instability induced interface states in both NMOS and PMOS devices. Evidence of annealing of the interface states, previously thought to be “permanent”, is presented for measurements including a methodology which allows the direct measurement of the time dependent growth/recovery of the interface state component.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116808943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804159
C. Sun, Lifang Liu, Zhigang Zhang, L. Pan
High-k dielectrics are candidate materials for the charge trapping layer of charge trapping memory devices. The use of this material allows to obtain a larger memory window and better retention performance. We investigate charge trapping memory capacitors with single or stacked high-K structures. Improved memory windows can be achieved by adopting stacked high-k films as charge trapping layers. However, the data retention characteristics of stacked structures are degraded with respect to the ones of single-layer high-k structures.
{"title":"Comparison of reliability of single and stacked high-k structures of charge trapping memories","authors":"C. Sun, Lifang Liu, Zhigang Zhang, L. Pan","doi":"10.1109/IIRW.2013.6804159","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804159","url":null,"abstract":"High-k dielectrics are candidate materials for the charge trapping layer of charge trapping memory devices. The use of this material allows to obtain a larger memory window and better retention performance. We investigate charge trapping memory capacitors with single or stacked high-K structures. Improved memory windows can be achieved by adopting stacked high-k films as charge trapping layers. However, the data retention characteristics of stacked structures are degraded with respect to the ones of single-layer high-k structures.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121975536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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