Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804168
S. Tyaginov, M. Bina, J. Franco, D. Osintsev, Y. Wimmer, B. Kaczer, T. Grasser
We present a novel approach to hot-carrier degradation (HCD) simulation, which for the first time considers and incorporates mechanisms crucial for HCD. First, two main pathways of Si-H bond dissociation, namely bond-breakage triggered by a single hot carrier and induced by multivibrational bond excitation, are combined and considered consistently. Second, we show how drastically electron-electron scattering affects the whole HCD picture. Furthermore, dispersion of the activation energy of bond dissociation substantially changes defect generation rates. Finally, the interaction between the electric field and the dipole moment of the bond leads to interface states created near the source end of the channel. To demonstrate the importance of all these peculiarities we use ultra-scaled n-MOSFETs with a channel gate of 65 nm.
{"title":"(Late) Essential ingredients for modeling of hot-carrier degradation in ultra-scaled MOSFETs","authors":"S. Tyaginov, M. Bina, J. Franco, D. Osintsev, Y. Wimmer, B. Kaczer, T. Grasser","doi":"10.1109/IIRW.2013.6804168","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804168","url":null,"abstract":"We present a novel approach to hot-carrier degradation (HCD) simulation, which for the first time considers and incorporates mechanisms crucial for HCD. First, two main pathways of Si-H bond dissociation, namely bond-breakage triggered by a single hot carrier and induced by multivibrational bond excitation, are combined and considered consistently. Second, we show how drastically electron-electron scattering affects the whole HCD picture. Furthermore, dispersion of the activation energy of bond dissociation substantially changes defect generation rates. Finally, the interaction between the electric field and the dipole moment of the bond leads to interface states created near the source end of the channel. To demonstrate the importance of all these peculiarities we use ultra-scaled n-MOSFETs with a channel gate of 65 nm.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804159
C. Sun, Lifang Liu, Zhigang Zhang, L. Pan
High-k dielectrics are candidate materials for the charge trapping layer of charge trapping memory devices. The use of this material allows to obtain a larger memory window and better retention performance. We investigate charge trapping memory capacitors with single or stacked high-K structures. Improved memory windows can be achieved by adopting stacked high-k films as charge trapping layers. However, the data retention characteristics of stacked structures are degraded with respect to the ones of single-layer high-k structures.
{"title":"Comparison of reliability of single and stacked high-k structures of charge trapping memories","authors":"C. Sun, Lifang Liu, Zhigang Zhang, L. Pan","doi":"10.1109/IIRW.2013.6804159","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804159","url":null,"abstract":"High-k dielectrics are candidate materials for the charge trapping layer of charge trapping memory devices. The use of this material allows to obtain a larger memory window and better retention performance. We investigate charge trapping memory capacitors with single or stacked high-K structures. Improved memory windows can be achieved by adopting stacked high-k films as charge trapping layers. However, the data retention characteristics of stacked structures are degraded with respect to the ones of single-layer high-k structures.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121975536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804162
G. Rott, H. Nielen, H. Reisinger, W. Gustin, S. Tyaginov, Tibor Grassersstrae
We present hot-carrier measurement results on a 130nm dual gate oxide MOS transistor technology node which is used for automotive and analog applications with a nominal voltage of 3.3V. Transistors of several geometries have been stressed at various gate and drain voltage combinations at room and elevated (125°C) temperatures. The results show two main degradation effects with one drift type (DIsub, max) close to the traditional hot-carrier degradation worst-case condition and another (DΨ, max) for Vds = Vgs. Both effects compensate the drift after a specific stress time. The drifts and their compensation are clearly observable by analyzing the change of the substrate current characteristics over stress time. In the literature several mechanisms for hot-carrier degradation have been reported. The first effect is related to the bond dissociation caused by a single high energetic carrier while the second one is due to the multiple vibrational excitation of the bond by several “colder” carriers. The results underline the importance of that approach and provide a benchmark for device degradation simulations due to the good separability of the observed effects. Long term stress data show that even for low Vgs the drift type DIsub, max will be compensated by DΨ, max.
{"title":"Drift compensating effect during hot-carrier degradation of 130nm technology dual gate oxide P-channel transistors","authors":"G. Rott, H. Nielen, H. Reisinger, W. Gustin, S. Tyaginov, Tibor Grassersstrae","doi":"10.1109/IIRW.2013.6804162","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804162","url":null,"abstract":"We present hot-carrier measurement results on a 130nm dual gate oxide MOS transistor technology node which is used for automotive and analog applications with a nominal voltage of 3.3V. Transistors of several geometries have been stressed at various gate and drain voltage combinations at room and elevated (125°C) temperatures. The results show two main degradation effects with one drift type (DIsub, max) close to the traditional hot-carrier degradation worst-case condition and another (DΨ, max) for Vds = Vgs. Both effects compensate the drift after a specific stress time. The drifts and their compensation are clearly observable by analyzing the change of the substrate current characteristics over stress time. In the literature several mechanisms for hot-carrier degradation have been reported. The first effect is related to the bond dissociation caused by a single high energetic carrier while the second one is due to the multiple vibrational excitation of the bond by several “colder” carriers. The results underline the importance of that approach and provide a benchmark for device degradation simulations due to the good separability of the observed effects. Long term stress data show that even for low Vgs the drift type DIsub, max will be compensated by DΨ, max.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804164
G. Wirth, J. Franco, B. Kaczer
Usually AC Bias Temperature Instability is modeled as consisting of a recoverable and a permanent component, assuming these components originate from different physical mechanisms. In this work we introduce a model based on charge trapping and detrapping that can properly account for both components. Under switching bias (AC stress), fast traps are able to follow the bias point change, while slow traps act according to an equivalent time constant, not being able to follow the bias point change. We present an extension to our previous model to properly account for these effects, and we provide a simple compact model to help circuit designers to cope with both components of BTI due to charge trapping. Model is validated by comparison to experimental data and Monte Carlo simulations.
{"title":"A unified model for AC bias temperature instability","authors":"G. Wirth, J. Franco, B. Kaczer","doi":"10.1109/IIRW.2013.6804164","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804164","url":null,"abstract":"Usually AC Bias Temperature Instability is modeled as consisting of a recoverable and a permanent component, assuming these components originate from different physical mechanisms. In this work we introduce a model based on charge trapping and detrapping that can properly account for both components. Under switching bias (AC stress), fast traps are able to follow the bias point change, while slow traps act according to an equivalent time constant, not being able to follow the bias point change. We present an extension to our previous model to properly account for these effects, and we provide a simple compact model to help circuit designers to cope with both components of BTI due to charge trapping. Model is validated by comparison to experimental data and Monte Carlo simulations.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129006483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804182
J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum
We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.
{"title":"High voltage PMOS FET NBTI results and mechanism","authors":"J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum","doi":"10.1109/IIRW.2013.6804182","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804182","url":null,"abstract":"We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131783013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804178
J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein
Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.
{"title":"Overlap design for higher tungsten via robustness in AlCu metallizations","authors":"J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein","doi":"10.1109/IIRW.2013.6804178","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804178","url":null,"abstract":"Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114225526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804142
A. Bezza, M. Rafik, D. Roy, X. Federspiel, P. Mora, G. Ghibaudo
This paper deals with the oxide breakdown (BD) under positive gate voltage in nMOS Devices. First, bulk current is shown to be more sensitive than gate current for breakdown event detection. Then, since test interruption is shown to induce possible error in TBD evaluation, a methodology with an on the fly detection of breakdown is proposed for both DC and AC stresses. Finally, a discussion on the impact of charge trapping/detrapping is opened.
{"title":"New insight on the frequency dependence of TDDB in high-k/metal gate stacks","authors":"A. Bezza, M. Rafik, D. Roy, X. Federspiel, P. Mora, G. Ghibaudo","doi":"10.1109/IIRW.2013.6804142","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804142","url":null,"abstract":"This paper deals with the oxide breakdown (BD) under positive gate voltage in nMOS Devices. First, bulk current is shown to be more sensitive than gate current for breakdown event detection. Then, since test interruption is shown to induce possible error in TBD evaluation, a methodology with an on the fly detection of breakdown is proposed for both DC and AC stresses. Finally, a discussion on the impact of charge trapping/detrapping is opened.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128051102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804174
M. Masuda, D. Derickson, T. Weatherford, M. Porter
Change in the drain and gate current low frequency noise (LFN) spectra of GaN-on-Si high electron mobility transistors (HEMTs) is measured before and after the application of electric field stressing on the gate. Extracted Hooge parameters are found to be consistent with previous research. RTS noise spectra are found to appear superimposed upon the 1/f spectrum after device stress. Time constants of the RTS spectra are characterized over a range of temperatures and voltages. It is found that RTS noise time constants change with In(τrts) ∝ 1/kT allowing trap activation energies to be calculated. Electron trapping mechanisms responsible for the modification of the RTS spectra are discussed in connection with degradation processes induced by field dependent stressing.
{"title":"Effects of gate stress evaluated using low frequency noise measurements in GaN on Si HEMTs","authors":"M. Masuda, D. Derickson, T. Weatherford, M. Porter","doi":"10.1109/IIRW.2013.6804174","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804174","url":null,"abstract":"Change in the drain and gate current low frequency noise (LFN) spectra of GaN-on-Si high electron mobility transistors (HEMTs) is measured before and after the application of electric field stressing on the gate. Extracted Hooge parameters are found to be consistent with previous research. RTS noise spectra are found to appear superimposed upon the 1/f spectrum after device stress. Time constants of the RTS spectra are characterized over a range of temperatures and voltages. It is found that RTS noise time constants change with In(τrts) ∝ 1/kT allowing trap activation energies to be calculated. Electron trapping mechanisms responsible for the modification of the RTS spectra are discussed in connection with degradation processes induced by field dependent stressing.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121474566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/IIRW.2013.6804184
J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein
The advantage of an increased lifetime of slotted metal tracks for the use in integrated circuits has already been shown. A benefit for slotted metal track geometries especially for thick metal tracks under DC and DC pulsed stress test conditions could be confirmed by lifetime measurements. To achieve a higher current capability these metal tracks, also known as “power metals”, were used in upper metallization layers. This new design concept shows a better robustness towards electromigration in comparison to conventional wide unslotted metal tracks. A new concept deals with the use of slotted geometries in lower metallization layers. Simulations show a decrease of von Mises stress in comparison to unslotted metal tracks. This behaviour can reduce the current shift of active and passive devices due to the imposed stress of the lower metallization layers.
{"title":"Deformation of octahedron slotted metal tracks","authors":"J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein","doi":"10.1109/IIRW.2013.6804184","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804184","url":null,"abstract":"The advantage of an increased lifetime of slotted metal tracks for the use in integrated circuits has already been shown. A benefit for slotted metal track geometries especially for thick metal tracks under DC and DC pulsed stress test conditions could be confirmed by lifetime measurements. To achieve a higher current capability these metal tracks, also known as “power metals”, were used in upper metallization layers. This new design concept shows a better robustness towards electromigration in comparison to conventional wide unslotted metal tracks. A new concept deals with the use of slotted geometries in lower metallization layers. Simulations show a decrease of von Mises stress in comparison to unslotted metal tracks. This behaviour can reduce the current shift of active and passive devices due to the imposed stress of the lower metallization layers.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122267412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2013.6804167
B. Kaczer, C. Chen, J. Watt, K. Chanda, P. Weckx, M. T. Luque, G. Groeseneken, T. Grasser
The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From individual trapping events in deeply-scaled NMOSFETs we then project PBTI distributions at 10 years. Finally, we show that at increased supply voltage the pass gate speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement.
{"title":"(Late) Reliability and performance considerations for NMOSFET pass gates in FPGA applications","authors":"B. Kaczer, C. Chen, J. Watt, K. Chanda, P. Weckx, M. T. Luque, G. Groeseneken, T. Grasser","doi":"10.1109/IIRW.2013.6804167","DOIUrl":"https://doi.org/10.1109/IIRW.2013.6804167","url":null,"abstract":"The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From individual trapping events in deeply-scaled NMOSFETs we then project PBTI distributions at 10 years. Finally, we show that at increased supply voltage the pass gate speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement.","PeriodicalId":287904,"journal":{"name":"2013 IEEE International Integrated Reliability Workshop Final Report","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125074240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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