Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722636
P. Watson, M. Weatherspoon, L. Dunleavy, G. Creech
Artificial neural networks (ANNs) are presented for the accurate and efficient small-signal modeling of active devices. Models are developed using measured data and are valid over ranges of parameters such as frequency, bias, and ambient temperature. Once generated, these ANN models are inserted into commercial microwave circuit simulators where they can be used for computer-aided design (CAD) and optimization of microwave/MM-wave circuits. Also, the developed ANN models can give physical insight into device behavior and scaling properties when used in conjunction with an equivalent circuit approach. An advantage of the ANN modeling approach is that it provides substantial data storage reduction over previously used modeling techniques without loss of accuracy. With increased model accuracy, the potential of first-pass design success may be realized, resulting in cost savings and decreased time-to-market for new products.
{"title":"Accurate and efficient small-signal modeling of active devices using artificial neural networks","authors":"P. Watson, M. Weatherspoon, L. Dunleavy, G. Creech","doi":"10.1109/GAAS.1998.722636","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722636","url":null,"abstract":"Artificial neural networks (ANNs) are presented for the accurate and efficient small-signal modeling of active devices. Models are developed using measured data and are valid over ranges of parameters such as frequency, bias, and ambient temperature. Once generated, these ANN models are inserted into commercial microwave circuit simulators where they can be used for computer-aided design (CAD) and optimization of microwave/MM-wave circuits. Also, the developed ANN models can give physical insight into device behavior and scaling properties when used in conjunction with an equivalent circuit approach. An advantage of the ANN modeling approach is that it provides substantial data storage reduction over previously used modeling techniques without loss of accuracy. With increased model accuracy, the potential of first-pass design success may be realized, resulting in cost savings and decreased time-to-market for new products.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115665380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722632
S. Goto, K. Fujii, H. Morishige, S. Suzuki, S. Sakamoto, N. Yoshida, N. Tanino, K. Sato
A 100 W low distortion AlGaAs-GaAs hetero-structure FET, which is the smallest package size ever reported, has been developed for TDMA and CDMA cellular base stations. The FET exhibited 100 W (50 dBm) saturation output power, and 11.5 dB power gain at 1 dB gain compression at 2.1 GHz. The third order inter-modulation distortion (IMD3) and the power added efficiency (PAE) under two-tone test condition (/spl Delta/f=1 MHz) were -35 dBc and 24%, respectively at 42 dBm output power, of which the level was 8 dB back-off from saturation power. To reduce the cost and the space, the size of the chip and the package were miniaturized to 1.41/spl times/2.6 mm/sup 2/ and 17.4/spl times/24.0 mm/sup 2/, respectively by lengthening the gate finger.
{"title":"A 100 W S-band AlGaAs/GaAs hetero-structure FET for base stations of wireless personal communications","authors":"S. Goto, K. Fujii, H. Morishige, S. Suzuki, S. Sakamoto, N. Yoshida, N. Tanino, K. Sato","doi":"10.1109/GAAS.1998.722632","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722632","url":null,"abstract":"A 100 W low distortion AlGaAs-GaAs hetero-structure FET, which is the smallest package size ever reported, has been developed for TDMA and CDMA cellular base stations. The FET exhibited 100 W (50 dBm) saturation output power, and 11.5 dB power gain at 1 dB gain compression at 2.1 GHz. The third order inter-modulation distortion (IMD3) and the power added efficiency (PAE) under two-tone test condition (/spl Delta/f=1 MHz) were -35 dBc and 24%, respectively at 42 dBm output power, of which the level was 8 dB back-off from saturation power. To reduce the cost and the space, the size of the chip and the package were miniaturized to 1.41/spl times/2.6 mm/sup 2/ and 17.4/spl times/24.0 mm/sup 2/, respectively by lengthening the gate finger.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126095659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722673
D. C. Larson
This paper will explain the theory behind direct digital synthesis (DDS) and examine the architecture and implementation details that put the theory to practice. Key performance attributes will be discussed, with examples of what has been achieved to date. The advantages of the DDS approach over the traditional analog PLL are summarized. New application areas are discussed and the high volume opportunities they provide for GaAs-based DDS products.
{"title":"High speed direct digital synthesis techniques and applications","authors":"D. C. Larson","doi":"10.1109/GAAS.1998.722673","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722673","url":null,"abstract":"This paper will explain the theory behind direct digital synthesis (DDS) and examine the architecture and implementation details that put the theory to practice. Key performance attributes will be discussed, with examples of what has been achieved to date. The advantages of the DDS approach over the traditional analog PLL are summarized. New application areas are discussed and the high volume opportunities they provide for GaAs-based DDS products.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126587431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722668
A. Hanson, D. Danzilio, K. Bacher, L. Leung
A selective recess process for GaAs-based FETs that utilizes etch-stop layers comprised of In/sub 0.5/Ga/sub 0.5/P is demonstrated. The material was grown by molecular beam epitaxy (MBE). This approach is shown to provide a suitable degree of selectivity over GaAs (150:1) for conventional recess chemistries. Additionally, insertion of a 20 /spl Aring/ stop-layer does not adversely effect the electrical performance of devices as previously reported approaches based on AlAs stop-layers have. Values of maximum open channel current (I/sub MAX/) transconductance (g/sub m/), pinchoff voltage (V/sub p/) and access resistance for devices containing In/sub 0.5/Ga/sub 0.5/P stop-layers compare well with nominal process values.
{"title":"A selective gate recess process utilizing MBE-grown In/sub 0.5/Ga/sub 0.5/P etch-stop layers for GaAs-based FET technologies","authors":"A. Hanson, D. Danzilio, K. Bacher, L. Leung","doi":"10.1109/GAAS.1998.722668","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722668","url":null,"abstract":"A selective recess process for GaAs-based FETs that utilizes etch-stop layers comprised of In/sub 0.5/Ga/sub 0.5/P is demonstrated. The material was grown by molecular beam epitaxy (MBE). This approach is shown to provide a suitable degree of selectivity over GaAs (150:1) for conventional recess chemistries. Additionally, insertion of a 20 /spl Aring/ stop-layer does not adversely effect the electrical performance of devices as previously reported approaches based on AlAs stop-layers have. Values of maximum open channel current (I/sub MAX/) transconductance (g/sub m/), pinchoff voltage (V/sub p/) and access resistance for devices containing In/sub 0.5/Ga/sub 0.5/P stop-layers compare well with nominal process values.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722644
Y. Amamiya, T. Niwa, N. Nagano, M. Mamada, Y. Suzuki, H. Shimawaki
This paper reports low power dissipation 40-GHz frequency dividers fabricated using high-performance AlGaAs/InGaAs HBTs. The high-speed performance of small-emitter-area HBTs was markedly improved by analyzing the device delay time and reducing the emitter resistance R/sub E/. An f/sub T/ of above 110 GHz and an f/sub max/ of 250 GHz were achieved with a small emitter area of 2.8 /spl mu/m/sup 2/. A frequency divider fabricated using these high-speed small-emitter-area HBTs operated at 40 GHz with an output voltage of 0.6 V/sub P-P/ and a low power dissipation of 0.9 W. The power dissipation is reduced by 43% compared with that for a frequency divider using conventional size HBTs.
{"title":"40-GHz frequency dividers with reduced power dissipation fabricated using high-speed small-emitter-area AlGaAs/InGaAs HBTs","authors":"Y. Amamiya, T. Niwa, N. Nagano, M. Mamada, Y. Suzuki, H. Shimawaki","doi":"10.1109/GAAS.1998.722644","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722644","url":null,"abstract":"This paper reports low power dissipation 40-GHz frequency dividers fabricated using high-performance AlGaAs/InGaAs HBTs. The high-speed performance of small-emitter-area HBTs was markedly improved by analyzing the device delay time and reducing the emitter resistance R/sub E/. An f/sub T/ of above 110 GHz and an f/sub max/ of 250 GHz were achieved with a small emitter area of 2.8 /spl mu/m/sup 2/. A frequency divider fabricated using these high-speed small-emitter-area HBTs operated at 40 GHz with an output voltage of 0.6 V/sub P-P/ and a low power dissipation of 0.9 W. The power dissipation is reduced by 43% compared with that for a frequency divider using conventional size HBTs.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115931028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722675
J. Kucera, U. Lott
A two stage monolithic on chip matched low noise amplifier (LNA) for the frequency range of 5 to 6 GHz has been designed. A 50 /spl Omega/ noise figure of 1.8 dB and an associated gain of 16.5 dB were measured at a DC power dissipation of only 6 mW from a 1 V supply, including the bias circuitry. At 5.5 GHz the input return loss and reverse isolation are better than -10 dB and -35 dB, respectively.
{"title":"A 1.8 dB noise figure low DC power MMIC LNA for C-band","authors":"J. Kucera, U. Lott","doi":"10.1109/GAAS.1998.722675","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722675","url":null,"abstract":"A two stage monolithic on chip matched low noise amplifier (LNA) for the frequency range of 5 to 6 GHz has been designed. A 50 /spl Omega/ noise figure of 1.8 dB and an associated gain of 16.5 dB were measured at a DC power dissipation of only 6 mW from a 1 V supply, including the bias circuitry. At 5.5 GHz the input return loss and reverse isolation are better than -10 dB and -35 dB, respectively.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"28 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120859977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722672
K. Esbraghian
This paper presents new design concepts in both architecture and design methodology to demonstrate a novel Intelligent Pixel Array (IPA) architecture to realise a real-time implementation of forward and inverse wavelet transform (WT) for image capture, in-situ processing and display. The approach achieves a unique design capable of both image capture and decomposition, as well as reconstruction and display on a single IPA. High speed and low power characteristics of GaAs latch coupled FET logic (LCFL) together with the display capability of ferroelectric liquid crystal (FLC) overlayed on a common GaAs substrate provide this new possibility.
{"title":"Intelligent pixel opto-VLSI architecture for mobile multimedia communicator","authors":"K. Esbraghian","doi":"10.1109/GAAS.1998.722672","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722672","url":null,"abstract":"This paper presents new design concepts in both architecture and design methodology to demonstrate a novel Intelligent Pixel Array (IPA) architecture to realise a real-time implementation of forward and inverse wavelet transform (WT) for image capture, in-situ processing and display. The approach achieves a unique design capable of both image capture and decomposition, as well as reconstruction and display on a single IPA. High speed and low power characteristics of GaAs latch coupled FET logic (LCFL) together with the display capability of ferroelectric liquid crystal (FLC) overlayed on a common GaAs substrate provide this new possibility.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116938525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722609
L. E. Pellon
This paper discusses progress in the development of high dynamic range direct conversion digital receivers being developed for DARPA (under the Advanced Digital Receiver Technology (ADRT) program), employing bandpass multibit /spl Sigma//spl Delta/ modulation with a focus on achieving 16 ENOB (98 dB SINAD and 120 dB SFDR) over 100 MHz bandwidth. An electronically tunable loop filter based on Recursive Transversal Filter (RTF) techniques provides bandpass noise shaping with multiple noise shaping center frequencies between 10 MHz and 900 MHz and with multiple bandwidths. A low in-band effective ADC noise figure of 2 dB enables direct conversion without an LNA external to the ADC. In this paper, the architecture for this DARPA receiver, employing 3.2 GSPS HBT AlGaAs-GaAs mixed signal elements, RTF low jitter clock, and 800 MSPSa GaAs DCFL digital processor, is discussed.
本文讨论了为DARPA(高级数字接收机技术(ADRT)计划)开发的高动态范围直接转换数字接收机的发展进展，采用带通多位/spl Sigma//spl Delta/调制，重点是在100 MHz带宽上实现16 ENOB (98 dB SINAD和120 dB SFDR)。一种基于递归横向滤波器(RTF)技术的电子可调谐环路滤波器提供了在10 MHz和900 MHz之间具有多个噪声整形中心频率和多个带宽的带通噪声整形。2 dB的低带内有效ADC噪声系数可实现直接转换，而无需ADC外部的LNA。本文讨论了采用3.2 GSPS HBT AlGaAs-GaAs混合信号元件、RTF低抖动时钟和800 MSPSa GaAs DCFL数字处理器的DARPA接收机的结构。
{"title":"RF-to-digital receivers employing bandpass multibit /spl Sigma//spl Delta/ ADC architectures","authors":"L. E. Pellon","doi":"10.1109/GAAS.1998.722609","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722609","url":null,"abstract":"This paper discusses progress in the development of high dynamic range direct conversion digital receivers being developed for DARPA (under the Advanced Digital Receiver Technology (ADRT) program), employing bandpass multibit /spl Sigma//spl Delta/ modulation with a focus on achieving 16 ENOB (98 dB SINAD and 120 dB SFDR) over 100 MHz bandwidth. An electronically tunable loop filter based on Recursive Transversal Filter (RTF) techniques provides bandpass noise shaping with multiple noise shaping center frequencies between 10 MHz and 900 MHz and with multiple bandwidths. A low in-band effective ADC noise figure of 2 dB enables direct conversion without an LNA external to the ADC. In this paper, the architecture for this DARPA receiver, employing 3.2 GSPS HBT AlGaAs-GaAs mixed signal elements, RTF low jitter clock, and 800 MSPSa GaAs DCFL digital processor, is discussed.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122133743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722664
J. Mondal, K. Wong, D. Richardson, K. Vu, K. Peterson, G. Dietz, R. Haubenstricker, N. Calanca, L. Gluck, S. Moghe
A MMIC chip set has been developed for use in a forward-looking Collision Avoidance Radar (CAR) at 77 GHz with diplex radar configuration. The chip set is designed with available MMIC foundry processes using a mix of 0.18 and 0.10 /spl mu/m T-gate PHEMT technology. The diplex radar has certain advantages over FMCW and FSK methods commonly adopted in CAR applications. For example, since this method allows for less stringent phase noise requirements on the oscillator, a common MMIC process can be used for all of the MMIC designs. The complete MMIC module has been evaluated for receive and transmit characteristics at 77 GHz and is presently awaiting road testing.
{"title":"77 GHz MMIC T/R module for diplex radar application in collision avoidance radar (CAR)","authors":"J. Mondal, K. Wong, D. Richardson, K. Vu, K. Peterson, G. Dietz, R. Haubenstricker, N. Calanca, L. Gluck, S. Moghe","doi":"10.1109/GAAS.1998.722664","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722664","url":null,"abstract":"A MMIC chip set has been developed for use in a forward-looking Collision Avoidance Radar (CAR) at 77 GHz with diplex radar configuration. The chip set is designed with available MMIC foundry processes using a mix of 0.18 and 0.10 /spl mu/m T-gate PHEMT technology. The diplex radar has certain advantages over FMCW and FSK methods commonly adopted in CAR applications. For example, since this method allows for less stringent phase noise requirements on the oscillator, a common MMIC process can be used for all of the MMIC designs. The complete MMIC module has been evaluated for receive and transmit characteristics at 77 GHz and is presently awaiting road testing.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117108365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722610
P. Asbeck, P.F. Chen, L. Larson
A key issue limiting power efficiency in wireless communication power amplifiers is the variation in signal level that must be accommodated. This paper discusses the importance of and techniques for varying the amplifier DC current and power supply voltage as a function of signal level. A high speed DC-DC converter operating from a 3.3 V source, implemented with GaAs HBTs, is described. The efficiency of a 2 GHz power amplifier using the DC-DC converter is shown to increase by 40%, averaged over signal power variations characteristic of IS-95 CDMA systems.
{"title":"Efficiency and linearity improvement in power amplifiers for wireless communications","authors":"P. Asbeck, P.F. Chen, L. Larson","doi":"10.1109/GAAS.1998.722610","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722610","url":null,"abstract":"A key issue limiting power efficiency in wireless communication power amplifiers is the variation in signal level that must be accommodated. This paper discusses the importance of and techniques for varying the amplifier DC current and power supply voltage as a function of signal level. A high speed DC-DC converter operating from a 3.3 V source, implemented with GaAs HBTs, is described. The efficiency of a 2 GHz power amplifier using the DC-DC converter is shown to increase by 40%, averaged over signal power variations characteristic of IS-95 CDMA systems.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116994982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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