Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722680
M. Masuda, N. Ohbata, H. Ishiuchi, K. Onda, R. Yamamoto
A high power handling of 4 W and low control voltage of +3/0 V GaAs Switch IC, available for the hand-held phone unit for GSM dual and triple mode applications, has been successfully developed. As a basic switch element, heterojunction FET technology has been applied. The optimized stacked-structure with a dual-gate-FET and a triple-gate-FET has demonstrated high linearity of Pin-Pout with a P-1 dB (Pin) of more than 38 dBm, an insertion loss of less than 0.6 dB and an isolation of more than 22 dB in a wide frequency range of 0.5 GHz to 2.0 GHz.
{"title":"High power heterojunction GaAs switch IC with P-1 dB of more than 38 dBm for GSM application","authors":"M. Masuda, N. Ohbata, H. Ishiuchi, K. Onda, R. Yamamoto","doi":"10.1109/GAAS.1998.722680","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722680","url":null,"abstract":"A high power handling of 4 W and low control voltage of +3/0 V GaAs Switch IC, available for the hand-held phone unit for GSM dual and triple mode applications, has been successfully developed. As a basic switch element, heterojunction FET technology has been applied. The optimized stacked-structure with a dual-gate-FET and a triple-gate-FET has demonstrated high linearity of Pin-Pout with a P-1 dB (Pin) of more than 38 dBm, an insertion loss of less than 0.6 dB and an isolation of more than 22 dB in a wide frequency range of 0.5 GHz to 2.0 GHz.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115608400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722670
N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, M. Takikawa
We developed a new type of enhancement-mode (E-mode) heterostructure field effect transistors (FETs) which provide single-voltage operation of power amplifiers in portable phone handsets. Gate leakage current paths were optimized, and a high gate-turn-on voltage and a high drain current density were obtained at the same time. This allows a 50% increase of the drain current by shortening the gate-to-source length without increasing the gate leakage current. We applied this technique to completely E-mode FETs (Vth>0.3 V). A power added efficiency as high as 70.6% has been achieved for an output power of 33 dBm under a Vds of 3.5 V at 850 MHz.
{"title":"Current path optimized structure for high drain current density and high gate-turn-on voltage enhancement mode heterostructure field effect transistors","authors":"N. Hara, Y. Nakasha, M. Nagahara, K. Joshin, Y. Watanabe, M. Takikawa","doi":"10.1109/GAAS.1998.722670","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722670","url":null,"abstract":"We developed a new type of enhancement-mode (E-mode) heterostructure field effect transistors (FETs) which provide single-voltage operation of power amplifiers in portable phone handsets. Gate leakage current paths were optimized, and a high gate-turn-on voltage and a high drain current density were obtained at the same time. This allows a 50% increase of the drain current by shortening the gate-to-source length without increasing the gate leakage current. We applied this technique to completely E-mode FETs (Vth>0.3 V). A power added efficiency as high as 70.6% has been achieved for an output power of 33 dBm under a Vds of 3.5 V at 850 MHz.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124796996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722690
H. Furukawa, T. Fukui, T. Tanaka, A. Noma, D. Ueda
A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process features deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. The Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate of over 4 /spl mu/m/min with a completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than the conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.
{"title":"A novel fabrication process of surface via-holes for GaAs power FETs","authors":"H. Furukawa, T. Fukui, T. Tanaka, A. Noma, D. Ueda","doi":"10.1109/GAAS.1998.722690","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722690","url":null,"abstract":"A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process features deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. The Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate of over 4 /spl mu/m/min with a completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than the conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722611
K. Choquette, A. Allerman, H. Hou, K. Geib, B. E. Hammous
The unique attributes of vertical cavity surface emitting laser (VCSEL) diodes have generated research and commercial interest worldwide. The near term product applications of implanted VCSELs presently center around optical data transmission. VCSELs are considered to be light-emitting diode replacements with respect to packaging and optical coupling, but will also enable very high modulation rate and high efficiency. The use of buried oxide layers for electrical and optical confinement has produced remarkable performance advances of interest for emerging applications. Future applications will leverage high efficiency VCSELs, 2-dimensional VCSEL arrays, and integration with microelectronics.
{"title":"Applications and performance of VCSELs","authors":"K. Choquette, A. Allerman, H. Hou, K. Geib, B. E. Hammous","doi":"10.1109/GAAS.1998.722611","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722611","url":null,"abstract":"The unique attributes of vertical cavity surface emitting laser (VCSEL) diodes have generated research and commercial interest worldwide. The near term product applications of implanted VCSELs presently center around optical data transmission. VCSELs are considered to be light-emitting diode replacements with respect to packaging and optical coupling, but will also enable very high modulation rate and high efficiency. The use of buried oxide layers for electrical and optical confinement has produced remarkable performance advances of interest for emerging applications. Future applications will leverage high efficiency VCSELs, 2-dimensional VCSEL arrays, and integration with microelectronics.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722624
M. Lang, Z. Wang, A. Thiede, H. Lienhart, T. Jakobus, W. Bronner, J. Hornung, A. Hulsmann
Using our 0.2 /spl mu/m AlGaAs-GaAs-AlGaAs quantum well HEMT technology, we have designed, manufactured and characterized a single chip comprising a clock recovery, a data decision and a 2:4 demultiplexer circuit. The chip is able to receive a data stream of 40 Gbit/s and converts it into a four bit parallel data signal. The results presented here have been measured on wafer.
{"title":"A complete GaAs HEMT single chip data receiver for 40 Gbit/s data rates","authors":"M. Lang, Z. Wang, A. Thiede, H. Lienhart, T. Jakobus, W. Bronner, J. Hornung, A. Hulsmann","doi":"10.1109/GAAS.1998.722624","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722624","url":null,"abstract":"Using our 0.2 /spl mu/m AlGaAs-GaAs-AlGaAs quantum well HEMT technology, we have designed, manufactured and characterized a single chip comprising a clock recovery, a data decision and a 2:4 demultiplexer circuit. The chip is able to receive a data stream of 40 Gbit/s and converts it into a four bit parallel data signal. The results presented here have been measured on wafer.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121390055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722631
K. Choumei, K. Yamamoto, N. Kasai, T. Moriwaki, Y. Yoshii, T. Fujii, J. Otsuji, Y. Miyazaki, N. Tanino, K. Sato
A high efficiency and very low voltage operation MMIC using planar self-aligned gate (SAG) FET has been developed for the 1.9 GHz Japanese Personal Handy Phone System (PHS). The MMIC integrates a power amplifier (PA), a low noise amplifier (LNA), a T/R switch (SW) and a negative voltage generator (NVG). The MMIC exhibited high power added efficiency of 39% at the output power (Pout) of 21.0 dBm, which is the highest efficiency in the 2.0 V single supply voltage operation RF front-end MMIC ever reported.
{"title":"A high efficiency, 2 V single-supply voltage operation RF front-end MMIC for 1.9 GHz Personal Handy Phone Systems","authors":"K. Choumei, K. Yamamoto, N. Kasai, T. Moriwaki, Y. Yoshii, T. Fujii, J. Otsuji, Y. Miyazaki, N. Tanino, K. Sato","doi":"10.1109/GAAS.1998.722631","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722631","url":null,"abstract":"A high efficiency and very low voltage operation MMIC using planar self-aligned gate (SAG) FET has been developed for the 1.9 GHz Japanese Personal Handy Phone System (PHS). The MMIC integrates a power amplifier (PA), a low noise amplifier (LNA), a T/R switch (SW) and a negative voltage generator (NVG). The MMIC exhibited high power added efficiency of 39% at the output power (Pout) of 21.0 dBm, which is the highest efficiency in the 2.0 V single supply voltage operation RF front-end MMIC ever reported.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131393130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722665
Jian-Qiang Lu, M. Hurt, W. Peatman, M. Shur
We describe a new class of field effect transistors (FETs) based on a heterodimensional contact between a three-dimensional gate (metal or semiconductor) and a two-dimensional electron gas. The heterodimensional FET family (2D MESFET, 2DI MESFET, and 2D JFET) has shown significant promise for future high speed, ultra low power applications. We review the recent developments, and report on a new fully ion implanted quasi-heterodimensional FET, the coax-2D JFET.
{"title":"Heterodimensional field effect transistors for ultra low power applications","authors":"Jian-Qiang Lu, M. Hurt, W. Peatman, M. Shur","doi":"10.1109/GAAS.1998.722665","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722665","url":null,"abstract":"We describe a new class of field effect transistors (FETs) based on a heterodimensional contact between a three-dimensional gate (metal or semiconductor) and a two-dimensional electron gas. The heterodimensional FET family (2D MESFET, 2DI MESFET, and 2D JFET) has shown significant promise for future high speed, ultra low power applications. We review the recent developments, and report on a new fully ion implanted quasi-heterodimensional FET, the coax-2D JFET.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127617065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722684
K. Kobayashi, J. Cowles, L. Tran, A. Gutierrez-Aitken, T. Block, F. Yamada, A. Oki, D. Streit
This paper reports on what is believed to be the highest frequency bipolar VCO MMIC so far reported. The W-band VCO is based on a push-push oscillator topology which employs InP-HBTs with f/sub T/'s and f/sub max/'s of 70 and 200 GHz, respectively. The W-band VCO produces a maximum oscillating frequency of 108 GHz and delivers an output power of +0.92 dBm into 50 /spl Omega/. The VCO also obtains a tuning range of 2.73 GHz or 2.6% using a monolithic varactor. A phase noise of -88 dBc/Hz and -109 dBc/Hz is achieved at 1 MHz and 10 MHz offsets, respectively, and is believed to be the lowest phase noise reported for a monolithic W-band VCO. The push-push VCO design approach enables higher VCO frequency operation, lower noise performance, and smaller size which is attractive for MM-wave frequency source applications.
{"title":"A low phase noise W-band InP-HBT monolithic push-push VCO","authors":"K. Kobayashi, J. Cowles, L. Tran, A. Gutierrez-Aitken, T. Block, F. Yamada, A. Oki, D. Streit","doi":"10.1109/GAAS.1998.722684","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722684","url":null,"abstract":"This paper reports on what is believed to be the highest frequency bipolar VCO MMIC so far reported. The W-band VCO is based on a push-push oscillator topology which employs InP-HBTs with f/sub T/'s and f/sub max/'s of 70 and 200 GHz, respectively. The W-band VCO produces a maximum oscillating frequency of 108 GHz and delivers an output power of +0.92 dBm into 50 /spl Omega/. The VCO also obtains a tuning range of 2.73 GHz or 2.6% using a monolithic varactor. A phase noise of -88 dBc/Hz and -109 dBc/Hz is achieved at 1 MHz and 10 MHz offsets, respectively, and is believed to be the lowest phase noise reported for a monolithic W-band VCO. The push-push VCO design approach enables higher VCO frequency operation, lower noise performance, and smaller size which is attractive for MM-wave frequency source applications.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133154223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722614
D. Mensa, Q. Lee, J. Guthrie, S. Jaganathan, M. Rodwell
Baseband amplifiers have been fabricated in the transferred-substrate HBT process. A Darlington amplifier achieved a DC gain of 15.6 dB with >50 GHz bandwidth. A mirror doubler amplifier achieved a DC gain of 6.8 dB with 86 GHz bandwidth. These amplifiers will be useful for future work in ADCs, DACs, and fiber-optic receivers, and serve to benchmark the transferred-substrate technology.
{"title":"Baseband amplifiers in transferred-substrate HBT technology","authors":"D. Mensa, Q. Lee, J. Guthrie, S. Jaganathan, M. Rodwell","doi":"10.1109/GAAS.1998.722614","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722614","url":null,"abstract":"Baseband amplifiers have been fabricated in the transferred-substrate HBT process. A Darlington amplifier achieved a DC gain of 15.6 dB with >50 GHz bandwidth. A mirror doubler amplifier achieved a DC gain of 6.8 dB with 86 GHz bandwidth. These amplifiers will be useful for future work in ADCs, DACs, and fiber-optic receivers, and serve to benchmark the transferred-substrate technology.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722649
P. Blount
In this paper we present a sub-harmonically pumped mixer using a mature, commercially available, low cost 0.5 /spl mu/m MESFET process. Housed in a BGA package, the downconverter IC forms an integral part of a receiver system solution in the 17-20 GHz band by supporting an IF of DC to 5 GHz. An on-board LO amplifier is incorporated reducing the drive level requirement to 0 dBm at 8-9 GHz. Due to the use of lumped element matching throughout the design, the mixer itself occupies only 0.2 mm/sup 2/ with an overall chip size of 0.7 mm/sup 2/. The integral LO amplifier is biased at +5 V, drawing 49 mA.
{"title":"A packaged, low cost 17-20 GHz subharmonic downconverter for satellite receiver applications","authors":"P. Blount","doi":"10.1109/GAAS.1998.722649","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722649","url":null,"abstract":"In this paper we present a sub-harmonically pumped mixer using a mature, commercially available, low cost 0.5 /spl mu/m MESFET process. Housed in a BGA package, the downconverter IC forms an integral part of a receiver system solution in the 17-20 GHz band by supporting an IF of DC to 5 GHz. An on-board LO amplifier is incorporated reducing the drive level requirement to 0 dBm at 8-9 GHz. Due to the use of lumped element matching throughout the design, the mixer itself occupies only 0.2 mm/sup 2/ with an overall chip size of 0.7 mm/sup 2/. The integral LO amplifier is biased at +5 V, drawing 49 mA.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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