Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722641
M. Rodwell, Q. Lee, D. Mensa, R. Pullela, J. Guthrie, S. Martin, R.P. Smith, S. Jaganathan, T. Mathew, B. Agarwal, S. Long
Using substrate transfer processes, we have fabricated heterojunction bipolar transistors with submicron emitter-base and collector-base junctions, minimizing RC parasitics and increasing f/sub max/ to 500 GHz. The process also provides a microstrip wiring environment on a low-/spl epsiv//sub r/ dielectric substrate. First design iterations of ECL master-slave flip-flops exhibit 48 GHz maximum clock frequency when connected as static frequency dividers.
利用衬底转移工艺，我们制造了具有亚微米发射基和集电极基结的异质结双极晶体管，最大限度地减少了RC寄生，并将f/sub max/提高到500 GHz。该工艺还提供了在低/spl epsiv/ sub /介电基板上的微带布线环境。当作为静态分频器连接时，ECL主从触发器的第一次设计迭代显示48 GHz的最大时钟频率。
{"title":"48 GHz digital ICs using transferred-substrate HBTs","authors":"M. Rodwell, Q. Lee, D. Mensa, R. Pullela, J. Guthrie, S. Martin, R.P. Smith, S. Jaganathan, T. Mathew, B. Agarwal, S. Long","doi":"10.1109/GAAS.1998.722641","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722641","url":null,"abstract":"Using substrate transfer processes, we have fabricated heterojunction bipolar transistors with submicron emitter-base and collector-base junctions, minimizing RC parasitics and increasing f/sub max/ to 500 GHz. The process also provides a microstrip wiring environment on a low-/spl epsiv//sub r/ dielectric substrate. First design iterations of ECL master-slave flip-flops exhibit 48 GHz maximum clock frequency when connected as static frequency dividers.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128427761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/gaas.1998.722608
J. D. del Alamo, M. Somerville
In spite of their superior transport characteristics, InP HEMTs deliver lower output power than GaAs PHEMTs in the millimeter-wave regime. However, the superior power-added efficiency of InP HEMTs when compared with PHEMTs, makes this technology attractive for many applications. The reason for the lower power output of InP HEMTs is their relatively small off- and on-state breakdown voltage (BV). The authors review the state of knowledge regarding the physics of BV in InP HEMTs placing it in contrast with PHEMTs. They also discuss strategies for improving BV and the power output of InP HEMTs.
{"title":"Breakdown in millimeter-wave power InP HEMTs: a comparison with PHEMTs","authors":"J. D. del Alamo, M. Somerville","doi":"10.1109/gaas.1998.722608","DOIUrl":"https://doi.org/10.1109/gaas.1998.722608","url":null,"abstract":"In spite of their superior transport characteristics, InP HEMTs deliver lower output power than GaAs PHEMTs in the millimeter-wave regime. However, the superior power-added efficiency of InP HEMTs when compared with PHEMTs, makes this technology attractive for many applications. The reason for the lower power output of InP HEMTs is their relatively small off- and on-state breakdown voltage (BV). The authors review the state of knowledge regarding the physics of BV in InP HEMTs placing it in contrast with PHEMTs. They also discuss strategies for improving BV and the power output of InP HEMTs.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"8 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722688
M. Yanagisawa, S. Nakajima, T. Sakurada, M. Kiyama, S. Sawada, R. Nakai
The Vertical Boat (VB) method has an advantage in the manufacture of large diameter GaAs substrates because of the low dislocation density and the small residual strain. The electrical characterization of devices fabricated on VB GaAs substrates have been demonstrated in this work. The VB substrate shows the same or better properties compared with the LEC substrate. We conclude that the VB GaAs substrate is expected to be suitable for the ion-implantation device process with a large diameter.
{"title":"Device characterization of semi-insulating GaAs substrate grown by vertical boat method for ion-implantation process","authors":"M. Yanagisawa, S. Nakajima, T. Sakurada, M. Kiyama, S. Sawada, R. Nakai","doi":"10.1109/GAAS.1998.722688","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722688","url":null,"abstract":"The Vertical Boat (VB) method has an advantage in the manufacture of large diameter GaAs substrates because of the low dislocation density and the small residual strain. The electrical characterization of devices fabricated on VB GaAs substrates have been demonstrated in this work. The VB substrate shows the same or better properties compared with the LEC substrate. We conclude that the VB GaAs substrate is expected to be suitable for the ion-implantation device process with a large diameter.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722616
M. Yu, M. Matloubian, P. Petre, L. Hamilton, R. Bowen, M. Lui, H. Sun, C. Ngo, P. Janke
In this paper we report on the development of W-band MMIC power amplifiers using 0.1 /spl mu/m AlInAs-GaInAs-InP HEMT technology and finite-ground coplanar waveguide (FGCPW) designs. Two single-stage single-ended W-band MMICs using 150 /spl mu/m and 250 /spl mu/m wide HEMTs were designed, fabricated and tested. The results show that the small signal performance of the MMIC using the 150 /spl mu/m wide HEMT has a linear gain of more than 12 dB at 94 GHz. The corresponding amplifier exhibits an output power of 13.8 dBm with a power-added efficiency of 23%. The MMIC using the 250 /spl mu/m wide HEMT demonstrates 9 dB linear gain and the amplifier has a maximum output power of 16.7 dBm with 17.5% power added efficiency at 94 GHz. These power amplifiers are the first ever reported using a CPW configuration at this frequency.
{"title":"W-band InP-based HEMT MMIC power amplifiers using finite-ground CPW design","authors":"M. Yu, M. Matloubian, P. Petre, L. Hamilton, R. Bowen, M. Lui, H. Sun, C. Ngo, P. Janke","doi":"10.1109/GAAS.1998.722616","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722616","url":null,"abstract":"In this paper we report on the development of W-band MMIC power amplifiers using 0.1 /spl mu/m AlInAs-GaInAs-InP HEMT technology and finite-ground coplanar waveguide (FGCPW) designs. Two single-stage single-ended W-band MMICs using 150 /spl mu/m and 250 /spl mu/m wide HEMTs were designed, fabricated and tested. The results show that the small signal performance of the MMIC using the 150 /spl mu/m wide HEMT has a linear gain of more than 12 dB at 94 GHz. The corresponding amplifier exhibits an output power of 13.8 dBm with a power-added efficiency of 23%. The MMIC using the 250 /spl mu/m wide HEMT demonstrates 9 dB linear gain and the amplifier has a maximum output power of 16.7 dBm with 17.5% power added efficiency at 94 GHz. These power amplifiers are the first ever reported using a CPW configuration at this frequency.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124776421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722695
T. Jenkins, L. Kehias, P. Parikh, J. Ibbetson, U. Mishra, D. Docter, Minh Le, K. Kiziloglu, D. Grider, J. Pusl
Record power-added efficiency (PAE) of 89% was obtained at 8 GHz with a gain of 9.6 dB using GaAs on insulator (GOI) MESFETs, which were operated using a 3 V supply. When the voltage was increased to 4 V, the peak PAE was 93% at 210 mW/mm with 9.2 dB gain. The ideal current-voltage characteristics with practically zero leakage current and large transconductance near pinch-off yielded PAE values approaching the theoretical limits of over-driven operation.
{"title":"Record power-added efficiency using GaAs on insulator MESFET technology","authors":"T. Jenkins, L. Kehias, P. Parikh, J. Ibbetson, U. Mishra, D. Docter, Minh Le, K. Kiziloglu, D. Grider, J. Pusl","doi":"10.1109/GAAS.1998.722695","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722695","url":null,"abstract":"Record power-added efficiency (PAE) of 89% was obtained at 8 GHz with a gain of 9.6 dB using GaAs on insulator (GOI) MESFETs, which were operated using a 3 V supply. When the voltage was increased to 4 V, the peak PAE was 93% at 210 mW/mm with 9.2 dB gain. The ideal current-voltage characteristics with practically zero leakage current and large transconductance near pinch-off yielded PAE values approaching the theoretical limits of over-driven operation.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722639
Jianwen Bao, R. Leoni, Xiaohang Du, J.C.M. Hwang, D. M. Shah, J. R. Jones, M. Shokrani
Methods to suppress substrate trap-induced gate lag in ion-implanted GaAs MESFETs have been investigated in detail. It was found that the methods generally involve a supply of holes which can combine with the trapped electrons which are the culprits of gate lag. For high-power amplifiers employing high drain voltages, holes can be supplied through impact ionization. For battery-operated amplifiers employing low drain voltages, holes can be supplied through a contact to the buried p-layer.
{"title":"Reduction of substrate-induced gate lag in GaAs MESFETs","authors":"Jianwen Bao, R. Leoni, Xiaohang Du, J.C.M. Hwang, D. M. Shah, J. R. Jones, M. Shokrani","doi":"10.1109/GAAS.1998.722639","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722639","url":null,"abstract":"Methods to suppress substrate trap-induced gate lag in ion-implanted GaAs MESFETs have been investigated in detail. It was found that the methods generally involve a supply of holes which can combine with the trapped electrons which are the culprits of gate lag. For high-power amplifiers employing high drain voltages, holes can be supplied through impact ionization. For battery-operated amplifiers employing low drain voltages, holes can be supplied through a contact to the buried p-layer.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722662
E. Alekseev, D. Pavlidis, V. Ziegler, M. Berg, J. Dickmann
InP-based InGaAs PIN millimeter-wave diodes were used to design and fabricate monolithic integrated transmit-receive switches for W-band automotive applications. Coplanar-waveguide InGaAs PIN diode technology with reduced parasitics was employed for fabricating MMICs and yielded switches with high isolation and low insertion loss as shown by the performance of W-band single-pole double-throw switches. 77 GHz SPDT switches demonstrated less than 1.35 dB insertion loss, more than 43 dB input-to-output isolation, and more than 30 dB output-to-output crosstalk. W-band on-wafer large-signal characterization revealed no degradation of performance when the input power was increased to the maximum available level of +11 dBm.
{"title":"77 GHz high-isolation coplanar transmit-receive switch using InGaAs/InP PIN diodes","authors":"E. Alekseev, D. Pavlidis, V. Ziegler, M. Berg, J. Dickmann","doi":"10.1109/GAAS.1998.722662","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722662","url":null,"abstract":"InP-based InGaAs PIN millimeter-wave diodes were used to design and fabricate monolithic integrated transmit-receive switches for W-band automotive applications. Coplanar-waveguide InGaAs PIN diode technology with reduced parasitics was employed for fabricating MMICs and yielded switches with high isolation and low insertion loss as shown by the performance of W-band single-pole double-throw switches. 77 GHz SPDT switches demonstrated less than 1.35 dB insertion loss, more than 43 dB input-to-output isolation, and more than 30 dB output-to-output crosstalk. W-band on-wafer large-signal characterization revealed no degradation of performance when the input power was increased to the maximum available level of +11 dBm.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115822607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722645
S. Wada, T. Maeda, M. Tokushima, J. Yamazaki, M. Ishikawa, M. Fujii
We have developed 0.1-/spl mu/m double-deck-shaped (DDS) gate enhancement-mode (E) and depletion-mode (D) heterojunction (HJ) FET technology based upon an all-dry-etching process, which enables high current-gain cut-off frequencies (f/sub T/) in both E- and D-mode FETs above 100 GHz. We also report the first 256/258 dual-modulus prescaler IC operating above 20 GHz with low power consumption. Obtained maximum input frequency for the prescaler was 27 GHz with power consumption of 151 mW at a supply voltage of 1.2 V. This power consumption is about 1/50 of the value extrapolated from ones reported for prescalers.
{"title":"A 27/GHz/151 mW GaAs 256/258 dual-modulus prescaler IC with 0.1 /spl mu/m double-deck-shaped (DDS) gate E/D-HJFETs","authors":"S. Wada, T. Maeda, M. Tokushima, J. Yamazaki, M. Ishikawa, M. Fujii","doi":"10.1109/GAAS.1998.722645","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722645","url":null,"abstract":"We have developed 0.1-/spl mu/m double-deck-shaped (DDS) gate enhancement-mode (E) and depletion-mode (D) heterojunction (HJ) FET technology based upon an all-dry-etching process, which enables high current-gain cut-off frequencies (f/sub T/) in both E- and D-mode FETs above 100 GHz. We also report the first 256/258 dual-modulus prescaler IC operating above 20 GHz with low power consumption. Obtained maximum input frequency for the prescaler was 27 GHz with power consumption of 151 mW at a supply voltage of 1.2 V. This power consumption is about 1/50 of the value extrapolated from ones reported for prescalers.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722638
R. Anholt
Drain barrier lowering gives pinchoff voltages that vary as /spl gamma/Vds, which affects the output conductances. The factor /spl gamma/ depends on the channel aspect ratio X=/spl pi/L/4d, where L is the effective gate length and d is the effective channel depth. For low output conductances we need to minimize /spl gamma/ and maximize the channel aspect ratio X. This paper uses 2D simulations to delineate the effective L and d parameters, and illustrates what can be done to the layer design to minimize d.
{"title":"Drain barrier lowering in HEMTs","authors":"R. Anholt","doi":"10.1109/GAAS.1998.722638","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722638","url":null,"abstract":"Drain barrier lowering gives pinchoff voltages that vary as /spl gamma/Vds, which affects the output conductances. The factor /spl gamma/ depends on the channel aspect ratio X=/spl pi/L/4d, where L is the effective gate length and d is the effective channel depth. For low output conductances we need to minimize /spl gamma/ and maximize the channel aspect ratio X. This paper uses 2D simulations to delineate the effective L and d parameters, and illustrates what can be done to the layer design to minimize d.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-01DOI: 10.1109/GAAS.1998.722692
R. Ribas, J. Lescot, J. Leclercq, J. Karam, F. Ndagijimana
Micromachined microwave passive devices have been successfully fabricated in a standard GaAs HEMT MMIC technology, through a straightforward, low-cost, maskless front-side bulk micromachining. Planar spiral inductors with the strips suspended individually have been possible because of the small 'open area' dimensions, needed to etch away some portions of the bulk material, and present numerous advantages with respect to the commonly used membrane-supported device, such as the reduced etching time and the elimination of fringing parasitic capacitances. In this paper, a two interleaved spiral inductor structure, in a 1:1 transformer-like configuration, has been fabricated and characterized up to 15 GHz, in order to demonstrate the features of this novel inductor. Moreover, heating and mechanical characteristics associated with the suspended devices are also briefly investigated.
{"title":"Monolithic micromachined planar spiral transformer","authors":"R. Ribas, J. Lescot, J. Leclercq, J. Karam, F. Ndagijimana","doi":"10.1109/GAAS.1998.722692","DOIUrl":"https://doi.org/10.1109/GAAS.1998.722692","url":null,"abstract":"Micromachined microwave passive devices have been successfully fabricated in a standard GaAs HEMT MMIC technology, through a straightforward, low-cost, maskless front-side bulk micromachining. Planar spiral inductors with the strips suspended individually have been possible because of the small 'open area' dimensions, needed to etch away some portions of the bulk material, and present numerous advantages with respect to the commonly used membrane-supported device, such as the reduced etching time and the elimination of fringing parasitic capacitances. In this paper, a two interleaved spiral inductor structure, in a 1:1 transformer-like configuration, has been fabricated and characterized up to 15 GHz, in order to demonstrate the features of this novel inductor. Moreover, heating and mechanical characteristics associated with the suspended devices are also briefly investigated.","PeriodicalId":288170,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114161814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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