Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653556
Farid Uddin Ahmed, Zarin Tasnim Sandhie, M. Mohammed, A. H. Yousuf, M. Chowdhury
Fully Depleted Silicon-on-Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are replacing the bulk MOSFET processes for lower technology nodes. Bulk MOSFETs suffer from severe short channel effects and leakage issues. Sleep transistor based power gating circuits are typically used to address leakage power. In this paper, data retention transistor along with sleep transistor is used to improve the performance. The proposed technique is implemented in 20nm FDSOI and 20nm FinFET technology. Simulations are performed in HSPICE and 2-input NAND gate is used for test purpose. It is observed that FinFET-NAND gate consumes 3.75 times less energy compared to FDSOI-NAND gate during active mode. However, FinFET-NAND gate consumes 1.05 times more energy than FDSOI-NAND gate during hold mode.
{"title":"Energy Efficient FDSOI and FinFET based Power Gating Circuit Using Data Retention Transistor","authors":"Farid Uddin Ahmed, Zarin Tasnim Sandhie, M. Mohammed, A. H. Yousuf, M. Chowdhury","doi":"10.1109/NANOTECH.2018.8653556","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653556","url":null,"abstract":"Fully Depleted Silicon-on-Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are replacing the bulk MOSFET processes for lower technology nodes. Bulk MOSFETs suffer from severe short channel effects and leakage issues. Sleep transistor based power gating circuits are typically used to address leakage power. In this paper, data retention transistor along with sleep transistor is used to improve the performance. The proposed technique is implemented in 20nm FDSOI and 20nm FinFET technology. Simulations are performed in HSPICE and 2-input NAND gate is used for test purpose. It is observed that FinFET-NAND gate consumes 3.75 times less energy compared to FDSOI-NAND gate during active mode. However, FinFET-NAND gate consumes 1.05 times more energy than FDSOI-NAND gate during hold mode.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123595255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653555
M. Mohammed, Athiya Nizam, M. Chowdhury
Power saving techniques have become essential for modern digital systems. Large on-chip SRAM memories are used in these systems and therefore it is necessary to optimize SRAM bitcell circuit to minimize the power consumption. In addition to this, it is equally important to design SRAM cell with high reliability and stability. Power gating technique with sleep transistor if applied to SRAM cell will degrade the performance of the cell. In this paper, Fully Depleted Silicon-on-Insulator (FDSOI) device based SRAM designs are proposed which eliminate the requirement of sleep transistors to reduce the power consumption. This reduces overall complexity and overheads of power gating memory designs. Based on this approach seven SRAM bitcell configurations are presented in the paper. Performance metrics of different SRAM configurations are evaluated and compared in HSPICE.
{"title":"Double-Gate FDSOI Based SRAM Bitcell Circuit Designs with Different Back-Gate Biasing Configurations","authors":"M. Mohammed, Athiya Nizam, M. Chowdhury","doi":"10.1109/NANOTECH.2018.8653555","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653555","url":null,"abstract":"Power saving techniques have become essential for modern digital systems. Large on-chip SRAM memories are used in these systems and therefore it is necessary to optimize SRAM bitcell circuit to minimize the power consumption. In addition to this, it is equally important to design SRAM cell with high reliability and stability. Power gating technique with sleep transistor if applied to SRAM cell will degrade the performance of the cell. In this paper, Fully Depleted Silicon-on-Insulator (FDSOI) device based SRAM designs are proposed which eliminate the requirement of sleep transistors to reduce the power consumption. This reduces overall complexity and overheads of power gating memory designs. Based on this approach seven SRAM bitcell configurations are presented in the paper. Performance metrics of different SRAM configurations are evaluated and compared in HSPICE.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114667141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653557
Liaquat Ali, Mahrukh Khan, M. Mohammed, A. H. Yousuf, Ma Chaudhry
This paper presents a high quality biosensor based on silicon photonics optical ring resonator for breast cancer detection. The sensor function by detecting the changes in interaction between light circulating inside the sensor and matter, which is antibody used for breast cancer on the sensor surface. The performance of optical ring resonator is investigate from the sensing point of view by measuring the change in resonance wavelength of ring resonator due to the change in refractive index. We reciprocate the process of binding of breast cancer antibody with respective antigen by changing the radius of ring resonator in simulations.
{"title":"High Quality Silicon Photonics Optical Ring Resonator Biosensor Design","authors":"Liaquat Ali, Mahrukh Khan, M. Mohammed, A. H. Yousuf, Ma Chaudhry","doi":"10.1109/NANOTECH.2018.8653557","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653557","url":null,"abstract":"This paper presents a high quality biosensor based on silicon photonics optical ring resonator for breast cancer detection. The sensor function by detecting the changes in interaction between light circulating inside the sensor and matter, which is antibody used for breast cancer on the sensor surface. The performance of optical ring resonator is investigate from the sensing point of view by measuring the change in resonance wavelength of ring resonator due to the change in refractive index. We reciprocate the process of binding of breast cancer antibody with respective antigen by changing the radius of ring resonator in simulations.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121446414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653561
G. Bhowmik, Mengbing Huang
Silicon Photonics is a disruptive technology that promises to revolutionize high performance computing by taking advantage of light in data transmission. Due to inefficient emission from Si, an outstanding quest has been the development of non-equilibrium group IV nanoscale alloy in achieving new functionalities, such as the formation of a direct bandgap elemental semiconductor. To address this challenge, we propose to use ion beam processing to fabricate Ge1−xSnx alloy nanowires in Ge wafers as a potential material structure for building Si-compatible light sources. Preliminary investigations of ion implantation of Sn into Ge crystals using Rutherford backscattering technique (RBS), their structural properties examined through scanning electron microscopy (SEM) and Sn distribution using energy-dispersive X-ray spectroscopy (EDX), crystallinity and Sn substitutionality using Raman spectroscopy is presented. This non-equilibrium induction of Sn in Ge, a bottom-up approach to formation of direct bandgap Ge1−xSnx nanowires opens up unlimited possibilities in group IV photonics.
{"title":"Development of nanostructured Ge1-xSnx alloy using ion beam techniques for band gap engineering","authors":"G. Bhowmik, Mengbing Huang","doi":"10.1109/NANOTECH.2018.8653561","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653561","url":null,"abstract":"Silicon Photonics is a disruptive technology that promises to revolutionize high performance computing by taking advantage of light in data transmission. Due to inefficient emission from Si, an outstanding quest has been the development of non-equilibrium group IV nanoscale alloy in achieving new functionalities, such as the formation of a direct bandgap elemental semiconductor. To address this challenge, we propose to use ion beam processing to fabricate Ge1−xSnx alloy nanowires in Ge wafers as a potential material structure for building Si-compatible light sources. Preliminary investigations of ion implantation of Sn into Ge crystals using Rutherford backscattering technique (RBS), their structural properties examined through scanning electron microscopy (SEM) and Sn distribution using energy-dispersive X-ray spectroscopy (EDX), crystallinity and Sn substitutionality using Raman spectroscopy is presented. This non-equilibrium induction of Sn in Ge, a bottom-up approach to formation of direct bandgap Ge1−xSnx nanowires opens up unlimited possibilities in group IV photonics.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653566
M. Mohammed, Athiya Nizam, M. Chowdhury
In this paper, the performance and reliability of optimized 6T and 8T SRAM circuits using high ION/IOFF ratio Asymmetrical Underlapped FinFETs are determined at a reduced supply voltage of 500mV. Performance of both SRAM designs are evaluated during read and write operations. 6T SRAM achieves 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N-curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology.
{"title":"Performance and Reliability of Asymmetrical Underlapped FinFET based 6T and 8T SRAMs in Sub-10nm Domain","authors":"M. Mohammed, Athiya Nizam, M. Chowdhury","doi":"10.1109/NANOTECH.2018.8653566","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653566","url":null,"abstract":"In this paper, the performance and reliability of optimized 6T and 8T SRAM circuits using high ION/IOFF ratio Asymmetrical Underlapped FinFETs are determined at a reduced supply voltage of 500mV. Performance of both SRAM designs are evaluated during read and write operations. 6T SRAM achieves 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N-curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"407 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132257585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653562
Siddarth Laveti, T. Manna, Jodi Grzeskowiak, M. Strohmayer, C. Ventrice
The most common technique for producing large area graphene films is by chemical vapor deposition on Cu foil substrates. Cu is used as a substrate because the solubility of carbon in Cu at the temperatures at which the chemical vapor deposition is performed is very low. This ensures a surface-mediated growth that is self-limited to a single monolayer of graphene if low precursor pressures are used. Before performing chemical vapor deposition, the surface oxide and carbon that is on the unprocessed foil need to be removed to achieve uniform graphene growth. In addition, the roughness of the surface of the Cu foil should be reduced to help prevent defects from forming in the graphene film during growth. The goal of this research project is to determine the optimal procedure for preparation of the Cu foil substrate to produce high quality graphene. Cu foils with 99.8% and 99.999% purity were used for the experiment. The Cu substrate preparation procedure involves annealing in 1 × 10−5 Torr of H2 at 850 °C to remove the native oxide and to reduce surface roughness. This is followed by annealing in 1 × 10−6 Torr of O2 at 500 °C to remove carbon from the surface of the foil by conversion to CO2 and CO. At this temperature, the solubility of oxygen in Cu is negligible, thus preventing dissolution of oxygen into the bulk. After the oxygen anneal, the foil is annealed in 1 × 10−5 Torr of H2 at 850 °C to remove chemisorbed oxygen from the Cu surface that has formed during the anneal in O2. The anneal durations in this study were varied to determine the optimal technique for graphene synthesis for each foil purity. The samples were characterized using X-ray photoelectron spectroscopy, scanning electron microscopy, and optical microscopy.
{"title":"Development of Cu Substrate Preparation Techniques for Graphene Synthesis","authors":"Siddarth Laveti, T. Manna, Jodi Grzeskowiak, M. Strohmayer, C. Ventrice","doi":"10.1109/NANOTECH.2018.8653562","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653562","url":null,"abstract":"The most common technique for producing large area graphene films is by chemical vapor deposition on Cu foil substrates. Cu is used as a substrate because the solubility of carbon in Cu at the temperatures at which the chemical vapor deposition is performed is very low. This ensures a surface-mediated growth that is self-limited to a single monolayer of graphene if low precursor pressures are used. Before performing chemical vapor deposition, the surface oxide and carbon that is on the unprocessed foil need to be removed to achieve uniform graphene growth. In addition, the roughness of the surface of the Cu foil should be reduced to help prevent defects from forming in the graphene film during growth. The goal of this research project is to determine the optimal procedure for preparation of the Cu foil substrate to produce high quality graphene. Cu foils with 99.8% and 99.999% purity were used for the experiment. The Cu substrate preparation procedure involves annealing in 1 × 10−5 Torr of H2 at 850 °C to remove the native oxide and to reduce surface roughness. This is followed by annealing in 1 × 10−6 Torr of O2 at 500 °C to remove carbon from the surface of the foil by conversion to CO2 and CO. At this temperature, the solubility of oxygen in Cu is negligible, thus preventing dissolution of oxygen into the bulk. After the oxygen anneal, the foil is annealed in 1 × 10−5 Torr of H2 at 850 °C to remove chemisorbed oxygen from the Cu surface that has formed during the anneal in O2. The anneal durations in this study were varied to determine the optimal technique for graphene synthesis for each foil purity. The samples were characterized using X-ray photoelectron spectroscopy, scanning electron microscopy, and optical microscopy.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653558
Yueming Xu, J. Plawsky, T. Lu
A charge transport model was previously developed in our group to predict intrinsic dielectric failure as a function of voltage for low-k SiCOH and high-k SiN, two materials commonly used in integrated circuits[1], [2]. The model incorporates a set of fundamental mechanisms, including electronical conduction and defect generation, resulting in breakdown when a critical defect density is reached. It replicated electrical conduction through dielectric materials and so can describe the entire history of current flow through the dielectric. Furthermore, a revised version of this model was recently proposed, and it overcame two limitations of the original model: the lack of thickness and temperature dependence. One issue recently investigated was the assumption that the effective velocity of tunneling electrons was the same as mobile electrons. These velocities are used to calculate the electron flux/current. New models separating the two velocities were developed and to fit the experimental data. These newer models offered slightly worse reliability predictions, and so the initial assumption remains not only simpler, but also more accurate so far. This model will be applied to predict the filament formation in resistive switching memory devices.
{"title":"The Development of the Charge Transport Model To Predict Dielectric Failure","authors":"Yueming Xu, J. Plawsky, T. Lu","doi":"10.1109/NANOTECH.2018.8653558","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653558","url":null,"abstract":"A charge transport model was previously developed in our group to predict intrinsic dielectric failure as a function of voltage for low-k SiCOH and high-k SiN, two materials commonly used in integrated circuits[1], [2]. The model incorporates a set of fundamental mechanisms, including electronical conduction and defect generation, resulting in breakdown when a critical defect density is reached. It replicated electrical conduction through dielectric materials and so can describe the entire history of current flow through the dielectric. Furthermore, a revised version of this model was recently proposed, and it overcame two limitations of the original model: the lack of thickness and temperature dependence. One issue recently investigated was the assumption that the effective velocity of tunneling electrons was the same as mobile electrons. These velocities are used to calculate the electron flux/current. New models separating the two velocities were developed and to fit the experimental data. These newer models offered slightly worse reliability predictions, and so the initial assumption remains not only simpler, but also more accurate so far. This model will be applied to predict the filament formation in resistive switching memory devices.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653570
Spencer Flottman, H. Frost, Mark Altwerger, S. Higashiya, D. Sadana, H. Efstathiadis
The rapid adoption of Li-ion batteries with liquid organic electrolytes created many safety issues, due to gas production and leakage of the flammable liquid organic electrolytes when operating at high voltages of ~6V and/or elevated temperatures of ~150°C. A possible solution to this problem is to use solid state electrolytes instead of liquid electrolytes. It has been demonstrated that some solid electrolytes can perform as well as their liquid electrolyte counterparts during battery operation. One such promising solid-state electrolyte is Lithium Aluminum Titanium Phosphate (LATP). Thick LATP films (several micrometers) have shown ionic conductivity of ~3×10−3 S cm−1, which is similar to that of a typical liquid electrolyte’s conductivity. It has excellent long-term stability in contact with the lithium anode and has been evaluated as a solid electrolyte for Li-ion batteries, as well as for electrochromics and deep neural networks. This study is therefore aimed at in-depth exploration of the LATP electrolyte for both the lithium ion battery and neuromorphic devices applications. Our work is focused on studying the influence of sputtering deposition parameters on the composition and the ionic conductivity of LATP that is not well understood. A systematic study to optimize sputtering target power, substrate heating, sputtering vacuum pressure, annealing temperature, atmospheric composition during annealing, and sputtering atmospheric composition was performed. Compositional uniformity of LATP films were analyzed via dynamic secondary ion mass spectroscopy (D-SIMS), nuclear reaction analysis (NRA), and Rutherford backscattered electron spectroscopy (RBS). Results from the aforementioned techniques have shown that deposition of compositionally uniform LATP films can be achieved by co-sputtering of Ti, Al and Li3PO4 on a Si or Si/SiO2 substrate. However, annealing of these films at > 400°C is required to enhance their performance. Microscale batteries (~ 100 μm × 100 μm) created with the annealed LATP films show promising electrolyte behavior. Charging of the batteries with a constant current of 200pA to 4.2V displayed charging and discharging characteristics of a typical battery with no measurable leakage.
液态有机电解质锂离子电池的迅速普及产生了许多安全问题，因为在~6V高压和/或~150°C高温下工作时，易燃液态有机电解质会产生气体和泄漏。一个可能的解决方案是使用固态电解质代替液态电解质。已经证明，在电池运行过程中，一些固体电解质可以表现得和它们的液体电解质一样好。其中一种很有前途的固态电解质是磷酸锂铝钛(LATP)。厚的LATP膜(几微米)的离子电导率为~3×10−3 S cm−1，与典型液体电解质的电导率相似。它在与锂阳极接触时具有优异的长期稳定性，并已被评估为锂离子电池以及电致变色和深度神经网络的固体电解质。因此，本研究旨在深入探索LATP电解质在锂离子电池和神经形态器件中的应用。我们的工作重点是研究溅射沉积参数对LATP成分和离子电导率的影响。对溅射靶功率、衬底加热、溅射真空压力、退火温度、退火过程中大气成分和溅射大气成分进行了系统的优化研究。通过动态二次离子质谱(D-SIMS)、核反应谱(NRA)和卢瑟福背散射电子能谱(RBS)分析了LATP膜的成分均匀性。上述技术的结果表明，通过在Si或Si/SiO2衬底上共溅射Ti、Al和Li3PO4，可以实现成分均匀的LATP薄膜沉积。然而，为了提高这些薄膜的性能，需要在bb0 - 400°C下退火。用退火LATP膜制备的微尺度电池(~ 100 μm × 100 μm)表现出良好的电解质行为。以200pA至4.2V的恒流对电池进行充电，显示典型电池的充放电特性，无可测量的泄漏。
{"title":"Fabrication process validation and investigations of lithium-ionic conductors for all-solid Li-ion batteries","authors":"Spencer Flottman, H. Frost, Mark Altwerger, S. Higashiya, D. Sadana, H. Efstathiadis","doi":"10.1109/NANOTECH.2018.8653570","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653570","url":null,"abstract":"The rapid adoption of Li-ion batteries with liquid organic electrolytes created many safety issues, due to gas production and leakage of the flammable liquid organic electrolytes when operating at high voltages of ~6V and/or elevated temperatures of ~150°C. A possible solution to this problem is to use solid state electrolytes instead of liquid electrolytes. It has been demonstrated that some solid electrolytes can perform as well as their liquid electrolyte counterparts during battery operation. One such promising solid-state electrolyte is Lithium Aluminum Titanium Phosphate (LATP). Thick LATP films (several micrometers) have shown ionic conductivity of ~3×10−3 S cm−1, which is similar to that of a typical liquid electrolyte’s conductivity. It has excellent long-term stability in contact with the lithium anode and has been evaluated as a solid electrolyte for Li-ion batteries, as well as for electrochromics and deep neural networks. This study is therefore aimed at in-depth exploration of the LATP electrolyte for both the lithium ion battery and neuromorphic devices applications. Our work is focused on studying the influence of sputtering deposition parameters on the composition and the ionic conductivity of LATP that is not well understood. A systematic study to optimize sputtering target power, substrate heating, sputtering vacuum pressure, annealing temperature, atmospheric composition during annealing, and sputtering atmospheric composition was performed. Compositional uniformity of LATP films were analyzed via dynamic secondary ion mass spectroscopy (D-SIMS), nuclear reaction analysis (NRA), and Rutherford backscattered electron spectroscopy (RBS). Results from the aforementioned techniques have shown that deposition of compositionally uniform LATP films can be achieved by co-sputtering of Ti, Al and Li3PO4 on a Si or Si/SiO2 substrate. However, annealing of these films at > 400°C is required to enhance their performance. Microscale batteries (~ 100 μm × 100 μm) created with the annealed LATP films show promising electrolyte behavior. Charging of the batteries with a constant current of 200pA to 4.2V displayed charging and discharging characteristics of a typical battery with no measurable leakage.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126685049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653559
Tao Li, Chanro Park, R. Bao, Koji Watanabe
The impact of oxygen containing plasma treatment on the electrical properties of gate stack is evaluated by measuring the interfacial layer thickness as a function of plasma treatment condition and by characterizing electrical parameters, such as threshold voltage (Vt), mobility, and interfacial trap density. X-ray photoelectron spectroscopy (XPS) measurements show that exposure to an oxygen containing plasma can result in interfacial layer growth when not protected by work function metal. This direct exposure may also result in the incorporation of positive charges into the dielectric layer. Incorporating positive charges into the dielectric layer results in a positive shift of Vt. This is further verified by the fact that the hole mobility is degraded after plasma processing. This impact to hole mobility is negated when the work function metal is in place to act as a diffusion barrier between the oxygen containing plasma and the dielectric layers.
{"title":"Plasma treatment effect on gate stack electrical properties","authors":"Tao Li, Chanro Park, R. Bao, Koji Watanabe","doi":"10.1109/NANOTECH.2018.8653559","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653559","url":null,"abstract":"The impact of oxygen containing plasma treatment on the electrical properties of gate stack is evaluated by measuring the interfacial layer thickness as a function of plasma treatment condition and by characterizing electrical parameters, such as threshold voltage (Vt), mobility, and interfacial trap density. X-ray photoelectron spectroscopy (XPS) measurements show that exposure to an oxygen containing plasma can result in interfacial layer growth when not protected by work function metal. This direct exposure may also result in the incorporation of positive charges into the dielectric layer. Incorporating positive charges into the dielectric layer results in a positive shift of Vt. This is further verified by the fact that the hole mobility is degraded after plasma processing. This impact to hole mobility is negated when the work function metal is in place to act as a diffusion barrier between the oxygen containing plasma and the dielectric layers.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114456546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/NANOTECH.2018.8653564
Baiwei Wang, D. Gall
Ti0.5Mg0.5N has recently been predicted to be a semiconductor with a 1.3 eV band gap and promising properties for thermoelectric and plasmonic devices. As a first step towards experimental validation, epitaxial Ti0.5Mg0.5N(001) layers are deposited on MgO(001) by reactive magnetron co-sputtering from titanium and magnesium targets at 600 °C in pure N2 atmospheres. X-ray diffraction ω-2θ scans, ω-rocking curves, φ-scans, and high resolution reciprocal space maps show that Ti0.5Mg0.5N alloys form a pseudobinary rocksalt structure and are single crystals with a cube-on-cube epitaxial relationship with the substrate: (001)TiMgN || (001)MgO and [100]TiMgN || [100]MgO. A 275-nm-thick Ti0.5Mg0.5N layer is fully relaxed and exhibits a 002 ω-rocking curve width Γω = 0.73°, while a 36-nm-thick layer is fully strained and has a Γω = 0.49°. These results indicate a thickness-dependent strain state which suggests a critical thickness for misfit dislocation nucleation and glide which is between 36 and 275 nm. A measured negative temperature coefficient of resistivity in combination with a low optical absorption coefficient of 0.25 × 105 cm−1 for λ = 740 nm, and a vanishing density of states at the Fermi level measured by x-ray photoelectron spectroscopy support the prediction that Ti0.5Mg0.5N is a semiconductor.
{"title":"A new semiconductor: Ti0.5Mg0.5N(001)","authors":"Baiwei Wang, D. Gall","doi":"10.1109/NANOTECH.2018.8653564","DOIUrl":"https://doi.org/10.1109/NANOTECH.2018.8653564","url":null,"abstract":"Ti<inf>0.5</inf>Mg<inf>0.5</inf>N has recently been predicted to be a semiconductor with a 1.3 eV band gap and promising properties for thermoelectric and plasmonic devices. As a first step towards experimental validation, epitaxial Ti<inf>0.5</inf>Mg<inf>0.5</inf>N(001) layers are deposited on MgO(001) by reactive magnetron co-sputtering from titanium and magnesium targets at 600 °C in pure N<inf>2</inf> atmospheres. X-ray diffraction ω-2θ scans, ω-rocking curves, φ-scans, and high resolution reciprocal space maps show that Ti<inf>0.5</inf>Mg<inf>0.5</inf>N alloys form a pseudobinary rocksalt structure and are single crystals with a cube-on-cube epitaxial relationship with the substrate: (001)<inf>TiMgN</inf> || (001)<inf>MgO</inf> and [100]<inf>TiMgN</inf> || [100]<inf>MgO</inf>. A 275-nm-thick Ti<inf>0.5</inf>Mg<inf>0.5</inf>N layer is fully relaxed and exhibits a 002 ω-rocking curve width Γ<inf>ω</inf> = 0.73°, while a 36-nm-thick layer is fully strained and has a Γ<inf>ω</inf> = 0.49°. These results indicate a thickness-dependent strain state which suggests a critical thickness for misfit dislocation nucleation and glide which is between 36 and 275 nm. A measured negative temperature coefficient of resistivity in combination with a low optical absorption coefficient of 0.25 × 10<sup>5</sup> cm<sup>−1</sup> for λ = 740 nm, and a vanishing density of states at the Fermi level measured by x-ray photoelectron spectroscopy support the prediction that Ti<inf>0.5</inf>Mg<inf>0.5</inf>N is a semiconductor.","PeriodicalId":292669,"journal":{"name":"2018 IEEE Nanotechnology Symposium (ANTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124823127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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