Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524113
Yasunori Suzuki, H. Okazaki, T. Asai, Y. Okumura
This paper presents a historical evolution of linearization technologies for power amplifiers of cellular base stations, which has three aspects. One is to reduce the saturation output power level of power amplifiers in multi-carrier base stations in second generation mobile communication systems. Second is to reduce the power consumption of power amplifiers in wideband modulated carrier base stations in third and fourth generation mobile communication systems. Third is to reduce the gain and phase deviations of power amplifiers in Massive MIMO base stations in fifth generation mobile communication systems. This paper shows our research activities of power amplifiers employing the linearization technologies for cellular base stations with regard to the historical evolution, while the linearization technologies will continuously provide a new solution for realizing the cellular base stations in new era.
{"title":"Linearization Technologies for Power Amplifiers of Cellular Base Stations","authors":"Yasunori Suzuki, H. Okazaki, T. Asai, Y. Okumura","doi":"10.1109/RFIT.2018.8524113","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524113","url":null,"abstract":"This paper presents a historical evolution of linearization technologies for power amplifiers of cellular base stations, which has three aspects. One is to reduce the saturation output power level of power amplifiers in multi-carrier base stations in second generation mobile communication systems. Second is to reduce the power consumption of power amplifiers in wideband modulated carrier base stations in third and fourth generation mobile communication systems. Third is to reduce the gain and phase deviations of power amplifiers in Massive MIMO base stations in fifth generation mobile communication systems. This paper shows our research activities of power amplifiers employing the linearization technologies for cellular base stations with regard to the historical evolution, while the linearization technologies will continuously provide a new solution for realizing the cellular base stations in new era.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114061692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524035
Doojin Jang, Taeju Lee, Hyuntak Jeon, Seoktae Koh, Jaesuk Choi, Junghyup Lee, M. Je
This paper presents a neural recording amplifier that operates in environments where large common-mode signals interfere. The proposed scheme employs two types of LDOs that generate isolated supply voltages and a buffer to sense a common-mode signal. Thanks to the isolated supply rails, both the intrinsic common-mode rejection ratio (ICMRR) and common-mode input impedance of the low-noise amplifier (LNA) are increased, which leads to the total common-mode rejection ratio (TCMRR) above 89.2 dB up to 1 kHz even in 16-channel recording with a shared reference electrode. Compared to the conventional method, the TCMRR is improved by 48.7 dB even for 28% mismatch of the electrode-tissue impedance (ETI) and 1% mismatch of the LNA input capacitances.
{"title":"16-Channel High-CMRR Neural-Recording Amplifiers Using Common-Made-Tracking Power Supply Rails","authors":"Doojin Jang, Taeju Lee, Hyuntak Jeon, Seoktae Koh, Jaesuk Choi, Junghyup Lee, M. Je","doi":"10.1109/RFIT.2018.8524035","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524035","url":null,"abstract":"This paper presents a neural recording amplifier that operates in environments where large common-mode signals interfere. The proposed scheme employs two types of LDOs that generate isolated supply voltages and a buffer to sense a common-mode signal. Thanks to the isolated supply rails, both the intrinsic common-mode rejection ratio (ICMRR) and common-mode input impedance of the low-noise amplifier (LNA) are increased, which leads to the total common-mode rejection ratio (TCMRR) above 89.2 dB up to 1 kHz even in 16-channel recording with a shared reference electrode. Compared to the conventional method, the TCMRR is improved by 48.7 dB even for 28% mismatch of the electrode-tissue impedance (ETI) and 1% mismatch of the LNA input capacitances.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114279633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524128
Feifei Chen, Yunshan Wang, Jung-Lin Lin, Zuo‐Min Tsai, Huei Wang
A 24-GHz high linearity down-conversion mixer in 90-nm CMOS is presented in this paper. The mixer utilizes folded architecture, LC tank, distributed derivative superposition (DS) linearization technique to achieve high linearity with relatively low power. The mixer achieves 0 dBm $boldsymbol{IP}_{1mathbf{dB}}$. The mixer provides −3 dB conversion gain and the IIP3 is 21 dBm with only 10-mW dc consumption.
{"title":"A 24-GHz High Linearity Down-conversion Mixer in 90-nm CMOS","authors":"Feifei Chen, Yunshan Wang, Jung-Lin Lin, Zuo‐Min Tsai, Huei Wang","doi":"10.1109/RFIT.2018.8524128","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524128","url":null,"abstract":"A 24-GHz high linearity down-conversion mixer in 90-nm CMOS is presented in this paper. The mixer utilizes folded architecture, LC tank, distributed derivative superposition (DS) linearization technique to achieve high linearity with relatively low power. The mixer achieves 0 dBm $boldsymbol{IP}_{1mathbf{dB}}$. The mixer provides −3 dB conversion gain and the IIP3 is 21 dBm with only 10-mW dc consumption.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133506330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524122
Peigen Zhou, Haoyi Dong, Zhigang Peng, Jixin Chen, Debin Hou, P. Yan, Yu Xiang, W. Hong
This paper presents a sigle-pole double-throw (SPDT) switch using a $0.13 {mu} mathbf{m}$ reverse saturated SiGe HBTs. The switch is based on ${lambda}/4$ transmission line and the performance of insertion loss and isolation is improved by adding a small area of substrate contacts around the NPN transistors and an isolation-boosting inductance between the collector and emitter, respectively. A measured insertion loss of 1.4-1.6 dB is achieved at 81-98 GHz and < 2.5 dB in the whole W-band frequencies. The measured output port-to-port isolation is > 25 dB at 78-97 GHz and > 20dB in W-band frequencies. The return loss is better than 10 dB at 75-102 GHz. To the best of the authors' knowledge, the proposed switch demonstrates the lowest insertion loss in the silicon-based SPDT switches in W-band frequencies.
{"title":"A W-Band Low Loss, High Power SPDT Switch Using Reverse Saturated $0.13 mu mathrm{m}$ SiGe HBTs","authors":"Peigen Zhou, Haoyi Dong, Zhigang Peng, Jixin Chen, Debin Hou, P. Yan, Yu Xiang, W. Hong","doi":"10.1109/RFIT.2018.8524122","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524122","url":null,"abstract":"This paper presents a sigle-pole double-throw (SPDT) switch using a $0.13 {mu} mathbf{m}$ reverse saturated SiGe HBTs. The switch is based on ${lambda}/4$ transmission line and the performance of insertion loss and isolation is improved by adding a small area of substrate contacts around the NPN transistors and an isolation-boosting inductance between the collector and emitter, respectively. A measured insertion loss of 1.4-1.6 dB is achieved at 81-98 GHz and < 2.5 dB in the whole W-band frequencies. The measured output port-to-port isolation is > 25 dB at 78-97 GHz and > 20dB in W-band frequencies. The return loss is better than 10 dB at 75-102 GHz. To the best of the authors' knowledge, the proposed switch demonstrates the lowest insertion loss in the silicon-based SPDT switches in W-band frequencies.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"784 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134583825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524095
K. Nishikawa, M. Muraguchi
This paper proposed and demonstrated a novel dual-mode frequency tunable band-pass filter (BPF) with capacitive coupling. The proposed three-pole microstrip-type combline BPF can tune both a center frequency and an operating frequency bandwidth with varactors. The varactors connected at the edge of the resonators and between the resonators tune the center frequency and the operating bandwidth, respectively. The varactors between the resonators make strong capacitive coupling, resulting in less magnetic coupling. The dual-mode tunable BPF also realizes high out-of-band signal suppression due to the capacitive coupling and the optimum varactor location connected at the resonator. The proposed configuration effectively realizes high level stopband rejection and wide range tunings. The fabricated tunable BPF achieved 26% tuning range, 8-16% variable bandwidth, and a maximum loss of 4.6dB. The stopband rejection range more than 40dB is 134%. The proposed three-pole dual-mode tunable BPF is the top-level performances in planar type tunable filters.
{"title":"Dual-Mode Frequency Tunable Planar Filter Design with Capacitive Coupling Technique","authors":"K. Nishikawa, M. Muraguchi","doi":"10.1109/RFIT.2018.8524095","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524095","url":null,"abstract":"This paper proposed and demonstrated a novel dual-mode frequency tunable band-pass filter (BPF) with capacitive coupling. The proposed three-pole microstrip-type combline BPF can tune both a center frequency and an operating frequency bandwidth with varactors. The varactors connected at the edge of the resonators and between the resonators tune the center frequency and the operating bandwidth, respectively. The varactors between the resonators make strong capacitive coupling, resulting in less magnetic coupling. The dual-mode tunable BPF also realizes high out-of-band signal suppression due to the capacitive coupling and the optimum varactor location connected at the resonator. The proposed configuration effectively realizes high level stopband rejection and wide range tunings. The fabricated tunable BPF achieved 26% tuning range, 8-16% variable bandwidth, and a maximum loss of 4.6dB. The stopband rejection range more than 40dB is 134%. The proposed three-pole dual-mode tunable BPF is the top-level performances in planar type tunable filters.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128433131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524130
Yun Wang, Rui Wu, K. Okada
This paper presents design of a 39-GHz power amplifier for fifth-generation (5G) mobile communication in millimeter-wave. The power amplifier consists of two differential capacitive-neutralized common-source stages. Low-loss transformers are employed for matching network in each stage. With 1.1-V supply, the power amplifier achieves a small-signal gain of 17 dB, saturated output power (PSAT) of 17.2 dBm, and 1-dB compression point (P1dB) of 15.5 dBm at 39 GHz. The amplifier has a maximum power-added efficiency (PAEMAX) of 31.2% and 30.2% at P1dB. The amplifier has an average output power of 9.0 dBm and 10.0% PAE with −25 dBc EVM. The amplifier has been fabricated in standard 65-nm CMOS and occupies an area of 0.081 mm2.
{"title":"A Compact 39-GHz 17.2-dBm Power Amplifier for 5G Communication in 65-nm CMOS","authors":"Yun Wang, Rui Wu, K. Okada","doi":"10.1109/RFIT.2018.8524130","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524130","url":null,"abstract":"This paper presents design of a 39-GHz power amplifier for fifth-generation (5G) mobile communication in millimeter-wave. The power amplifier consists of two differential capacitive-neutralized common-source stages. Low-loss transformers are employed for matching network in each stage. With 1.1-V supply, the power amplifier achieves a small-signal gain of 17 dB, saturated output power (PSAT) of 17.2 dBm, and 1-dB compression point (P1dB) of 15.5 dBm at 39 GHz. The amplifier has a maximum power-added efficiency (PAEMAX) of 31.2% and 30.2% at P1dB. The amplifier has an average output power of 9.0 dBm and 10.0% PAE with −25 dBc EVM. The amplifier has been fabricated in standard 65-nm CMOS and occupies an area of 0.081 mm2.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130987442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524055
Yupeng Fu, Lianming Li, Dongming Wang
A fractional-N divider with delta-sigma modulator and phase-lag selector for phase-locked loop (PLL) is presented in this paper. Basically, the fractional-N frequency divider consists of a pre-divide-by-2 frequency divider (Div. 2), a phase selector (PS) with the auxiliary circuit, a multi-modulus frequency divider (MMD) and a delta-sigma modulator (DSM). With a 65nm CMOS process, the high speed circuit, like Div. 2, and low power circuits, like MMD and DSM, are designed. The proposed divider achieves 8.5GHz maximum operating frequency with 32–256 division range and less than 25 Hz frequency resolution. The divider power consumption is less than 8mA from a 1.2 V power supply at 6GHz.
{"title":"A Fractional-N Divider for Phase-Locked Loop with Delta-Sigma Modulator and Phase-Lag Selector","authors":"Yupeng Fu, Lianming Li, Dongming Wang","doi":"10.1109/RFIT.2018.8524055","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524055","url":null,"abstract":"A fractional-N divider with delta-sigma modulator and phase-lag selector for phase-locked loop (PLL) is presented in this paper. Basically, the fractional-N frequency divider consists of a pre-divide-by-2 frequency divider (Div. 2), a phase selector (PS) with the auxiliary circuit, a multi-modulus frequency divider (MMD) and a delta-sigma modulator (DSM). With a 65nm CMOS process, the high speed circuit, like Div. 2, and low power circuits, like MMD and DSM, are designed. The proposed divider achieves 8.5GHz maximum operating frequency with 32–256 division range and less than 25 Hz frequency resolution. The divider power consumption is less than 8mA from a 1.2 V power supply at 6GHz.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131196589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524116
D. Kholodnyak
Frequency characteristics of artificial transmission lines consisting of different number of cascaded unit cells with variable capacitors to tune the center frequency are investigated. Analysis of tunability constraints is presented. Design issues are considered with an emphasis to applications in small-size tunable RF and microwave devices.
{"title":"Tunability of Artificial Transmission Lines with Variable Capacitors","authors":"D. Kholodnyak","doi":"10.1109/RFIT.2018.8524116","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524116","url":null,"abstract":"Frequency characteristics of artificial transmission lines consisting of different number of cascaded unit cells with variable capacitors to tune the center frequency are investigated. Analysis of tunability constraints is presented. Design issues are considered with an emphasis to applications in small-size tunable RF and microwave devices.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524030
Sangyeop Lee, K. Takano, R. Dong, S. Amakawa, T. Yoshida, M. Fujishima
An ultra-low-power K-band oscillator, which consumes $300 {mu} mathbf{W}$ from a 0.31-V voltage supply, is implemented using a 55-nm CMOS deeply-depleted-channel (DDC) technology. For the oscillation frequency of 17.9 GHz, the 1-MHz-offset phase noise is −97 dBc/Hz. An unusually wide transmission line is used to build the tank circuit. An open stub composed of such a line turns out to work as a higher-Q capacitor than a standard metal-insulator-metal (MIM) capacitor and contributes to the low-voltage operation.
{"title":"A $300-mu mathrm{W}$ K-Band Oscillator with High-Q Open-Stub Capacitor in 55-nm CMOS DDC","authors":"Sangyeop Lee, K. Takano, R. Dong, S. Amakawa, T. Yoshida, M. Fujishima","doi":"10.1109/RFIT.2018.8524030","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524030","url":null,"abstract":"An ultra-low-power K-band oscillator, which consumes $300 {mu} mathbf{W}$ from a 0.31-V voltage supply, is implemented using a 55-nm CMOS deeply-depleted-channel (DDC) technology. For the oscillation frequency of 17.9 GHz, the 1-MHz-offset phase noise is −97 dBc/Hz. An unusually wide transmission line is used to build the tank circuit. An open stub composed of such a line turns out to work as a higher-Q capacitor than a standard metal-insulator-metal (MIM) capacitor and contributes to the low-voltage operation.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127619838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/RFIT.2018.8524073
Vishal Kumar, S. Koul, A. Basu
In this paper, a novel RF MEMS shunt switch with enhanced reliability is presented. A Ka-band shunt switch which is fabricated on a high resistivity silicon substrate implements a novel concept of tri-layer sandwich (insulator-Metal-insulator) membrane which results a lower actuation voltage of 10 Volt. The switch is actuated using electrostatic actuation mechanism and has the measured insertion loss and isolation of 1.94 dB and 18 dB at 40 GHz respectively. The switching speed of the switch is $76 mutext{sec}$ and works well up to one billion cycles of operation without deterioration in performance. The switch provides a solution for low voltage communication system applications.
{"title":"RF MEMS Switch with Enhanced Reliability","authors":"Vishal Kumar, S. Koul, A. Basu","doi":"10.1109/RFIT.2018.8524073","DOIUrl":"https://doi.org/10.1109/RFIT.2018.8524073","url":null,"abstract":"In this paper, a novel RF MEMS shunt switch with enhanced reliability is presented. A Ka-band shunt switch which is fabricated on a high resistivity silicon substrate implements a novel concept of tri-layer sandwich (insulator-Metal-insulator) membrane which results a lower actuation voltage of 10 Volt. The switch is actuated using electrostatic actuation mechanism and has the measured insertion loss and isolation of 1.94 dB and 18 dB at 40 GHz respectively. The switching speed of the switch is $76 mutext{sec}$ and works well up to one billion cycles of operation without deterioration in performance. The switch provides a solution for low voltage communication system applications.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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