Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628239
H. Brech, T. Grave, T. Simlinger, S. Selberherr
Combined hydrodynamic/drift-diffusion simulations of GaAs-based pseudomorphic high electron mobility transistors (PHEMTs) are presented. They do not only take into account the structure of the intrinsic transistor but also model the complex geometries of contacts and dielectric passivation in a realistic manner. Special care was taken to implement a general scheme for the T-gate cross section that allows to model gate profiles realized with electron beam lithography as well as with spacer processes based on optical lithography. Measured dc and RF data of two different PHEMTs (gate lengths 220 and 500 mm, respectively) manufactured on the same wafer with spacer technology are calculated very exactly. The simulator is then used to predict the effects of gate length reduction, modification of the T-gate profile and thinning of the passivation on device RF performance quantitatively. The specific problems of gate spacer processes applied to high frequency devices are identified, and the most effective process improvements are indicated.
{"title":"Influence of T-gate shape and footprint length on PHEMT high frequency performance","authors":"H. Brech, T. Grave, T. Simlinger, S. Selberherr","doi":"10.1109/GAAS.1997.628239","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628239","url":null,"abstract":"Combined hydrodynamic/drift-diffusion simulations of GaAs-based pseudomorphic high electron mobility transistors (PHEMTs) are presented. They do not only take into account the structure of the intrinsic transistor but also model the complex geometries of contacts and dielectric passivation in a realistic manner. Special care was taken to implement a general scheme for the T-gate cross section that allows to model gate profiles realized with electron beam lithography as well as with spacer processes based on optical lithography. Measured dc and RF data of two different PHEMTs (gate lengths 220 and 500 mm, respectively) manufactured on the same wafer with spacer technology are calculated very exactly. The simulator is then used to predict the effects of gate length reduction, modification of the T-gate profile and thinning of the passivation on device RF performance quantitatively. The specific problems of gate spacer processes applied to high frequency devices are identified, and the most effective process improvements are indicated.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130416502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628262
R. Leoni, J. Bao, X. Du, M. Shirokov, J.C.M. Hwang
Effects of reverse gate-drain current stress on the characteristics of GaAs power MESFET's were investigated. In addition to the previously reported power-slump effect, the gate-lag characteristic became worse. Conductance DLTS measurements of the device before and after stress revealed no new types of surface traps. Further investigation showed gate lag was worsened by a decrease in impact ionization which slowed the hole capture rate. This confirms that power slump is caused by electron traps in the passivation, while gate lag is aggravated by increased sensitivity of existing surface traps to the gate potential.
{"title":"Conductance DLTS analysis of the correlation between power slump and gate lag","authors":"R. Leoni, J. Bao, X. Du, M. Shirokov, J.C.M. Hwang","doi":"10.1109/GAAS.1997.628262","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628262","url":null,"abstract":"Effects of reverse gate-drain current stress on the characteristics of GaAs power MESFET's were investigated. In addition to the previously reported power-slump effect, the gate-lag characteristic became worse. Conductance DLTS measurements of the device before and after stress revealed no new types of surface traps. Further investigation showed gate lag was worsened by a decrease in impact ionization which slowed the hole capture rate. This confirms that power slump is caused by electron traps in the passivation, while gate lag is aggravated by increased sensitivity of existing surface traps to the gate potential.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125324977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628242
R. Hattori, G. Nakamura, S. Nomura, T. Ichise, A. Masuda, H. Matsumura
We improved the catalytic (cat-) CVD technique for damage free passivation on compound semiconductors. The cat-CVD SiN passivation successfully reduces the noise figure of X-band pHEMTs because Rs and Cgs are reduced due to low deposition damage.
{"title":"Noise reduction of pHEMTs with plasmaless SiN passivation by catalytic CVD","authors":"R. Hattori, G. Nakamura, S. Nomura, T. Ichise, A. Masuda, H. Matsumura","doi":"10.1109/GAAS.1997.628242","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628242","url":null,"abstract":"We improved the catalytic (cat-) CVD technique for damage free passivation on compound semiconductors. The cat-CVD SiN passivation successfully reduces the noise figure of X-band pHEMTs because Rs and Cgs are reduced due to low deposition damage.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131625032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628253
R. Ribas, N. Bennouri, J. Karam, B. Courtois
This paper presents the GaAs front-side bulk micromachining using the 0.2 /spl mu/m HEMT MMIC technology from Philips Microwave Limeil (PML). The free-standing structures are obtained by removing wells of the GaAs substrate through an additional post-process wet chemical etching, without any modification in the standard IC fabrication and with no influence on the electronic behaviour. It is a very flexible approach to construct bridges, cantilevers and membranes. In respect to the suspended material and vertical profile, different structures could be realized according to the etching solution used and the layout arrangement. Among potential applications, thermopile based devices, such as infrared sensors, gas-flow sensors and thermoconverters could be targeted using GaAs/metal thermocouples. Moreover, suspended microstrips transmission lines and planar spiral inductor are also very useful to enhance the RF circuit performance. Finally, a complete CAD engineering kit containing the micromachining design rules, layout generators and a cross-section viewer has been developed on the Mentor Graphics framework.
{"title":"GaAs MEMS design using 0.2 /spl mu/m HEMT MMIC technology","authors":"R. Ribas, N. Bennouri, J. Karam, B. Courtois","doi":"10.1109/GAAS.1997.628253","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628253","url":null,"abstract":"This paper presents the GaAs front-side bulk micromachining using the 0.2 /spl mu/m HEMT MMIC technology from Philips Microwave Limeil (PML). The free-standing structures are obtained by removing wells of the GaAs substrate through an additional post-process wet chemical etching, without any modification in the standard IC fabrication and with no influence on the electronic behaviour. It is a very flexible approach to construct bridges, cantilevers and membranes. In respect to the suspended material and vertical profile, different structures could be realized according to the etching solution used and the layout arrangement. Among potential applications, thermopile based devices, such as infrared sensors, gas-flow sensors and thermoconverters could be targeted using GaAs/metal thermocouples. Moreover, suspended microstrips transmission lines and planar spiral inductor are also very useful to enhance the RF circuit performance. Finally, a complete CAD engineering kit containing the micromachining design rules, layout generators and a cross-section viewer has been developed on the Mentor Graphics framework.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124701130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628241
J.G. Wang, K. Hur, L. Studebaker, B. Keppeler, A. Quach
A 0.15 um gate process using a deep-UV stepper and phase-shifting mask lithography has been developed. This process eliminates the need for low throughput, direct write e-beam gate lithography. Using this process we have fabricated, for the first time, AlInAs/GaInAs MHEMTs on GaAs with f/sub t/'s up to 119 GHz. This optical approach for gate lithography is very attractive for manufacturing high volume, high performance, low cost GaAs integrated circuits.
{"title":"0.15 micron gate AlInAs/GaInAs MHEMT fabricated on GaAs using deep-UV phase-shifting mask lithography","authors":"J.G. Wang, K. Hur, L. Studebaker, B. Keppeler, A. Quach","doi":"10.1109/GAAS.1997.628241","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628241","url":null,"abstract":"A 0.15 um gate process using a deep-UV stepper and phase-shifting mask lithography has been developed. This process eliminates the need for low throughput, direct write e-beam gate lithography. Using this process we have fabricated, for the first time, AlInAs/GaInAs MHEMTs on GaAs with f/sub t/'s up to 119 GHz. This optical approach for gate lithography is very attractive for manufacturing high volume, high performance, low cost GaAs integrated circuits.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130104956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628240
S. Wada, J. Yamazaki, M. Ishikawa, T. Maeda
This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-/spl mu/m DDS gate-openings adapted to the reduction in C/sub f//sup ext/ and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-/spl mu/m DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al/sub 0.2/Ga/sub 0.8/As-In/sub 0.15/Ga/sub 0.75/As HJFETs exhibit an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV. Also, the HJFET covered with a SiO/sub 2/ film shows a very high millimeter-wave performance with f/sub T/ of 120 GHz and f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/. In addition, a high f/sub T/ of 151 GHz and f/sub max/ of 186 GHz are obtained without a SiO/sub 2/ film.
{"title":"A 0.1-/spl mu/m double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs","authors":"S. Wada, J. Yamazaki, M. Ishikawa, T. Maeda","doi":"10.1109/GAAS.1997.628240","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628240","url":null,"abstract":"This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-/spl mu/m DDS gate-openings adapted to the reduction in C/sub f//sup ext/ and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-/spl mu/m DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al/sub 0.2/Ga/sub 0.8/As-In/sub 0.15/Ga/sub 0.75/As HJFETs exhibit an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV. Also, the HJFET covered with a SiO/sub 2/ film shows a very high millimeter-wave performance with f/sub T/ of 120 GHz and f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/. In addition, a high f/sub T/ of 151 GHz and f/sub max/ of 186 GHz are obtained without a SiO/sub 2/ film.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134084278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628278
K. Kobayashi, L. Tran, M. Lammert, T. Block, P. Grossman, A. Oki, D. Streit
Here we report on direct-coupled HBT MMIC LNAs which achieve sub-1.3 dB noise figures up to 2 GHz. This is believed to be the lowest noise figure (NF) reported for a 50/spl Omega/ MMIC-matched LNA in this frequency range. The LNAs are based on a new 1-/spl mu/m GaAs HBT technology which provides high DC current gains of >400 and f/sub T/'s in excess of 40 GHz and enables low broadband amplifier noise figure performance. A DC-3.2 GHz HBT LNA (DCLNA2) design achieves a gain of 24.6 dB and sub-1.3 dB NF up to 2 GHz while consuming only 7.8 mA of current. The minimum LNA noise figure is 1.22 dB at 1.5 GHz. A DC-6 GHz design (DCLNA1) achieves 26.1 dB gain and a NF less than 2 dB up to 4 GHz while consuming 16.4 mA. The NF at 6 GHz is 2.52 dB with a corresponding IP3 of 11 dBm. These HBT MMICs provide a low cost LNA solution for receiver applications encompassing the industrial-scientific-medical (ISM) wireless bands.
{"title":"Sub-1.3 dB noise figure direct-coupled MMIC LNAs using a high current-gain 1-/spl mu/m GaAs HBT technology","authors":"K. Kobayashi, L. Tran, M. Lammert, T. Block, P. Grossman, A. Oki, D. Streit","doi":"10.1109/GAAS.1997.628278","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628278","url":null,"abstract":"Here we report on direct-coupled HBT MMIC LNAs which achieve sub-1.3 dB noise figures up to 2 GHz. This is believed to be the lowest noise figure (NF) reported for a 50/spl Omega/ MMIC-matched LNA in this frequency range. The LNAs are based on a new 1-/spl mu/m GaAs HBT technology which provides high DC current gains of >400 and f/sub T/'s in excess of 40 GHz and enables low broadband amplifier noise figure performance. A DC-3.2 GHz HBT LNA (DCLNA2) design achieves a gain of 24.6 dB and sub-1.3 dB NF up to 2 GHz while consuming only 7.8 mA of current. The minimum LNA noise figure is 1.22 dB at 1.5 GHz. A DC-6 GHz design (DCLNA1) achieves 26.1 dB gain and a NF less than 2 dB up to 4 GHz while consuming 16.4 mA. The NF at 6 GHz is 2.52 dB with a corresponding IP3 of 11 dBm. These HBT MMICs provide a low cost LNA solution for receiver applications encompassing the industrial-scientific-medical (ISM) wireless bands.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131793010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628267
A. Yuen, K. Giboney, E. Wong, L. Buckman, D. Haritos, P. Rosenberg, D. Dolfi
Parallel optical interconnection technology can solve many of the current data bottlenecks that exist due to the ever growing Internet usage and the increasing speeds of processors. As a result many optoelectronic companies have begun to make parallel optical modules available with a variety of performances and costs. This paper will present an overview of the current work being done in this area.
{"title":"Parallel optical links for gigabyte/s data communication","authors":"A. Yuen, K. Giboney, E. Wong, L. Buckman, D. Haritos, P. Rosenberg, D. Dolfi","doi":"10.1109/GAAS.1997.628267","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628267","url":null,"abstract":"Parallel optical interconnection technology can solve many of the current data bottlenecks that exist due to the ever growing Internet usage and the increasing speeds of processors. As a result many optoelectronic companies have begun to make parallel optical modules available with a variety of performances and costs. This paper will present an overview of the current work being done in this area.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122709956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628282
J. Mueller, P. Baureis, O. Berger, T. Boettner, N. Bovolon, G. Packeiser, P. Zwicknagl
A 62% power added efficiency (PAE) AlGaAs-GaAs HBT MMIC power amplifier with a very small chip size of 1.2 mm/sup 2/ for use in PCN applications (1800 MHz) is described. Maximum output power is 2 W at only a single voltage supply of 3 V. The linear gain of the two-stage MMIC is 33 dB. To our knowledge this is the best combination of power performance data for wireless applications demonstrated so far for a MMIC. The chip size is more than a factor of four smaller than comparable MMICs known before. The MMIC offers the potential both for low cost production due to small chip size, single voltage supply and high performance at the same time.
{"title":"A 2 W, 62% PAE, small chip size HBT MMIC for 3 V PCN applications","authors":"J. Mueller, P. Baureis, O. Berger, T. Boettner, N. Bovolon, G. Packeiser, P. Zwicknagl","doi":"10.1109/GAAS.1997.628282","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628282","url":null,"abstract":"A 62% power added efficiency (PAE) AlGaAs-GaAs HBT MMIC power amplifier with a very small chip size of 1.2 mm/sup 2/ for use in PCN applications (1800 MHz) is described. Maximum output power is 2 W at only a single voltage supply of 3 V. The linear gain of the two-stage MMIC is 33 dB. To our knowledge this is the best combination of power performance data for wireless applications demonstrated so far for a MMIC. The chip size is more than a factor of four smaller than comparable MMICs known before. The MMIC offers the potential both for low cost production due to small chip size, single voltage supply and high performance at the same time.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"393 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122772717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-12DOI: 10.1109/GAAS.1997.628238
A. Kanda, S. Kodama, T. Furuta, T. Nittono, T. Ishibashi, M. Muraguchi
19 GHz-band GaAs MESFET switch ICs have been demonstrated, intended for use in high-speed wireless LAN systems. The FET channel is fabricated on a SiO/sub 2/ insulator in order to reduce parasitic FET drain-source capacitance (Cds) which acts as off-state capacitance (Coff) in switches. The LOXI (Layered-Oxide-Isolation)-MESFET has enough DC and RF performance for use as an active device. On-state FET resistance (Ron) remains the same as that of conventional MESFETs white Coff is reduced. This allows the use of larger gate-width switch FETs, which yield low insertion loss. The measured simple SPST (single-pole, single-throw) switch has low insertion loss of 0.5 dB and high isolation of 23 dB at 19 GHz. The measured simple SPDT (single-pole, double throw) switch also has good characteristics, 0.8 dB insertion loss and 17 dB isolation at 19 GHz.
{"title":"High-performance 19 GHz-band GaAs FET switches using LOXI (Layered-Oxide-Isolation)-MESFETs","authors":"A. Kanda, S. Kodama, T. Furuta, T. Nittono, T. Ishibashi, M. Muraguchi","doi":"10.1109/GAAS.1997.628238","DOIUrl":"https://doi.org/10.1109/GAAS.1997.628238","url":null,"abstract":"19 GHz-band GaAs MESFET switch ICs have been demonstrated, intended for use in high-speed wireless LAN systems. The FET channel is fabricated on a SiO/sub 2/ insulator in order to reduce parasitic FET drain-source capacitance (Cds) which acts as off-state capacitance (Coff) in switches. The LOXI (Layered-Oxide-Isolation)-MESFET has enough DC and RF performance for use as an active device. On-state FET resistance (Ron) remains the same as that of conventional MESFETs white Coff is reduced. This allows the use of larger gate-width switch FETs, which yield low insertion loss. The measured simple SPST (single-pole, single-throw) switch has low insertion loss of 0.5 dB and high isolation of 23 dB at 19 GHz. The measured simple SPDT (single-pole, double throw) switch also has good characteristics, 0.8 dB insertion loss and 17 dB isolation at 19 GHz.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130413188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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