Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612135
J. Weber, E. Oruklu, J. Saniie
Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages when compared to a traditional processor datapath, especially for reconfigurable platforms such as FPGAs. This paper presents an architecture integrating NoC concepts into the design of a processor datapath in order to create a polymorphic processor. The paper will further explore and analyze the effect of topology choices and NoC design on the performance of polymorphic processors with specific focus on the impacts of NoC datapath integration.
{"title":"NoC datapath for polymorphic processors in embedded systems","authors":"J. Weber, E. Oruklu, J. Saniie","doi":"10.1109/EIT.2010.5612135","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612135","url":null,"abstract":"Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages when compared to a traditional processor datapath, especially for reconfigurable platforms such as FPGAs. This paper presents an architecture integrating NoC concepts into the design of a processor datapath in order to create a polymorphic processor. The paper will further explore and analyze the effect of topology choices and NoC design on the performance of polymorphic processors with specific focus on the impacts of NoC datapath integration.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130098576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612114
Jeff Rebacz, E. Oruklu, J. Saniie
General-Purpose Computing on Graphics Processing Units (GPGPU) has lately been of great interest due to the release of architectures and software that simplifies programming graphics cards. This study explores how performance scales with FIR digital filters by varying the number of taps and the samples. We also discuss the trade-offs with various techniques for GPGPU programming in CUDA.
{"title":"Exploring scalability of FIR filter realizations on Graphics Processing Units","authors":"Jeff Rebacz, E. Oruklu, J. Saniie","doi":"10.1109/EIT.2010.5612114","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612114","url":null,"abstract":"General-Purpose Computing on Graphics Processing Units (GPGPU) has lately been of great interest due to the release of architectures and software that simplifies programming graphics cards. This study explores how performance scales with FIR digital filters by varying the number of taps and the samples. We also discuss the trade-offs with various techniques for GPGPU programming in CUDA.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612185
Hussein R. Al-Zoubi
In this paper we propose a coin recognition system using a statistical approach and apply it to the recognition of Jordanian coins. The proposed method depends on two features in the recognition process: the color of the coin, and its area. The recognition process consists of several steps. Firstly, a gray-level image is extracted from the original colored image. The image is then segmented into two regions, coin and background, based on the histogram drawn from the gray-level image. To reduce the noise, the segmented image is then cleaned by opening and closing through several erosion and dilation operations. After that, four parameters are calculated, the area, the average red, blue, and green colors of the coin to be recognized. Based on these parameters, the decision to which category the coin belongs is obtained. The results provided illustrate that the proposed approach is both simple and accurate. Although the proposed recognition approach is applied to Jordanian coins, it can be applied to the recognition of any coins.
{"title":"Efficient coin recognition using a statistical approach","authors":"Hussein R. Al-Zoubi","doi":"10.1109/EIT.2010.5612185","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612185","url":null,"abstract":"In this paper we propose a coin recognition system using a statistical approach and apply it to the recognition of Jordanian coins. The proposed method depends on two features in the recognition process: the color of the coin, and its area. The recognition process consists of several steps. Firstly, a gray-level image is extracted from the original colored image. The image is then segmented into two regions, coin and background, based on the histogram drawn from the gray-level image. To reduce the noise, the segmented image is then cleaned by opening and closing through several erosion and dilation operations. After that, four parameters are calculated, the area, the average red, blue, and green colors of the coin to be recognized. Based on these parameters, the decision to which category the coin belongs is obtained. The results provided illustrate that the proposed approach is both simple and accurate. Although the proposed recognition approach is applied to Jordanian coins, it can be applied to the recognition of any coins.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116389783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612142
Tsang-Hung Wu, Shyh-Chang Liu
Due to the development of information technology, relevant business information of enterprise and government authority is stored in the computer by means of digital method. In addition, it relies on computer and network to maintain it operation. Due to the characteristics of network, person with intention to commit crime can conduct criminal behavior by linking with the network at any time and at any place. If there is no appropriate control on the information asset, information can be easily altered or deleted and even important information may be disclosed thereby generating serious loss. As the business of the finance industry includes the personal and transaction information of customer, therefore the requirement on information security has to be more stringent than other industry. Moreover, for the consideration on information security, generally this is conducted based on the angle of technology, but other factors are ignored. In fact, information security has three aspects including technology, management and policy. This thesis will provide suggestion on the overall information security protection on the information environment of the finance industry. Furthermore, study is conducted on the information regulation/industry standard and flow planning that can be used to provide an overall information security solution plan that is safe and efficient.
{"title":"A research on the establishment of an information security environment for the finance industry","authors":"Tsang-Hung Wu, Shyh-Chang Liu","doi":"10.1109/EIT.2010.5612142","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612142","url":null,"abstract":"Due to the development of information technology, relevant business information of enterprise and government authority is stored in the computer by means of digital method. In addition, it relies on computer and network to maintain it operation. Due to the characteristics of network, person with intention to commit crime can conduct criminal behavior by linking with the network at any time and at any place. If there is no appropriate control on the information asset, information can be easily altered or deleted and even important information may be disclosed thereby generating serious loss. As the business of the finance industry includes the personal and transaction information of customer, therefore the requirement on information security has to be more stringent than other industry. Moreover, for the consideration on information security, generally this is conducted based on the angle of technology, but other factors are ignored. In fact, information security has three aspects including technology, management and policy. This thesis will provide suggestion on the overall information security protection on the information environment of the finance industry. Furthermore, study is conducted on the information regulation/industry standard and flow planning that can be used to provide an overall information security solution plan that is safe and efficient.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128283743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612107
M. Padmini, K. Athre
Timetabling is a classic problem with practical applications. Based on the available literature on timetable generation, it is clear that the process of automation gives rise to difficulties while trying to incorporate all the constraints involved. The fast elegant simple heuristic proposed here is used for multi-campus university where the faculty belongs to a common teaching pool Administrative processes are adopted to overcome constraints at various levels of hierarchy. The timetable is generated in constant time. The heuristic finds application in various scheduling problems such as: flight scheduling, train scheduling etc.
{"title":"Efficient design of university timetable","authors":"M. Padmini, K. Athre","doi":"10.1109/EIT.2010.5612107","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612107","url":null,"abstract":"Timetabling is a classic problem with practical applications. Based on the available literature on timetable generation, it is clear that the process of automation gives rise to difficulties while trying to incorporate all the constraints involved. The fast elegant simple heuristic proposed here is used for multi-campus university where the faculty belongs to a common teaching pool Administrative processes are adopted to overcome constraints at various levels of hierarchy. The timetable is generated in constant time. The heuristic finds application in various scheduling problems such as: flight scheduling, train scheduling etc.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132653599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612100
Li Li, Wei Wang, K. Choi, Seongmo Park, Moo-Kyoung Chung
For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is introduced by a few advanced CAD vendors. In order to maximize the power reduction of the MMP design, we propose a novel selective sequential clock gating (SeSCG) technique in this paper. The SeSCG scheme can choose optimal sequential clock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level. We have tested the proposed technique on two real industrial MMP designs using 65 nanometer technology. The experimental results show that the conventional sequential clock gating scheme even increases average 4.77% of total power while the proposed SeSCG technique decreases average 23.71% total power with reasonably very small area overhead (no more than 0.63%) when we use real industrial testbenches for the two industrial MMP designs.
{"title":"SeSCG: Selective sequential clock gating for ultra-low-power multimedia mobile processor design","authors":"Li Li, Wei Wang, K. Choi, Seongmo Park, Moo-Kyoung Chung","doi":"10.1109/EIT.2010.5612100","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612100","url":null,"abstract":"For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is introduced by a few advanced CAD vendors. In order to maximize the power reduction of the MMP design, we propose a novel selective sequential clock gating (SeSCG) technique in this paper. The SeSCG scheme can choose optimal sequential clock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level. We have tested the proposed technique on two real industrial MMP designs using 65 nanometer technology. The experimental results show that the conventional sequential clock gating scheme even increases average 4.77% of total power while the proposed SeSCG technique decreases average 23.71% total power with reasonably very small area overhead (no more than 0.63%) when we use real industrial testbenches for the two industrial MMP designs.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612174
M. Andalibizadeh, M. T. Savadkouhi, B. Nasri
In this paper a temperature sensor in 65 nm technology is presented. All blocks are implementable on chips as it was the goal from the beginning to have a "Sensor on a Chip" as outcome of the design. The general block diagram of the system shows that it can be used for any other purpose by changing the sensing part and making it a linear one. The sensor assumed to be usable for a control system and the output of a system is Frequency! It works at frequency range of 26 GHz to 31 GHz which represents a resolution of 50 MHz/°C. The range for temperature is 100 °C to 190 °C. For sure this range can be improved by using other sorts of sensing parts than what is used for this research. The main part of the circuit is a VCO which consumes 17 mW at the highest frequency and a phase noise of −106.8 dBc/Hz at 1 MHz offset.
{"title":"A VCO in 65 nm technology for very accurate sensing applications","authors":"M. Andalibizadeh, M. T. Savadkouhi, B. Nasri","doi":"10.1109/EIT.2010.5612174","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612174","url":null,"abstract":"In this paper a temperature sensor in 65 nm technology is presented. All blocks are implementable on chips as it was the goal from the beginning to have a \"Sensor on a Chip\" as outcome of the design. The general block diagram of the system shows that it can be used for any other purpose by changing the sensing part and making it a linear one. The sensor assumed to be usable for a control system and the output of a system is Frequency! It works at frequency range of 26 GHz to 31 GHz which represents a resolution of 50 MHz/°C. The range for temperature is 100 °C to 190 °C. For sure this range can be improved by using other sorts of sensing parts than what is used for this research. The main part of the circuit is a VCO which consumes 17 mW at the highest frequency and a phase noise of −106.8 dBc/Hz at 1 MHz offset.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124775749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612138
Wei Wang, K. Choi
Unlike CMOS circuit design, even though there are promising advantages to use carbon nanotubes for digital circuits in terms of power, delay, temperature, and area, one of the critical issues to design by using carbon nanotubes is optimization of additional design parameters such as number of nanotubes and pitch size. To reduce the optimization complexity of the increased technology parameters, in this paper, we proposed a novel curve fitting design methodology for carbon-nanotube circuits. The proposed curve fitting methodology can guarantee from 90% to 100% correlation accuracy comparing with SPICE simulation and it can find optimal CNFET SRAM cell parameters without exhaustive simulation time and large memory space. The optimized CNFET SRAM cell by the proposed methodology shows that total power consumption including static power is reduced by 83.14% and the total PDP (product of delay and power) is reduced by 83.39%, comparing with CMOS SRAM cell design. The total runtime is reduced by 96.9% compared with conventional Monte Carlo simulation method in SPICE.
{"title":"Novel curve fitting design methodology for carbon nanotube SRAM cell optimization","authors":"Wei Wang, K. Choi","doi":"10.1109/EIT.2010.5612138","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612138","url":null,"abstract":"Unlike CMOS circuit design, even though there are promising advantages to use carbon nanotubes for digital circuits in terms of power, delay, temperature, and area, one of the critical issues to design by using carbon nanotubes is optimization of additional design parameters such as number of nanotubes and pitch size. To reduce the optimization complexity of the increased technology parameters, in this paper, we proposed a novel curve fitting design methodology for carbon-nanotube circuits. The proposed curve fitting methodology can guarantee from 90% to 100% correlation accuracy comparing with SPICE simulation and it can find optimal CNFET SRAM cell parameters without exhaustive simulation time and large memory space. The optimized CNFET SRAM cell by the proposed methodology shows that total power consumption including static power is reduced by 83.14% and the total PDP (product of delay and power) is reduced by 83.39%, comparing with CMOS SRAM cell design. The total runtime is reduced by 96.9% compared with conventional Monte Carlo simulation method in SPICE.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612104
L. Mapa, G. Aryal, K. Chanda
Radio Frequency Identification (RFID) technology is becoming increasingly popular in the area of supply chain management, to track and record shipments in retail and manufacturing industries. This paper focuses on the readability of RFID tags in the presence of various nanofluids at different concentrations on a conveyor belt which is a typical packaging environment. Several variables tested in this experiment were different types of nanofluids at several concentrations, different speeds of the conveyor. Antenna type, and the distance of the tag from the antenna were kept constant throughout the experiment. The data was analyzed using nested factorial design to examine the significance of the main factors.
{"title":"Effect of nanofluids on the readability of RFID tags","authors":"L. Mapa, G. Aryal, K. Chanda","doi":"10.1109/EIT.2010.5612104","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612104","url":null,"abstract":"Radio Frequency Identification (RFID) technology is becoming increasingly popular in the area of supply chain management, to track and record shipments in retail and manufacturing industries. This paper focuses on the readability of RFID tags in the presence of various nanofluids at different concentrations on a conveyor belt which is a typical packaging environment. Several variables tested in this experiment were different types of nanofluids at several concentrations, different speeds of the conveyor. Antenna type, and the distance of the tag from the antenna were kept constant throughout the experiment. The data was analyzed using nested factorial design to examine the significance of the main factors.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124222555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-20DOI: 10.1109/EIT.2010.5612165
R. Klump
This presentation will describe the ways in which data is kept secret, verified to have come from a particular origin, and protected from unwanted modification while in transit. Such technology, which belongs to a field called Encryption and Authentication Systems, is very important to understand if you are an engineer or manager considering how to protect measurement and control data on the emerging smart electrical grid. This talk will explain symmetric and asymmetric cryptosystems and then explain how they are and may be applied to electric power applications.
{"title":"Data security fundamentals for power systems personnel","authors":"R. Klump","doi":"10.1109/EIT.2010.5612165","DOIUrl":"https://doi.org/10.1109/EIT.2010.5612165","url":null,"abstract":"This presentation will describe the ways in which data is kept secret, verified to have come from a particular origin, and protected from unwanted modification while in transit. Such technology, which belongs to a field called Encryption and Authentication Systems, is very important to understand if you are an engineer or manager considering how to protect measurement and control data on the emerging smart electrical grid. This talk will explain symmetric and asymmetric cryptosystems and then explain how they are and may be applied to electric power applications.","PeriodicalId":305049,"journal":{"name":"2010 IEEE International Conference on Electro/Information Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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