Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704042
Mervat M. A. Mahmoud, D. El-Dib, H. Fahmy
A simple low energy new lossless compression/decompression approach is suggested for main memory data for exact storage of critical applications that need precise outputs. The proposed design lowers energy consumption by up to 66% when compared to previous designs. This is due to its simplicity and low latency. Furthermore, the frequency of operation is increased from 300MHz to 800MHz. The new design also allows the main memory to store up to 30% more data according to PARSEC and PERFECT benchmarks applications data.
{"title":"Low Energy ASIC Design for Main Memory Data Compression/Decompression","authors":"Mervat M. A. Mahmoud, D. El-Dib, H. Fahmy","doi":"10.1109/ICM.2018.8704042","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704042","url":null,"abstract":"A simple low energy new lossless compression/decompression approach is suggested for main memory data for exact storage of critical applications that need precise outputs. The proposed design lowers energy consumption by up to 66% when compared to previous designs. This is due to its simplicity and low latency. Furthermore, the frequency of operation is increased from 300MHz to 800MHz. The new design also allows the main memory to store up to 30% more data according to PARSEC and PERFECT benchmarks applications data.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704113
Leandro M Ribeiro, T. Pimenta
In order to minimize electromagnetic interferences in Electroencephalogram - EEG, we are developing an integrated circuit containing the amplifier, filter and AD converter to be placed directly over the electrodes, thus obtaining active electrodes. The active electrodes are connected to a hub that sends the data to the external equipment. Since the amplification and filtering should be programmable according to the patient and environment, the communication between the active electrodes and the external equipment (via hub) must be bidirectional. This paper describes the hub and its communication to the active electrodes using the I2C Protocol. The project was developed using the Verilog and tested on boards that emulated the hub and the active electrodes. The tests demonstrated the circuits work as expected.
{"title":"The Implementation of Communication Hub for EEG Active Electrodes","authors":"Leandro M Ribeiro, T. Pimenta","doi":"10.1109/ICM.2018.8704113","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704113","url":null,"abstract":"In order to minimize electromagnetic interferences in Electroencephalogram - EEG, we are developing an integrated circuit containing the amplifier, filter and AD converter to be placed directly over the electrodes, thus obtaining active electrodes. The active electrodes are connected to a hub that sends the data to the external equipment. Since the amplification and filtering should be programmable according to the patient and environment, the communication between the active electrodes and the external equipment (via hub) must be bidirectional. This paper describes the hub and its communication to the active electrodes using the I2C Protocol. The project was developed using the Verilog and tested on boards that emulated the hub and the active electrodes. The tests demonstrated the circuits work as expected.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129020327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704057
Hossam Hassan, Hyungwon Kim, S. Ibrahim
In this paper we propose a configurable CMOS capacitive fingerprint that has two configuration modes for charge detection in each cell pixel. The readout circuit can be configured to operate with/without analog-to-digital converter (ADC). One of the configuration modes utilize in-cell pixel comparator which provides an instant decision of the finger features (Ridge = 1 or Valley = 0). While, the other one uses a programmable gain amplifier (PGA) to provide the detected signal to an ADC. The simulation results show the difference between the output of both configurations.
{"title":"Design of Configurable CMOS Capacitive Fingerprint","authors":"Hossam Hassan, Hyungwon Kim, S. Ibrahim","doi":"10.1109/ICM.2018.8704057","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704057","url":null,"abstract":"In this paper we propose a configurable CMOS capacitive fingerprint that has two configuration modes for charge detection in each cell pixel. The readout circuit can be configured to operate with/without analog-to-digital converter (ADC). One of the configuration modes utilize in-cell pixel comparator which provides an instant decision of the finger features (Ridge = 1 or Valley = 0). While, the other one uses a programmable gain amplifier (PGA) to provide the detected signal to an ADC. The simulation results show the difference between the output of both configurations.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116639141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704019
Abdulaziz H. Elsafty, M. Tolba, L. Said, A. Madian, A. Radwan
This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed. Entropy, MSE, correlation coefficient tests are applied on two different input files to examine the efficiency of this cryptosystem.
{"title":"FPGA Speech Encryption Realization Based on Variable S-Box and Memristor Chaotic Circuit","authors":"Abdulaziz H. Elsafty, M. Tolba, L. Said, A. Madian, A. Radwan","doi":"10.1109/ICM.2018.8704019","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704019","url":null,"abstract":"This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed. Entropy, MSE, correlation coefficient tests are applied on two different input files to examine the efficiency of this cryptosystem.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127721891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704068
Sirine Mnejja, Y. Aydi, M. Abid
Since the number of cores incorporated on the same multicore chip increases, the main important challenge for System-on-Chip (SoC) systems is the interconnection between their components. Thus, to deal with the problem of communication that became the bottleneck of conventional NoC, wireless Networks on Chip (WiNoCs) have recently been proposed for Multiprocessor systems on chip (MP-SoCs) interconnection. This paper proposed a mesh based Hybrid architecture Network-on-Chip (NoC), which wired dual support and wireless communications. The whole architecture has been implemented and integrated over Noxim platform. A performance evaluation of this model has been illustrated to analyze the dynamic behavior of the Network.
{"title":"Exploring Hybrid NoC Architecture for Chip Multiprocessor","authors":"Sirine Mnejja, Y. Aydi, M. Abid","doi":"10.1109/ICM.2018.8704068","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704068","url":null,"abstract":"Since the number of cores incorporated on the same multicore chip increases, the main important challenge for System-on-Chip (SoC) systems is the interconnection between their components. Thus, to deal with the problem of communication that became the bottleneck of conventional NoC, wireless Networks on Chip (WiNoCs) have recently been proposed for Multiprocessor systems on chip (MP-SoCs) interconnection. This paper proposed a mesh based Hybrid architecture Network-on-Chip (NoC), which wired dual support and wireless communications. The whole architecture has been implemented and integrated over Noxim platform. A performance evaluation of this model has been illustrated to analyze the dynamic behavior of the Network.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133590109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704058
Alfonso Rodríguez, Tiziana Fanni
Cyber-Physical Systems (CPS) operate in increasingly complex and demanding application scenarios, while requiring also high adaptivity levels to satisfy several requirements that usually change over time. Multi-grain reconfigurable hardware architectures are an appealing solution to provide high, heterogeneous flexibility, thus reaching the advanced runtime adaptivity support necessary for CPS. This work presents a demonstration of an automated framework for the development and runtime management of multi-grain reconfigurable hardware systems. The framework supports different reconfiguration mechanisms, each with different overheads and depth in terms of system behavior modification.
{"title":"DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems","authors":"Alfonso Rodríguez, Tiziana Fanni","doi":"10.1109/ICM.2018.8704058","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704058","url":null,"abstract":"Cyber-Physical Systems (CPS) operate in increasingly complex and demanding application scenarios, while requiring also high adaptivity levels to satisfy several requirements that usually change over time. Multi-grain reconfigurable hardware architectures are an appealing solution to provide high, heterogeneous flexibility, thus reaching the advanced runtime adaptivity support necessary for CPS. This work presents a demonstration of an automated framework for the development and runtime management of multi-grain reconfigurable hardware systems. The framework supports different reconfiguration mechanisms, each with different overheads and depth in terms of system behavior modification.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114837675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8703995
A. Abougarair, Abdulhamid Oun, A. Emhemmed
Active suspension system poses the ability to reduce the traditional design as a compromise between handling and comfort by directly controlling the suspensions force actuators. This paper presents a linear model and control of a quarter-car active suspension system with unknown mass and road disturbance. The controller is designed to derive a control law and that achieves stability of the system and convergence that can considerably improve ride comfort and road disturbance handling. PD, Fuzzy PD, and Adaptive PD in order to use in active vibration control simulations. The designed controllers efficiency are examined using Matlab simulation. Finally, the designed controllers suitability are studied by comparing their performances in case of using different road profile functions.
{"title":"Intelligent Control Design for Linear Model of Active Suspension System","authors":"A. Abougarair, Abdulhamid Oun, A. Emhemmed","doi":"10.1109/ICM.2018.8703995","DOIUrl":"https://doi.org/10.1109/ICM.2018.8703995","url":null,"abstract":"Active suspension system poses the ability to reduce the traditional design as a compromise between handling and comfort by directly controlling the suspensions force actuators. This paper presents a linear model and control of a quarter-car active suspension system with unknown mass and road disturbance. The controller is designed to derive a control law and that achieves stability of the system and convergence that can considerably improve ride comfort and road disturbance handling. PD, Fuzzy PD, and Adaptive PD in order to use in active vibration control simulations. The designed controllers efficiency are examined using Matlab simulation. Finally, the designed controllers suitability are studied by comparing their performances in case of using different road profile functions.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704050
Hossam Hassan, Hyungwon Kim, S. Ibrahim
This paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.
{"title":"Design and Investigation of Configurable Source Coupled Logic","authors":"Hossam Hassan, Hyungwon Kim, S. Ibrahim","doi":"10.1109/ICM.2018.8704050","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704050","url":null,"abstract":"This paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123343363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704010
N. Soliman, M. Fouda, L. Said, A. Madian, A. Radwan
This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit.
{"title":"Memristor-CNTFET based Ternary Comparator unit","authors":"N. Soliman, M. Fouda, L. Said, A. Madian, A. Radwan","doi":"10.1109/ICM.2018.8704010","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704010","url":null,"abstract":"This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124910654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704118
M. Kanoun, B. Jadav, D. Cordeau, J. Paillot, H. Mnif, M. Loulou
This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz in a 0.25 µm BiCMOS SiGe:C process. The proposed circuit is able to provide a 360° continuous phase shift range, allowing to control the radiation pattern of a phased antenna array. The required phase shift is synthesized using an Injection-Locked Oscillator (ILO) for fine tuning followed by an in-phase/quadrature (IQ) modulator for coarse tuning. The total current consumption of the circuit is 33.7 mA from a 2.5 V supply voltage. The core size including all the pads is 1.324*1.086mm2.
{"title":"A Fully Integrated 5.8 GHz BiCMOS SiGe:C tunable active phase shifter for Beamforming","authors":"M. Kanoun, B. Jadav, D. Cordeau, J. Paillot, H. Mnif, M. Loulou","doi":"10.1109/ICM.2018.8704118","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704118","url":null,"abstract":"This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz in a 0.25 µm BiCMOS SiGe:C process. The proposed circuit is able to provide a 360° continuous phase shift range, allowing to control the radiation pattern of a phased antenna array. The required phase shift is synthesized using an Injection-Locked Oscillator (ILO) for fine tuning followed by an in-phase/quadrature (IQ) modulator for coarse tuning. The total current consumption of the circuit is 33.7 mA from a 2.5 V supply voltage. The core size including all the pads is 1.324*1.086mm2.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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