Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704118
M. Kanoun, B. Jadav, D. Cordeau, J. Paillot, H. Mnif, M. Loulou
This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz in a 0.25 µm BiCMOS SiGe:C process. The proposed circuit is able to provide a 360° continuous phase shift range, allowing to control the radiation pattern of a phased antenna array. The required phase shift is synthesized using an Injection-Locked Oscillator (ILO) for fine tuning followed by an in-phase/quadrature (IQ) modulator for coarse tuning. The total current consumption of the circuit is 33.7 mA from a 2.5 V supply voltage. The core size including all the pads is 1.324*1.086mm2.
{"title":"A Fully Integrated 5.8 GHz BiCMOS SiGe:C tunable active phase shifter for Beamforming","authors":"M. Kanoun, B. Jadav, D. Cordeau, J. Paillot, H. Mnif, M. Loulou","doi":"10.1109/ICM.2018.8704118","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704118","url":null,"abstract":"This paper presents the design and the implementation of a fully integrated active phase shifter for beamforming at 5.8 GHz in a 0.25 µm BiCMOS SiGe:C process. The proposed circuit is able to provide a 360° continuous phase shift range, allowing to control the radiation pattern of a phased antenna array. The required phase shift is synthesized using an Injection-Locked Oscillator (ILO) for fine tuning followed by an in-phase/quadrature (IQ) modulator for coarse tuning. The total current consumption of the circuit is 33.7 mA from a 2.5 V supply voltage. The core size including all the pads is 1.324*1.086mm2.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704119
Hussein Bazzi, A. Harb, H. Aziza, M. Moreau
Static Random-Access Memories (SRAMs) are very common in today’s chips industry thanks to their speed and power consumption but they are classified as volatile memory. Non-Volatile SRAMs (NVSRAMs) combine SRAM features with non-volatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. This paper presents a detailed overview on Resistive RAM-based NVSRAM structures, with deep looking on the ability to store and restore data. After reviewing the designs, a comparison in terms of speed, power consumption and design complexity is presented for 2 NVSRAM memory cells (6T2R and a 10T1R) implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.
{"title":"Design of Hybrid CMOS Non-Volatile SRAM Cells in 130nm RRAM Technology","authors":"Hussein Bazzi, A. Harb, H. Aziza, M. Moreau","doi":"10.1109/ICM.2018.8704119","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704119","url":null,"abstract":"Static Random-Access Memories (SRAMs) are very common in today’s chips industry thanks to their speed and power consumption but they are classified as volatile memory. Non-Volatile SRAMs (NVSRAMs) combine SRAM features with non-volatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. This paper presents a detailed overview on Resistive RAM-based NVSRAM structures, with deep looking on the ability to store and restore data. After reviewing the designs, a comparison in terms of speed, power consumption and design complexity is presented for 2 NVSRAM memory cells (6T2R and a 10T1R) implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704050
Hossam Hassan, Hyungwon Kim, S. Ibrahim
This paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.
{"title":"Design and Investigation of Configurable Source Coupled Logic","authors":"Hossam Hassan, Hyungwon Kim, S. Ibrahim","doi":"10.1109/ICM.2018.8704050","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704050","url":null,"abstract":"This paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123343363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704106
Radhoine Aloui, Z. Houaneb, H. Zairi
The compact size of two-port substrate integrate waveguide three-dimensional (SIW 3-D) cavity resonator designed with a half mode (HM) for Ku-band application have been simulated. The microwave circuits we find the resonator, filter, antenna, and coupler the can be designed by using SIW techniques. firstly started to model a new circuit structure such as the 3-D resonator cavity. The electromagnetic simulation with the CST-studio software shows a 28.9 GHz resonance frequency. Furthermore, the modulation resulted in lowering the cost and the miniaturization of the dimension of the circuit by 75% cut Finally, the variation of the substrate's nature at the level of folding which is characterized by a permittivity εr different from that of the circuit substrate, after obtaining the different results, the conclude that the lower the dielectric permittivity (εr) is, the higher S11 and S12 (the reflection and transmission coefficient respectively) value is.
{"title":"Modeling a Ka-Band Resonator Cavity with SIW 3-D Technology","authors":"Radhoine Aloui, Z. Houaneb, H. Zairi","doi":"10.1109/ICM.2018.8704106","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704106","url":null,"abstract":"The compact size of two-port substrate integrate waveguide three-dimensional (SIW 3-D) cavity resonator designed with a half mode (HM) for Ku-band application have been simulated. The microwave circuits we find the resonator, filter, antenna, and coupler the can be designed by using SIW techniques. firstly started to model a new circuit structure such as the 3-D resonator cavity. The electromagnetic simulation with the CST-studio software shows a 28.9 GHz resonance frequency. Furthermore, the modulation resulted in lowering the cost and the miniaturization of the dimension of the circuit by 75% cut Finally, the variation of the substrate's nature at the level of folding which is characterized by a permittivity εr different from that of the circuit substrate, after obtaining the different results, the conclude that the lower the dielectric permittivity (εr) is, the higher S11 and S12 (the reflection and transmission coefficient respectively) value is.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128309068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704059
S. Khediri, Adel Thaljaoui, A. Dallali, A. Kachouri
The clustering technique is a kind of key method used to balance energy consumption in wireless sensor networks. It can increase the lifetime of the network and scalability. Energy-efficient clustering algorithms should be designed for the characteristic of homogeneous WSN. We propose and evaluate a new centralized energy-efficient clustering protocol for homogenous WSNs, which is called Distance energy evaluated DEE. In DEE, the cluster-heads (CHs), are elected by a probability based on the ratio between distance and residual energy of each node. The probability of being CH according to their initial and residual energy. Finally, the simulation results seemed that DEE achieves more effective messages and longer lifetime than current important clustering protocols in homogeneous environments.
{"title":"Clustering Algorithm in wireless sensor networks based on shortest path","authors":"S. Khediri, Adel Thaljaoui, A. Dallali, A. Kachouri","doi":"10.1109/ICM.2018.8704059","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704059","url":null,"abstract":"The clustering technique is a kind of key method used to balance energy consumption in wireless sensor networks. It can increase the lifetime of the network and scalability. Energy-efficient clustering algorithms should be designed for the characteristic of homogeneous WSN. We propose and evaluate a new centralized energy-efficient clustering protocol for homogenous WSNs, which is called Distance energy evaluated DEE. In DEE, the cluster-heads (CHs), are elected by a probability based on the ratio between distance and residual energy of each node. The probability of being CH according to their initial and residual energy. Finally, the simulation results seemed that DEE achieves more effective messages and longer lifetime than current important clustering protocols in homogeneous environments.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704066
Abeer Y. Al-Hyari, Ziad Abuowaimer, Dani Maarouf, S. Areibi, G. Grewal
One of the most time consuming steps in the FPGA CAD flow is the placement problem which directly impacts the completion of the design flow. Accordingly, a routability driven FPGA placement contest was organized by Xilinx in ISPD 2016 to address this problem. Due to variations in the ISPD benchmark characteristics and heterogeneity of the FPGA architectures, as well as the different optimization strategies employed by different participating placers, placement algorithms that performed well on some circuits performed poorly on others. In this paper we propose a Machine-Learning (ML) framework that is capable of recommending the best FPGA placement algorithm within the CAD flow. Results obtained indicate that the ML framework is capable of selecting the correct flow with an 83% accuracy.
{"title":"An Effective FPGA Placement Flow Selection Framework using Machine Learning","authors":"Abeer Y. Al-Hyari, Ziad Abuowaimer, Dani Maarouf, S. Areibi, G. Grewal","doi":"10.1109/ICM.2018.8704066","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704066","url":null,"abstract":"One of the most time consuming steps in the FPGA CAD flow is the placement problem which directly impacts the completion of the design flow. Accordingly, a routability driven FPGA placement contest was organized by Xilinx in ISPD 2016 to address this problem. Due to variations in the ISPD benchmark characteristics and heterogeneity of the FPGA architectures, as well as the different optimization strategies employed by different participating placers, placement algorithms that performed well on some circuits performed poorly on others. In this paper we propose a Machine-Learning (ML) framework that is capable of recommending the best FPGA placement algorithm within the CAD flow. Results obtained indicate that the ML framework is capable of selecting the correct flow with an 83% accuracy.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"2019 30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130941713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704010
N. Soliman, M. Fouda, L. Said, A. Madian, A. Radwan
This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit.
{"title":"Memristor-CNTFET based Ternary Comparator unit","authors":"N. Soliman, M. Fouda, L. Said, A. Madian, A. Radwan","doi":"10.1109/ICM.2018.8704010","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704010","url":null,"abstract":"This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124910654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704105
A. Kouhoul, Y. Karmous, Naim Benhamida, S. Aouini, Tahar Haddad, Larbi Talbi
Verification of high-precision nanometer analog and mixed-signal circuits has become very challenging because traditional Analog simulators do not have the capacity required to support the circuit complexity. As a result, they are not suitable for large analog, mixed-signal, and digital circuits as the run time is too long. To overcome this limitation and address the need of speed and accuracy behavioral models are developed. This article explains the development and implementation of a new digital environment to run analog and mixed signal systems. The proposed environment was tested to verify a 400Gbit/s coherent optical modem.
{"title":"Framework for Developping Behavioural Models From Physical Designs","authors":"A. Kouhoul, Y. Karmous, Naim Benhamida, S. Aouini, Tahar Haddad, Larbi Talbi","doi":"10.1109/ICM.2018.8704105","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704105","url":null,"abstract":"Verification of high-precision nanometer analog and mixed-signal circuits has become very challenging because traditional Analog simulators do not have the capacity required to support the circuit complexity. As a result, they are not suitable for large analog, mixed-signal, and digital circuits as the run time is too long. To overcome this limitation and address the need of speed and accuracy behavioral models are developed. This article explains the development and implementation of a new digital environment to run analog and mixed signal systems. The proposed environment was tested to verify a 400Gbit/s coherent optical modem.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128118088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8703879
EF Maalouf, N. Marina, J. B. Abdo, Alain Aoun, M. Hamad, A. Kassem
This paper describes a prototype for asthma irritant monitoring system (AIM) that can be used by asthma patients. The AIM is a compact device that senses the environment around the patient for different irritants in order to detect any signs of asthma attacks or potentially unhealthy environments. Hence, asthma patients are able to know whether the environment around them is healthy or not, allowing them to take appropriate action. In addition, the device offers the capability of sending the data to the physician to follow the patient case and a display indicating the environment condition around the patients. Furthermore, the AIM displays data reordered in the daily tests, allowing the patient and the physician to check the progress from previous days. Finally, the AIM device is aligned with the medical requirements as per physicians’ and telemedicine specialists’ recommendations; the experiments carried out on asthma patients demonstrated the effectiveness and sustainable use of the AIM device.
{"title":"Asthma Irritant Monitoring","authors":"EF Maalouf, N. Marina, J. B. Abdo, Alain Aoun, M. Hamad, A. Kassem","doi":"10.1109/ICM.2018.8703879","DOIUrl":"https://doi.org/10.1109/ICM.2018.8703879","url":null,"abstract":"This paper describes a prototype for asthma irritant monitoring system (AIM) that can be used by asthma patients. The AIM is a compact device that senses the environment around the patient for different irritants in order to detect any signs of asthma attacks or potentially unhealthy environments. Hence, asthma patients are able to know whether the environment around them is healthy or not, allowing them to take appropriate action. In addition, the device offers the capability of sending the data to the physician to follow the patient case and a display indicating the environment condition around the patients. Furthermore, the AIM displays data reordered in the daily tests, allowing the patient and the physician to check the progress from previous days. Finally, the AIM device is aligned with the medical requirements as per physicians’ and telemedicine specialists’ recommendations; the experiments carried out on asthma patients demonstrated the effectiveness and sustainable use of the AIM device.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127550003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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