Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704037
Esraa M. Hamed, K. Salah, A. Madian, A. Radwan
In this paper, an automated universal verification methodology (UVM) tool for rapid functional verification is presented. Now, UVM dominates the verification process but, it is very hard and too complicated to learn. This paper introduces a lightweight UVM tool which allows the user to rapidly verify complex RTL designs and different IPs. Also, it allows the user to perform the simulation for any design under test (DUT). The proposed tool generates the suitable UVM architecture to the DUT with the needed codes. Moreover, it provides the user with statistics about the number of the used classes and methods. Different UVM architectures with different UVM environments are proposed such as the single layer, multilayers, multi-masters multi-slaves and generic UVM architecture. Finally, the tool is tested with automotive IPs and the results show that the tool is very robust and reliable.
{"title":"An Automated Lightweight UVM Tool","authors":"Esraa M. Hamed, K. Salah, A. Madian, A. Radwan","doi":"10.1109/ICM.2018.8704037","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704037","url":null,"abstract":"In this paper, an automated universal verification methodology (UVM) tool for rapid functional verification is presented. Now, UVM dominates the verification process but, it is very hard and too complicated to learn. This paper introduces a lightweight UVM tool which allows the user to rapidly verify complex RTL designs and different IPs. Also, it allows the user to perform the simulation for any design under test (DUT). The proposed tool generates the suitable UVM architecture to the DUT with the needed codes. Moreover, it provides the user with statistics about the number of the used classes and methods. Different UVM architectures with different UVM environments are proposed such as the single layer, multilayers, multi-masters multi-slaves and generic UVM architecture. Finally, the tool is tested with automotive IPs and the results show that the tool is very robust and reliable.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704089
N. Abid, T. Ouni, K. Loukil, M. Abid, A. Ammeri
Local Binary Pattern multi-scale covariance descriptor (LBP_MSCOV) has been proved to be robust for video surveillance applications such as person detection, tracking and re-identification. Matching technique has recently grown in interest. It can be used to design person detection, tracking and re-identification. However, the original version is difficult to execute in real time. It requires a large data set and complex operations. Parallel implementation is adopted to achieve real time constraints. In this paper, we propose an optimized parallel model of a person matching algorithm based on LBP_MSCOV. For this end, a high-level parallelization approach based on the exploration of task and data levels of parallelism is adopted. First, an initial model is defined using only task-level parallelism. Second, this model is validated and analyzed at a high level of abstraction. Using the communication and computation workload results, the potential bottlenecks of this model are then identified. Concurrent optimizations are then performed to propose an optimized parallel model with the best workload balance. Finally, this model is validated and prototyped using a dual-core ARM-Cortex-A9architecture achieving up to 20.21 fps processing performance.
{"title":"Parallel Implementation for Real Time Person Matching System","authors":"N. Abid, T. Ouni, K. Loukil, M. Abid, A. Ammeri","doi":"10.1109/ICM.2018.8704089","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704089","url":null,"abstract":"Local Binary Pattern multi-scale covariance descriptor (LBP_MSCOV) has been proved to be robust for video surveillance applications such as person detection, tracking and re-identification. Matching technique has recently grown in interest. It can be used to design person detection, tracking and re-identification. However, the original version is difficult to execute in real time. It requires a large data set and complex operations. Parallel implementation is adopted to achieve real time constraints. In this paper, we propose an optimized parallel model of a person matching algorithm based on LBP_MSCOV. For this end, a high-level parallelization approach based on the exploration of task and data levels of parallelism is adopted. First, an initial model is defined using only task-level parallelism. Second, this model is validated and analyzed at a high level of abstraction. Using the communication and computation workload results, the potential bottlenecks of this model are then identified. Concurrent optimizations are then performed to propose an optimized parallel model with the best workload balance. Finally, this model is validated and prototyped using a dual-core ARM-Cortex-A9architecture achieving up to 20.21 fps processing performance.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132147499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704075
Imtinan B. Attili, S. Mahmoud
This paper provides a comparison between three OTA designs that enhance the performance of the conventional current mirror OTA through shunting current from the main differential pair. In the examined circuits, current shunting is achieved through; constant biased current source transistors in the first design, adaptive biased current shunt transistors through an additional differential pair in the second design, and by a new proposed design that combines the first two techniques together in the third design. The performance of the three designs are tested and optimized on LTspice using 90nm CMOS technology while maintaining stability with a phase margin ≥ 60°. Another major factor examined in this paper is the robustness of the designs against process variations. To test this, all width and length for all transistors were varied by a ±5% using two different tests.
{"title":"Examining the Performance of Low Power – Area Efficient OTA Designs that are Based on Different Current Shunting Techniques","authors":"Imtinan B. Attili, S. Mahmoud","doi":"10.1109/ICM.2018.8704075","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704075","url":null,"abstract":"This paper provides a comparison between three OTA designs that enhance the performance of the conventional current mirror OTA through shunting current from the main differential pair. In the examined circuits, current shunting is achieved through; constant biased current source transistors in the first design, adaptive biased current shunt transistors through an additional differential pair in the second design, and by a new proposed design that combines the first two techniques together in the third design. The performance of the three designs are tested and optimized on LTspice using 90nm CMOS technology while maintaining stability with a phase margin ≥ 60°. Another major factor examined in this paper is the robustness of the designs against process variations. To test this, all width and length for all transistors were varied by a ±5% using two different tests.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125880325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704111
Y. Halawani, B. Mohammad, M. Al-Qutayri, S. Al-Sarawi
The memristor-based array architecture promises an efficient analog implementation of the multiply-add engine that can have significant impact in signal processing and neural network implementations. The ability to represent a negative conductance value to correspond to a negative matrix element is one of the main challenges associated with analog memristor array implementation. In this paper, a re-configurable general purpose single array architecture is proposed to realize a multiply-add operation that allows both positive and negative conductance values. The architecture utilizes memristor devices with two different characteristics, one for computation and one for storage. The proposed design has been verified using LTSpice circuit simulator. Several cases with different combinations of polarities for the input voltage and conductance values were demonstrated.
{"title":"A Re-configurable Memristor Array Structure for In-Memory Computing Applications","authors":"Y. Halawani, B. Mohammad, M. Al-Qutayri, S. Al-Sarawi","doi":"10.1109/ICM.2018.8704111","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704111","url":null,"abstract":"The memristor-based array architecture promises an efficient analog implementation of the multiply-add engine that can have significant impact in signal processing and neural network implementations. The ability to represent a negative conductance value to correspond to a negative matrix element is one of the main challenges associated with analog memristor array implementation. In this paper, a re-configurable general purpose single array architecture is proposed to realize a multiply-add operation that allows both positive and negative conductance values. The architecture utilizes memristor devices with two different characteristics, one for computation and one for storage. The proposed design has been verified using LTSpice circuit simulator. Several cases with different combinations of polarities for the input voltage and conductance values were demonstrated.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704103
Nesrine Jaziri, Ayda Boughamoura-Ben Messaoud, Fares Tounsi, B. Mezghani, J. Muller
This paper presents numerical and analytic studies of a reported thermoelectric micro-generator based on LTCC (Low Temperature Co-fired Ceramic) technology. These types of devices are mainly used in energy harvesting applications by converting the waste thermal energy into electrical one. The aim of the performed analysis is to carry out analytical and numerical studies to investigate the electrical output parameters (internal resistance, output voltage and power) of a fabricated thermopile and multilayer generator. As mentioned in the published paper, the first structure of the thermopile contains 30 thick-film silver/Nickel thermocouples connected electrically in series and thermally in parallel on a single LTCC layer whereas the second structure contains 90 thermocouples screen-printed on three LTCC layers. The obtained numerical and analytical results show an average value of error compared to experimental ones of 11% and 16%, respectively. This good agreement with respect to experimental reported data shows that the derived and used FEM model is validated.
{"title":"Analytical and Numerical Analysis and Validation of an LTCC-based Fabricated TEG","authors":"Nesrine Jaziri, Ayda Boughamoura-Ben Messaoud, Fares Tounsi, B. Mezghani, J. Muller","doi":"10.1109/ICM.2018.8704103","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704103","url":null,"abstract":"This paper presents numerical and analytic studies of a reported thermoelectric micro-generator based on LTCC (Low Temperature Co-fired Ceramic) technology. These types of devices are mainly used in energy harvesting applications by converting the waste thermal energy into electrical one. The aim of the performed analysis is to carry out analytical and numerical studies to investigate the electrical output parameters (internal resistance, output voltage and power) of a fabricated thermopile and multilayer generator. As mentioned in the published paper, the first structure of the thermopile contains 30 thick-film silver/Nickel thermocouples connected electrically in series and thermally in parallel on a single LTCC layer whereas the second structure contains 90 thermocouples screen-printed on three LTCC layers. The obtained numerical and analytical results show an average value of error compared to experimental ones of 11% and 16%, respectively. This good agreement with respect to experimental reported data shows that the derived and used FEM model is validated.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704064
S. Lahiani, S. B. Salem, M. Loulou
This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA) that employs two transconductance amplifier and transimpedance amplifiers. The gain can be changed by used a digital control block, an auxiliary pair to retain a constant current density and offers a gain-independent bandwidth (BW). The proposed circuit has been presented to demonstrate the performance enhancement with the use of only one VGA stage for Worldwide Interoperability for Microwave Access (WiMAX) and Long Time Evolution (LTE) standards. The variable gain amplifier is designed for high gain, high bandwidth, low power consumption and low Noise Figure (NF). This circuit is implemented and simulated using device-level description of TSMC 0.18 u.m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 43 dB (from 27 to -16 dB) with a 3 dB bandwidth over more than 166 MHz. The designed VGA circuit acquires a Noise Figure (NF) less than 19 dB, an Input Referred Noise (TRN) of around 4.2 nV2/Hz and the Third Order Intercept Point measured at the Input (DZP3) of 8 dBm. The circuit consumes the maximum power 0.3 mW from a 1.8 V supply.
{"title":"Low Power CMOS Digital Variable Gain Amplifier Design For WiMAX/LTE Receiver","authors":"S. Lahiani, S. B. Salem, M. Loulou","doi":"10.1109/ICM.2018.8704064","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704064","url":null,"abstract":"This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA) that employs two transconductance amplifier and transimpedance amplifiers. The gain can be changed by used a digital control block, an auxiliary pair to retain a constant current density and offers a gain-independent bandwidth (BW). The proposed circuit has been presented to demonstrate the performance enhancement with the use of only one VGA stage for Worldwide Interoperability for Microwave Access (WiMAX) and Long Time Evolution (LTE) standards. The variable gain amplifier is designed for high gain, high bandwidth, low power consumption and low Noise Figure (NF). This circuit is implemented and simulated using device-level description of TSMC 0.18 u.m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 43 dB (from 27 to -16 dB) with a 3 dB bandwidth over more than 166 MHz. The designed VGA circuit acquires a Noise Figure (NF) less than 19 dB, an Input Referred Noise (TRN) of around 4.2 nV2/Hz and the Third Order Intercept Point measured at the Input (DZP3) of 8 dBm. The circuit consumes the maximum power 0.3 mW from a 1.8 V supply.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125554790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704046
Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, K. Besbes
An AD-PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) is proposed to attain a wide range of operation and a phase error monitor to reduce the process lock. To cover a wide range of frequency with improved spectral purity, two digitally controlled oscillators are proposed. An LC-tank oscillator with a tunable active inductor is used to reach the on-GHz band with a fine tuning resolution, while the sub-GHz is covered by an interpolated ring DCO. The proposed ADPLL is designed using a 90 nm TSMC CMOS process. The operational frequency range of the proposed circuit varies from 140 MHz to 3.52 GHz. The ADPLL achieves a fast settling time of less than 5 μs. By consuming 13.4 mW, the frequency synthesizer achieves -105 dBc/Hz far-off phase noise and -55 dBc fractional spur.
{"title":"A 0.14-3.5 GHz All Digital PLL with improved fast frequency-lock and a novel TDC-based self-calibration capability","authors":"Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi, K. Besbes","doi":"10.1109/ICM.2018.8704046","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704046","url":null,"abstract":"An AD-PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) is proposed to attain a wide range of operation and a phase error monitor to reduce the process lock. To cover a wide range of frequency with improved spectral purity, two digitally controlled oscillators are proposed. An LC-tank oscillator with a tunable active inductor is used to reach the on-GHz band with a fine tuning resolution, while the sub-GHz is covered by an interpolated ring DCO. The proposed ADPLL is designed using a 90 nm TSMC CMOS process. The operational frequency range of the proposed circuit varies from 140 MHz to 3.52 GHz. The ADPLL achieves a fast settling time of less than 5 μs. By consuming 13.4 mW, the frequency synthesizer achieves -105 dBc/Hz far-off phase noise and -55 dBc fractional spur.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"50 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/ICM.2018.8704017
W. Filali, S. Oussalah, N. Sengouga, M. Henini, David Taylor
This paper presents a systematic simulation approach for analyzing a p-type Ti/Au/Al0.29Ga0.71 As Schottky diode with traps. The traps parameters are extracted by DLTS (Deep Level Transient Spectroscopy) technique. Simulation was carried out using Atlas-SILVACO TCAD 2D simulator. The simulation is performed using the appropriate physical models to explain the behavior of the physical mechanisms of the Schottky diode. The obtained results are the current-voltage and capacitance-voltage characteristic as function of temperature, frequency and Schottky contact diameters with and without defects.
{"title":"Simulation of p-type Schottky Diode Based on Al0.29Ga0.71As with Titanium/Gold Schottky Contact","authors":"W. Filali, S. Oussalah, N. Sengouga, M. Henini, David Taylor","doi":"10.1109/ICM.2018.8704017","DOIUrl":"https://doi.org/10.1109/ICM.2018.8704017","url":null,"abstract":"This paper presents a systematic simulation approach for analyzing a p-type Ti/Au/Al0.29Ga0.71 As Schottky diode with traps. The traps parameters are extracted by DLTS (Deep Level Transient Spectroscopy) technique. Simulation was carried out using Atlas-SILVACO TCAD 2D simulator. The simulation is performed using the appropriate physical models to explain the behavior of the physical mechanisms of the Schottky diode. The obtained results are the current-voltage and capacitance-voltage characteristic as function of temperature, frequency and Schottky contact diameters with and without defects.","PeriodicalId":305356,"journal":{"name":"2018 30th International Conference on Microelectronics (ICM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132517186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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