C. A. Pennise, H. E. Boesch, G. Goetz, J. B. Mckitterick
Silicon-on-insulator (SOI) materials are known to possess many features attractive for use in microelectronic applications. To take advantage of these features, it is important to understand and characterize the effects of ionizing radiation on the electrical properties of SOI materials and devices. In this paper we apply the photocurrent technique together with capacitance-voltage measurements to study four representative BESOI buried oxide (BOX) materials with different processing histories. In the photoconduction current technique, an X-ray machine is used to measure a radiation-generated current that can be related to the amount of charge moving through the BOX layer. These methods allow us to develop a clear picture of the radiation-induced charge trapping and transport properties of SOI material.<>
{"title":"Radiation effects in BESOI structures with different insulating layers","authors":"C. A. Pennise, H. E. Boesch, G. Goetz, J. B. Mckitterick","doi":"10.1109/SOI.1993.344605","DOIUrl":"https://doi.org/10.1109/SOI.1993.344605","url":null,"abstract":"Silicon-on-insulator (SOI) materials are known to possess many features attractive for use in microelectronic applications. To take advantage of these features, it is important to understand and characterize the effects of ionizing radiation on the electrical properties of SOI materials and devices. In this paper we apply the photocurrent technique together with capacitance-voltage measurements to study four representative BESOI buried oxide (BOX) materials with different processing histories. In the photoconduction current technique, an X-ray machine is used to measure a radiation-generated current that can be related to the amount of charge moving through the BOX layer. These methods allow us to develop a clear picture of the radiation-induced charge trapping and transport properties of SOI material.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Flandre, P. Francis, J. Colinge, S. Cristoloveanu
The advantage of symmetrical gate (GAA) SOI structures over regular SOI in the case of AM p-MOSFETs was demonstrated in several respects: suppression of a latch phenomenon, suppression of excessively high hot-electron gate currents which have been experimentally and theoretically correlated with the latch, and better resistance to hot-electron degradation due to the absence of the latch and of the vulnerable buried oxide.<>
{"title":"Comparison of hot-carrier effects in thin-film SOI and gate-all-around accumulation-mode p-MOSFETs","authors":"D. Flandre, P. Francis, J. Colinge, S. Cristoloveanu","doi":"10.1109/SOI.1993.344553","DOIUrl":"https://doi.org/10.1109/SOI.1993.344553","url":null,"abstract":"The advantage of symmetrical gate (GAA) SOI structures over regular SOI in the case of AM p-MOSFETs was demonstrated in several respects: suppression of a latch phenomenon, suppression of excessively high hot-electron gate currents which have been experimentally and theoretically correlated with the latch, and better resistance to hot-electron degradation due to the absence of the latch and of the vulnerable buried oxide.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127049484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the key elements of a reliable CMOS process is a robust, defect free gate oxide. The formation of such layers on bulk substrates is a topic that has been studied for many years and has reached an advanced state of understanding. In contrast the growth of reliable gate oxides on either thick or thin film SOI substrates is considerably less well understood.This paper discusses the formation of gate oxides on thick film SOI substrates. Two topics have been covered in this study, long term reliability of the oxide and early life failure rate of the oxide.<>
{"title":"Growing reliable gate oxides on thick film SOI substrates","authors":"K. Yallup, O. Creighton","doi":"10.1109/SOI.1993.344583","DOIUrl":"https://doi.org/10.1109/SOI.1993.344583","url":null,"abstract":"One of the key elements of a reliable CMOS process is a robust, defect free gate oxide. The formation of such layers on bulk substrates is a topic that has been studied for many years and has reached an advanced state of understanding. In contrast the growth of reliable gate oxides on either thick or thin film SOI substrates is considerably less well understood.This paper discusses the formation of gate oxides on thick film SOI substrates. Two topics have been covered in this study, long term reliability of the oxide and early life failure rate of the oxide.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127363371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ionescu, S. Cristoloveanu, A. Rusu, A. Chovet, A. Hassein-bey
Although powerful device simulators are being developed, analytical models are still essential for depicting the underlying physical mechanisms. Recently, attention was paid to a "unified" approach able to account for MOSFET continuous operation from weak to moderate and strong inversion. In this paper, we propose an original model which applies not only to bulk Si and partially depleted SOI MOSFET's, but also to ultrathin film SOI transistors.<>
{"title":"A unified model of threshold voltage, subthreshold slope and interface coupling in thin film SOI MOSFETs","authors":"A. Ionescu, S. Cristoloveanu, A. Rusu, A. Chovet, A. Hassein-bey","doi":"10.1109/SOI.1993.344559","DOIUrl":"https://doi.org/10.1109/SOI.1993.344559","url":null,"abstract":"Although powerful device simulators are being developed, analytical models are still essential for depicting the underlying physical mechanisms. Recently, attention was paid to a \"unified\" approach able to account for MOSFET continuous operation from weak to moderate and strong inversion. In this paper, we propose an original model which applies not only to bulk Si and partially depleted SOI MOSFET's, but also to ultrathin film SOI transistors.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Yee, L. Hite, T. Houston, Y. Sheu, Rajan, Rajgopal, C. Shen, J. Hwang, G. Pollack
A 1-M bit SRAM with 0.8 um feature sizes has been successfully fabricated using SIMOX material. The advantages of SOI for low capacitance, latch-up immunity, and reduced collection charge for single events have been long recognized. The demonstration of a 1-M SRAM at 0.8 um is a significant milestone in the evaluation of the technology for fabrication of very large scale integrated circuits.<>
{"title":"A 1-M bit SRAM on SIMOX material","authors":"E. Yee, L. Hite, T. Houston, Y. Sheu, Rajan, Rajgopal, C. Shen, J. Hwang, G. Pollack","doi":"10.1109/SOI.1993.344546","DOIUrl":"https://doi.org/10.1109/SOI.1993.344546","url":null,"abstract":"A 1-M bit SRAM with 0.8 um feature sizes has been successfully fabricated using SIMOX material. The advantages of SOI for low capacitance, latch-up immunity, and reduced collection charge for single events have been long recognized. The demonstration of a 1-M SRAM at 0.8 um is a significant milestone in the evaluation of the technology for fabrication of very large scale integrated circuits.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114191526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the characteristics of n-channel SOI MOSFETs in MOS and hybrid-modes of operation are simulated using standard MOS I-V equations. It is shown that the enhancement in drain current in the threshold region is only due to the reduction of the MOS threshold voltage by the applied positive body bias. Only for body voltages higher than 2/spl phi//sub P/ does the BJT contribution to the drain current become significant.<>
{"title":"Analysis of hybrid-mode operation of SOI MOSFETs","authors":"M. Matloubian","doi":"10.1109/SOI.1993.344541","DOIUrl":"https://doi.org/10.1109/SOI.1993.344541","url":null,"abstract":"In this paper, the characteristics of n-channel SOI MOSFETs in MOS and hybrid-modes of operation are simulated using standard MOS I-V equations. It is shown that the enhancement in drain current in the threshold region is only due to the reduction of the MOS threshold voltage by the applied positive body bias. Only for body voltages higher than 2/spl phi//sub P/ does the BJT contribution to the drain current become significant.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Flament, P. Paillet, D. Hervé, O. Musseau, J. Leray, B. Aspar
The pseudo-MOS transistor (/spl Psi/-MOSFET) has been proposed as a cheap and easy tool to characterize as-grown SOI wafers and to anticipate the radiation hardness performance of technologies manufactured upon these substrates. The aim of this study is to check the ability of this technique to investigate SIMOX response for doses up to 100 Mrad(SiO/sub 2/). Direct comparison with basic MOS transistors reveals the influence of the process.<>
{"title":"High dose response of as-grown SIMOX substrates","authors":"O. Flament, P. Paillet, D. Hervé, O. Musseau, J. Leray, B. Aspar","doi":"10.1109/SOI.1993.344596","DOIUrl":"https://doi.org/10.1109/SOI.1993.344596","url":null,"abstract":"The pseudo-MOS transistor (/spl Psi/-MOSFET) has been proposed as a cheap and easy tool to characterize as-grown SOI wafers and to anticipate the radiation hardness performance of technologies manufactured upon these substrates. The aim of this study is to check the ability of this technique to investigate SIMOX response for doses up to 100 Mrad(SiO/sub 2/). Direct comparison with basic MOS transistors reveals the influence of the process.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125309707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS.<>
深亚微米，薄的完全耗尽(TFD) SOI mosfet在未来的ULSI技术中是可行的，它们在低功耗电路中也有潜在的应用。然而，随着它们的大幅缩小，由于冲击电离驱动的寄生BJT，它们的过早击穿和非状态闩锁会威胁到它们的生存能力。这些效应的可靠建模需要对冲击电离进行非局部分析，而传统的局部场分析往往会过度预测载流子产生率。此外，为了在电路级研究上述效应，模型必须紧凑，同时反映潜在的器件物理。在本文中，我们描述了在强反转和弱反转的完全耗尽SOI mosfet中碰撞电离的非局部模型的开发和实现，并讨论了该器件模型在我们的预测电路模拟器SOISPICE-2中的应用，以优化缩放SOI CMOS的设计。
{"title":"Non-local modeling of impact ionization for optimal device/circuit design in fully depleted SOI CMOS technology","authors":"S. Krishnan, J. Fossum","doi":"10.1109/SOI.1993.344570","DOIUrl":"https://doi.org/10.1109/SOI.1993.344570","url":null,"abstract":"Deep-submicron, thin fully depleted (TFD) SOI MOSFETs are potentially viable for future ULSI technology, and they also have potential applications in low-power circuits. However as they are aggressively scaled down, premature breakdown and off-state latch, attributed to the parasitic BJT driven by impact-ionization, threaten their viability. Reliable modeling of these effects requires a non-local analysis of impact ionization, as opposed to conventional local-field analyses that tend to over-predict the carrier generation rate. Furthermore, to study the mentioned effects at the circuit level, the models have to be compact while reflecting the underlying device physics. In this paper we describe the development and implementation of a non-local model for impact ionization in fully depleted SOI MOSFETs in both strong and weak inversion, and we discuss application of the device model in our predictive circuit simulator SOISPICE-2 to design optimization of scaled SOI CMOS.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115372774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. T. Su, J. B. Jacobs, J. E. Chung, D. Antoniadis
Thin-film, fully-depleted silicon-on-insulator (SOI) MOSFETs are currently of great interest due to potentially improved isolation, reduced subthreshold slope, and reduced parasitic capacitances as compared to bulk silicon technology. In addition, for scaling devices into the deep-submicrometer region, SOI offers unique options for the reduction of short-channel effects. Previous work has shown that scaling silicon film thickness and buried oxide thickness are important in the reduction of SOI short-channel effects. However, to fully exploit these options in SOI, a careful examination of the design tradeoffs is necessary. In this paper, short-channel effects in SOI are examined in comparison to conventional bulk devices for scaling into the deep-submicrometer region.<>
{"title":"Short-channel effects in deep-submicrometer SOI MOSFETS","authors":"L. T. Su, J. B. Jacobs, J. E. Chung, D. Antoniadis","doi":"10.1109/SOI.1993.344571","DOIUrl":"https://doi.org/10.1109/SOI.1993.344571","url":null,"abstract":"Thin-film, fully-depleted silicon-on-insulator (SOI) MOSFETs are currently of great interest due to potentially improved isolation, reduced subthreshold slope, and reduced parasitic capacitances as compared to bulk silicon technology. In addition, for scaling devices into the deep-submicrometer region, SOI offers unique options for the reduction of short-channel effects. Previous work has shown that scaling silicon film thickness and buried oxide thickness are important in the reduction of SOI short-channel effects. However, to fully exploit these options in SOI, a careful examination of the design tradeoffs is necessary. In this paper, short-channel effects in SOI are examined in comparison to conventional bulk devices for scaling into the deep-submicrometer region.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There exists a well established model for the subthreshold slope of enhancement-mode MOSFETs. Indeed, the subthreshold slope is given by: S=kT/q ln10 (1+/spl alpha/) where /spl alpha/ is equal to the ratio C/sub bb//C/sub ox1/. In other words, /spl alpha/ is the ratio between the capacitance of the structure below the channel and that of the structure above it. C/sub bb/ is equal to C/sub depl/, C/sub si/ and (C/sub si/ in series with C/sub ox2/) in bulk, fully depleted (FD) SOI with back accumulation and fully depleted SOI devices, respectively. As the potential distribution in an accumulation-mode (AM) p-channel SOI MOSFET in the subthreshold regime is similar to that of an n-channel FD enhancement-mode (FDEM) device, the same analytical model can be used to determine S.<>
{"title":"Subthreshold slope of accumulation-mode p-channel SOI MOSFETs","authors":"J. Colinge, F. van de Wiele, D. Flandre","doi":"10.1109/SOI.1993.344558","DOIUrl":"https://doi.org/10.1109/SOI.1993.344558","url":null,"abstract":"There exists a well established model for the subthreshold slope of enhancement-mode MOSFETs. Indeed, the subthreshold slope is given by: S=kT/q ln10 (1+/spl alpha/) where /spl alpha/ is equal to the ratio C/sub bb//C/sub ox1/. In other words, /spl alpha/ is the ratio between the capacitance of the structure below the channel and that of the structure above it. C/sub bb/ is equal to C/sub depl/, C/sub si/ and (C/sub si/ in series with C/sub ox2/) in bulk, fully depleted (FD) SOI with back accumulation and fully depleted SOI devices, respectively. As the potential distribution in an accumulation-mode (AM) p-channel SOI MOSFET in the subthreshold regime is similar to that of an n-channel FD enhancement-mode (FDEM) device, the same analytical model can be used to determine S.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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