M.S.L. Lee, W. Redman-White, B. Tenbroek, M. Robinson
Circuit simulation models for thin-film silicon-on-insulator (SOI) MOSFETs have been available for some time. However, these do not take account of the increasingly important self-heating effects that have been widely reported. These effects can lead to a significant reduction in the drain current resulting in negative differential resistance (NDR) in the I/V characteristics of SOI devices. Moreover, recent work has shown that thermal self-heating can also affect transient and small-signal behaviour. Here, we describe the implementation of a model in the SPICE3 code which has been developed to include thermal effects as well as some of the other common characteristics observed in SOI devices. Results of trial simulations are then presented.<>
{"title":"Modelling of thin film SOI devices for circuit simulation including per-instance dynamic self-heating effects","authors":"M.S.L. Lee, W. Redman-White, B. Tenbroek, M. Robinson","doi":"10.1109/SOI.1993.344556","DOIUrl":"https://doi.org/10.1109/SOI.1993.344556","url":null,"abstract":"Circuit simulation models for thin-film silicon-on-insulator (SOI) MOSFETs have been available for some time. However, these do not take account of the increasingly important self-heating effects that have been widely reported. These effects can lead to a significant reduction in the drain current resulting in negative differential resistance (NDR) in the I/V characteristics of SOI devices. Moreover, recent work has shown that thermal self-heating can also affect transient and small-signal behaviour. Here, we describe the implementation of a model in the SPICE3 code which has been developed to include thermal effects as well as some of the other common characteristics observed in SOI devices. Results of trial simulations are then presented.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Integrated circuits operating at elevated temperatures are of interest in several applications such as automotive, well logging, aircraft, and spacecraft. Conventional silicon integrated circuits usually cease to function at approximately 250/spl deg/C because of excessive junction leakage currents. Source-drain junction areas in the MOSFETs fabricated in SOI are much smaller than those in bulk Si MOSFETs. In addition, the total volume of Si in SOI devices is also very small, which can reduce the diffusion currents across the junction especially at high temperatures. Hence, in principle, smaller leakage currents can be achieved at high temperatures if bulk Si quality source-drain junctions are made in SOI MOSFETs employing ultra-thin Si films. The possibility of lower leakage currents makes SOI MOSFETs attractive for operation at elevated temperatures beyond the operating temperatures of bulk Si MOSFETs. Several studies of SOI devices at elevated temperatures are found in the published literature. Speculations on extending the operating temperature to higher values (/spl sim/500/spl deg/C) with improved performance by extremely thinning the SOI film (30 nm) have also been made in the literature. This present study of fully depleted NMOS devices fabricated in thin (23.5, 63.5 and 91.5 nm) SIMOX Si films was taken up to verify the high temperature advantages of thinning the SOI film.<>
{"title":"Ultra-thin SOI MOSFETs at high temperature","authors":"P. Karulkar","doi":"10.1109/SOI.1993.344561","DOIUrl":"https://doi.org/10.1109/SOI.1993.344561","url":null,"abstract":"Integrated circuits operating at elevated temperatures are of interest in several applications such as automotive, well logging, aircraft, and spacecraft. Conventional silicon integrated circuits usually cease to function at approximately 250/spl deg/C because of excessive junction leakage currents. Source-drain junction areas in the MOSFETs fabricated in SOI are much smaller than those in bulk Si MOSFETs. In addition, the total volume of Si in SOI devices is also very small, which can reduce the diffusion currents across the junction especially at high temperatures. Hence, in principle, smaller leakage currents can be achieved at high temperatures if bulk Si quality source-drain junctions are made in SOI MOSFETs employing ultra-thin Si films. The possibility of lower leakage currents makes SOI MOSFETs attractive for operation at elevated temperatures beyond the operating temperatures of bulk Si MOSFETs. Several studies of SOI devices at elevated temperatures are found in the published literature. Speculations on extending the operating temperature to higher values (/spl sim/500/spl deg/C) with improved performance by extremely thinning the SOI film (30 nm) have also been made in the literature. This present study of fully depleted NMOS devices fabricated in thin (23.5, 63.5 and 91.5 nm) SIMOX Si films was taken up to verify the high temperature advantages of thinning the SOI film.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The statistical variation of the threshold voltage in SOI MOSFETs can be calculated using the probability distribution of the threshold voltage assuming that device parameters can be characterized with a Gaussian distribution. In order to evaluate the relative importance in device parameters and obtain the worst case analysis. however. it would be effective to express the variation in an analytical form. In this paper, we present analytical expressions of the threshold voltage variation for thin-film SOI and bulk MOSFETs, and discuss influences by SOI doping density N/sub SOI/ and SOI film thickness t/sub SOI/.<>
{"title":"An analysis of threshold voltage variation in thin-film SOI MOSFETs","authors":"S. Masui, M. Tachimori","doi":"10.1109/SOI.1993.344578","DOIUrl":"https://doi.org/10.1109/SOI.1993.344578","url":null,"abstract":"The statistical variation of the threshold voltage in SOI MOSFETs can be calculated using the probability distribution of the threshold voltage assuming that device parameters can be characterized with a Gaussian distribution. In order to evaluate the relative importance in device parameters and obtain the worst case analysis. however. it would be effective to express the variation in an analytical form. In this paper, we present analytical expressions of the threshold voltage variation for thin-film SOI and bulk MOSFETs, and discuss influences by SOI doping density N/sub SOI/ and SOI film thickness t/sub SOI/.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125005491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Feng, M. Matloubian, D. Mathur, P.B. Mumola, G. Gardopee
Gate-oxide breakdown measurements were made to determine the quality of the Si surface of plasma-thinned Si wafers. Circular MOS capacitors having a thermal oxide of 190 A were fabricated on unprocessed bulk Si wafers and plasma-thinned wafers. The distribution of gate-oxide breakdown voltages for 250-/spl mu/m diameter MOS capacitors fabricated on a bulk Si wafer and on a plasma-thinned bulk Si wafer are shown. The similarity between the breakdown distributions is an indication that the AcuThin wafer thinning process does not degrade the Si surface quality. Based on these and other results to be presented, we believe that this plasma etching process for thinning bonded Si wafers does not cause any surface or subsurface damage which could adversely impact device performance, i.e., it preserves the bulk silicon material qualities.<>
{"title":"Material properties of plasma-thinned bonded SOI wafers","authors":"T. Feng, M. Matloubian, D. Mathur, P.B. Mumola, G. Gardopee","doi":"10.1109/SOI.1993.344591","DOIUrl":"https://doi.org/10.1109/SOI.1993.344591","url":null,"abstract":"Gate-oxide breakdown measurements were made to determine the quality of the Si surface of plasma-thinned Si wafers. Circular MOS capacitors having a thermal oxide of 190 A were fabricated on unprocessed bulk Si wafers and plasma-thinned wafers. The distribution of gate-oxide breakdown voltages for 250-/spl mu/m diameter MOS capacitors fabricated on a bulk Si wafer and on a plasma-thinned bulk Si wafer are shown. The similarity between the breakdown distributions is an indication that the AcuThin wafer thinning process does not degrade the Si surface quality. Based on these and other results to be presented, we believe that this plasma etching process for thinning bonded Si wafers does not cause any surface or subsurface damage which could adversely impact device performance, i.e., it preserves the bulk silicon material qualities.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MOSFETs built on the SOI structure exhibit superior short channel behaviors over the bulk MOSFETs. They also have other advantages such as reduction of the junction capacitance, radiation hardness and ease for device isolation. The SOI MOSFET is a promising candidate for future device scaling. The hot-carrier effect that increases with device miniaturization is another important device scaling constraint that has to be considered for the SOI MOSFET. The hot-carrier effect, which is usually monitored by the substrate current for the NMOSFET and the gate current for the PMOSFET for bulk devices, are closely related to the high channel electric field near the drain. The quasi-two-dimensional (quasi-2D) model provides the link between the hot-carrier currents and the device design parameters for the bulk MOSFETs. This model is refined by considering the 2D effect and the lateral doping gradient effect separately.<>
{"title":"Hot-carrier currents of SOI MOSFETs","authors":"H. Wann, J. King, Jian Chen, P. Ko, C. Hu","doi":"10.1109/SOI.1993.344568","DOIUrl":"https://doi.org/10.1109/SOI.1993.344568","url":null,"abstract":"MOSFETs built on the SOI structure exhibit superior short channel behaviors over the bulk MOSFETs. They also have other advantages such as reduction of the junction capacitance, radiation hardness and ease for device isolation. The SOI MOSFET is a promising candidate for future device scaling. The hot-carrier effect that increases with device miniaturization is another important device scaling constraint that has to be considered for the SOI MOSFET. The hot-carrier effect, which is usually monitored by the substrate current for the NMOSFET and the gate current for the PMOSFET for bulk devices, are closely related to the high channel electric field near the drain. The quasi-two-dimensional (quasi-2D) model provides the link between the hot-carrier currents and the device design parameters for the bulk MOSFETs. This model is refined by considering the 2D effect and the lateral doping gradient effect separately.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121039566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Allen, B. Cordts, W. Krull, J. Yap, T. Maung, J. Chung
We present results of the first experiments investigating the effects of wafer temperature during the SIMOX implant which is independent of the beam current. The results show a decreased pinhole density at the lower implant temperature and better dislocation density and substrate/buried oxide interface structure at the higher temperature.<>
{"title":"Independent control of wafer temperature and beam current on SIMOX material quality","authors":"L. Allen, B. Cordts, W. Krull, J. Yap, T. Maung, J. Chung","doi":"10.1109/SOI.1993.344609","DOIUrl":"https://doi.org/10.1109/SOI.1993.344609","url":null,"abstract":"We present results of the first experiments investigating the effects of wafer temperature during the SIMOX implant which is independent of the beam current. The results show a decreased pinhole density at the lower implant temperature and better dislocation density and substrate/buried oxide interface structure at the higher temperature.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122293246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Performance advantages of SOI technology have been widely published. However, a critical step in the maturation of any technology is progressing from demonstrating best case performance advantages to demonstrating repeatable performance. For a technology to be production qualified, target values must be met for critical parameters, with lot parametric variations within the required tolerances. We examine fully depleted SOI from this point of view. As a result of the very thin Si films used in fully-depleted SOI, sensitivities are found for process steps such as oxidation, salicide formation, and photolithography that are not found in bulk silicon or partially-depleted SOI. Since one of most important SOI substrate parameters is the thickness of the Si film (tsi), we focus here on how key electrical parameters are affected by tsi, for both mean and standard deviation. We find that not only is the tsi variation across a single wafer important, but that it must be controlled lot to lot. This impacts SOI wafer suppliers, as well as VLSI production flows in which sacrificial oxidations are done.<>
{"title":"Manufacturability considerations for fully depleted SOI","authors":"F. Brady, N. Haddad","doi":"10.1109/SOI.1993.344564","DOIUrl":"https://doi.org/10.1109/SOI.1993.344564","url":null,"abstract":"Performance advantages of SOI technology have been widely published. However, a critical step in the maturation of any technology is progressing from demonstrating best case performance advantages to demonstrating repeatable performance. For a technology to be production qualified, target values must be met for critical parameters, with lot parametric variations within the required tolerances. We examine fully depleted SOI from this point of view. As a result of the very thin Si films used in fully-depleted SOI, sensitivities are found for process steps such as oxidation, salicide formation, and photolithography that are not found in bulk silicon or partially-depleted SOI. Since one of most important SOI substrate parameters is the thickness of the Si film (tsi), we focus here on how key electrical parameters are affected by tsi, for both mean and standard deviation. We find that not only is the tsi variation across a single wafer important, but that it must be controlled lot to lot. This impacts SOI wafer suppliers, as well as VLSI production flows in which sacrificial oxidations are done.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"16 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Feijóo, A. Mills, A. Kortan, J. Sapjeta, C. Hsieh, G. Carver
In this work we have used established and novel analysis techniques to compare SOI wafers produced by wafer-bonding and different thinning techniques such as chemical-mechanical thinning, plasma etching and wet etching, and by separation-by-implanted-oxygen (SIMOX). The techniques employed were optical-beam-induced reflectance, positron annihilation, atomic force microscopy and X-ray diffractometry.<>
{"title":"Comparative materials characterization of SOI wafers produced by competing technologies","authors":"D. Feijóo, A. Mills, A. Kortan, J. Sapjeta, C. Hsieh, G. Carver","doi":"10.1109/SOI.1993.344603","DOIUrl":"https://doi.org/10.1109/SOI.1993.344603","url":null,"abstract":"In this work we have used established and novel analysis techniques to compare SOI wafers produced by wafer-bonding and different thinning techniques such as chemical-mechanical thinning, plasma etching and wet etching, and by separation-by-implanted-oxygen (SIMOX). The techniques employed were optical-beam-induced reflectance, positron annihilation, atomic force microscopy and X-ray diffractometry.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127144580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Venables, S. J. Krause, J.C. Park, J.D. Lee, P. Roitman
In this paper we describe the origin and characteristics of the defect structures in contemporary SIMOX and show how their densities are controlled by the processing method and conditions.<>
本文描述了当代SIMOX中缺陷结构的起源和特征，并说明了它们的密度如何受到加工方法和条件的控制。
{"title":"Effect of single vs. multiple implant processing on defect types and densities in SIMOX","authors":"D. Venables, S. J. Krause, J.C. Park, J.D. Lee, P. Roitman","doi":"10.1109/SOI.1993.344598","DOIUrl":"https://doi.org/10.1109/SOI.1993.344598","url":null,"abstract":"In this paper we describe the origin and characteristics of the defect structures in contemporary SIMOX and show how their densities are controlled by the processing method and conditions.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"36 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129382560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of this work is to demonstrate that hot electron stressing one channel in a SOI MOSFET can in fact inject charges into the other channel, and it discusses two important applications of this phenomenon: namely, that it can be used as a new tool for the study of the mechanisms of degradation, and for designing erasing schemes for SOI based flash memories. The measurements were performed on partially and fully depleted SIMOX MOSFETs with LDD and channel lengths down to 0.6 /spl mu/m.<>
{"title":"Successive charging/discharging of gate oxides in SOI MOSFETs by sequential hot electron stressing of front/back channel","authors":"A. Zaleski, D. Ioannou, G. Campisi, H. Hughes","doi":"10.1109/SOI.1993.344552","DOIUrl":"https://doi.org/10.1109/SOI.1993.344552","url":null,"abstract":"The purpose of this work is to demonstrate that hot electron stressing one channel in a SOI MOSFET can in fact inject charges into the other channel, and it discusses two important applications of this phenomenon: namely, that it can be used as a new tool for the study of the mechanisms of degradation, and for designing erasing schemes for SOI based flash memories. The measurements were performed on partially and fully depleted SIMOX MOSFETs with LDD and channel lengths down to 0.6 /spl mu/m.<<ETX>>","PeriodicalId":308249,"journal":{"name":"Proceedings of 1993 IEEE International SOI Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125627179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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