Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286247
P. Matyasik, G. J. Nalepa
This paper presents a concept of an integrated development platform for fast and error-free implementation of embedded intelligent systems. The main idea reside in dividing the control program into separate logic layers. The lowest-level layer uses embedded real-time operating system. The high-level control is knowledge-based and provides an intelligent system behavior. The paper presents some implementation details of the low-level layer and the concept of the intelligent control layer. The concept is then applied to the Hexorll mobile robot platform.
{"title":"Knowledge-Based Control of Reactive Systems with Multi-Layer Architecture","authors":"P. Matyasik, G. J. Nalepa","doi":"10.1109/MIXDES.2007.4286247","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286247","url":null,"abstract":"This paper presents a concept of an integrated development platform for fast and error-free implementation of embedded intelligent systems. The main idea reside in dividing the control program into separate logic layers. The lowest-level layer uses embedded real-time operating system. The high-level control is knowledge-based and provides an intelligent system behavior. The paper presents some implementation details of the low-level layer and the concept of the intelligent control layer. The concept is then applied to the Hexorll mobile robot platform.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130592003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286167
A. Amaricai, M. Vladutiu, L. Prodan, M. Udrescu, O. Boncalo
This paper presents the design and implementation of a combined, interval and conventional floating point multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point multiplier - which computes several results of the same operation (rounded differently) - and of two floating point comparator circuits. This architecture implements an algorithm that is suitable for pipelined structures. Furthermore, the two floating point comparators can be used for interval hull and intersection, two of the most frequent interval operations. The cost overhead of the proposed unit is 40% with respect to a conventional floating point multiplier. The performance of the floating point multiplication on the proposed architecture is the same as of a conventional floating point multiplier, whereas the performance of an interval multiplication is almost half-an outstanding result for such a demanding operation.
{"title":"Hardware Support for Combined Interval and Floating Point Multiplication","authors":"A. Amaricai, M. Vladutiu, L. Prodan, M. Udrescu, O. Boncalo","doi":"10.1109/MIXDES.2007.4286167","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286167","url":null,"abstract":"This paper presents the design and implementation of a combined, interval and conventional floating point multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point multiplier - which computes several results of the same operation (rounded differently) - and of two floating point comparator circuits. This architecture implements an algorithm that is suitable for pipelined structures. Furthermore, the two floating point comparators can be used for interval hull and intersection, two of the most frequent interval operations. The cost overhead of the proposed unit is 40% with respect to a conventional floating point multiplier. The performance of the floating point multiplication on the proposed architecture is the same as of a conventional floating point multiplier, whereas the performance of an interval multiplication is almost half-an outstanding result for such a demanding operation.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130653513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286160
M.S.T. Talaska, R. Dlugosz, R. Wojtyna
In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner take all circuit, Euclidean distance calculation circuit, adaptive weights change mechanism. The example network contains four neurons, each of them having three weights. There are three input signals applied, which can be currents or voltages converted just at the beginning into currents. The network operates with the clock frequency of 20 MHz, dissipating 1.5 mW of power from 1.5 V supply voltage. For lower operation frequencies power dissipation can be reduced.
{"title":"Current Mode Analog Kohonen Neural Network","authors":"M.S.T. Talaska, R. Dlugosz, R. Wojtyna","doi":"10.1109/MIXDES.2007.4286160","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286160","url":null,"abstract":"In this paper we present Matlab analysis as well as CMOS implementation of an analog current mode Kohonen neural network (KNN). The presented KNN has been realized using several building blocks proposed earlier by the authors, such as: binary tree winner take all circuit, Euclidean distance calculation circuit, adaptive weights change mechanism. The example network contains four neurons, each of them having three weights. There are three input signals applied, which can be currents or voltages converted just at the beginning into currents. The network operates with the clock frequency of 20 MHz, dissipating 1.5 mW of power from 1.5 V supply voltage. For lower operation frequencies power dissipation can be reduced.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126210601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286203
A. Schafer, J. Freuer, K. Hahn, W. Nebel, R. Bruck
The entire verification of simple and complex constraints is crucial to the development of highly reliable microelectronic systems as they are demanded by the zero defect policy in the automobile industry. The increasing requirements on electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional properties. This paper describes a constraint verification method based on a unified representation of constraints enabling multi-tool verification tasks. With the constraint engineering system (CES) we present a new verification method, which provides flexible, extensible, and multi-tool definitions of complex constraints. The CES does not replace existing verification and simulation tools. It rather offers a method to combine these tools. The CES is based on the approaches of constraint logic programming and is capable of processing verification tasks on a much higher level of abstraction than usually found in existing verification tools. First tests of practical applications prove the power, flexibility, practicability, and potential of our approach.
{"title":"Multi-Tool Constraint Verification","authors":"A. Schafer, J. Freuer, K. Hahn, W. Nebel, R. Bruck","doi":"10.1109/MIXDES.2007.4286203","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286203","url":null,"abstract":"The entire verification of simple and complex constraints is crucial to the development of highly reliable microelectronic systems as they are demanded by the zero defect policy in the automobile industry. The increasing requirements on electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional properties. This paper describes a constraint verification method based on a unified representation of constraints enabling multi-tool verification tasks. With the constraint engineering system (CES) we present a new verification method, which provides flexible, extensible, and multi-tool definitions of complex constraints. The CES does not replace existing verification and simulation tools. It rather offers a method to combine these tools. The CES is based on the approaches of constraint logic programming and is capable of processing verification tasks on a much higher level of abstraction than usually found in existing verification tools. First tests of practical applications prove the power, flexibility, practicability, and potential of our approach.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121595780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286127
D. Stefanovic, S. Pesenti, M. Pastre, M. Kayal
This paper presents the design flow from system-level specifications to transistor-level design for three different fully-differential amplifiers composing the first and the second integrator of a second-order hybrid multi-bit ΔΣ modulator. The circuit-level specifications for each amplifier are extracted using behavioral models and time-domain system-level simulations with a SNDR target value of 93 dB ± 2 dB. The amplifiers are designed using the structured analog design methodology consisting of circuit partitioning into basic analog blocks, specification derivation for each basic block, and transistor sizing in a specific design sequence. Transistor-level design is based on the choice of the inversion factor and the transistor length to achieve the required specifications of each block. After all three analog amplifiers are sized, the system-level performance is confirmed by time-domain simulations, and the obtained SNDR value is within the specified range.
{"title":"Structured Design Based on the Inversion Factor Parameter: Case Study of ΔΣ Modulator System","authors":"D. Stefanovic, S. Pesenti, M. Pastre, M. Kayal","doi":"10.1109/MIXDES.2007.4286127","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286127","url":null,"abstract":"This paper presents the design flow from system-level specifications to transistor-level design for three different fully-differential amplifiers composing the first and the second integrator of a second-order hybrid multi-bit ΔΣ modulator. The circuit-level specifications for each amplifier are extracted using behavioral models and time-domain system-level simulations with a SNDR target value of 93 dB ± 2 dB. The amplifiers are designed using the structured analog design methodology consisting of circuit partitioning into basic analog blocks, specification derivation for each basic block, and transistor sizing in a specific design sequence. Transistor-level design is based on the choice of the inversion factor and the transistor length to achieve the required specifications of each block. After all three analog amplifiers are sized, the system-level performance is confirmed by time-domain simulations, and the obtained SNDR value is within the specified range.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121520950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/ISSCS.2007.4292655
J. Seon, K. Nam, S.H. Kang, K. Bae, J.B. Kim
A novel track-and-hold (T&H) employing an operational transconductance amplifier (OTA) with two cross-coupled differential pairs (CCDPs) is proposed for high-accuracy and high-frequency applications. The T&H has a simple architecture requiring smaller capacitors and fewer switches and offers higher speed, lower distortion, and lower power dissipation than its op-amp based counterparts. The chip implemented in 0.35 mum CMOS process operates from a single 1.8 V supply and achieves more than 10-bits precision for sampling rate in excess of 120 MS/s.
提出了一种新的跟踪保持(T&H)方法，该方法采用具有两个交叉耦合差分对(ccdp)的运算跨导放大器(OTA)，用于高精度和高频应用。T&H具有简单的结构，需要更小的电容器和更少的开关，并且与基于运放的同类产品相比，具有更高的速度、更低的失真和更低的功耗。该芯片采用0.35 μ m CMOS工艺，采用1.8 V单电源，采样率超过120 MS/s，精度超过10位。
{"title":"A Simple and Accurate Track-and-Hold Circuit using Operational Transconductance Amplifier","authors":"J. Seon, K. Nam, S.H. Kang, K. Bae, J.B. Kim","doi":"10.1109/ISSCS.2007.4292655","DOIUrl":"https://doi.org/10.1109/ISSCS.2007.4292655","url":null,"abstract":"A novel track-and-hold (T&H) employing an operational transconductance amplifier (OTA) with two cross-coupled differential pairs (CCDPs) is proposed for high-accuracy and high-frequency applications. The T&H has a simple architecture requiring smaller capacitors and fewer switches and offers higher speed, lower distortion, and lower power dissipation than its op-amp based counterparts. The chip implemented in 0.35 mum CMOS process operates from a single 1.8 V supply and achieves more than 10-bits precision for sampling rate in excess of 120 MS/s.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132719612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286227
P. Del Croce, J. Hadzi-Vukovic, B. Meldt, M. Ladurner
This paper presents a design approach based on the splitting of the power transistor for smart power applications. The design approach is applied to realize a high side power switch with a configurable output in smart power technology. Experimental results are also presented and discussed.
{"title":"Configurable High Side Power Switch in Smart Power Technology","authors":"P. Del Croce, J. Hadzi-Vukovic, B. Meldt, M. Ladurner","doi":"10.1109/MIXDES.2007.4286227","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286227","url":null,"abstract":"This paper presents a design approach based on the splitting of the power transistor for smart power applications. The design approach is applied to realize a high side power switch with a configurable output in smart power technology. Experimental results are also presented and discussed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133305105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286176
X. Ren, T. Kazmierski
The paper presents a novel approach to efficient performance modelling and optimisation which can be applied to automatic synthesis of circuit-level radio frequency (RF) analogue circuits. Support vector machines regression models are used to construct automatically general performance models for RF circuits which lend themselves naturally to pattern-search optimisation by exploring the design space. Experiments show that the approach can provide accurate and extremely fast performance estimation.
{"title":"Performance Modelling and Optimisation of RF Circuits using Support Vector Machines","authors":"X. Ren, T. Kazmierski","doi":"10.1109/MIXDES.2007.4286176","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286176","url":null,"abstract":"The paper presents a novel approach to efficient performance modelling and optimisation which can be applied to automatic synthesis of circuit-level radio frequency (RF) analogue circuits. Support vector machines regression models are used to construct automatically general performance models for RF circuits which lend themselves naturally to pattern-search optimisation by exploring the design space. Experiments show that the approach can provide accurate and extremely fast performance estimation.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115627418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286124
H. Momose, S. Yoshitomi, K. Kojima, T. Ohguro, Y. Toyoshima, H. Ishiuchi
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.
{"title":"Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel","authors":"H. Momose, S. Yoshitomi, K. Kojima, T. Ohguro, Y. Toyoshima, H. Ishiuchi","doi":"10.1109/MIXDES.2007.4286124","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286124","url":null,"abstract":"Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286164
J. Kolczynski
This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the design goals. The final circuit is a unique combination of low power topologies with solutions from large gain, high power amplifiers. This was done to achieve largest possible value of amplifier's gain within total power consumption constraint. The device performance was verified positively both at the schematic and at the layout level.
{"title":"Design of Operational Amplifier with Low Power Consumption in 0.35 μm Technology","authors":"J. Kolczynski","doi":"10.1109/MIXDES.2007.4286164","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286164","url":null,"abstract":"This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the design goals. The final circuit is a unique combination of low power topologies with solutions from large gain, high power amplifiers. This was done to achieve largest possible value of amplifier's gain within total power consumption constraint. The device performance was verified positively both at the schematic and at the layout level.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114219179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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