Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286243
P. Szecówka, M. Kowalski, K. Krysztoforski, A. Wolczowski
The paper describes an architecture and design of digital circuit dedicated for wavelet transform calculation, being a part of complex pattern recognition and control algorithm. The target application is artificial hand controlled by the nervous system of handicapped human, setting strict requirements on timing. Speed/size trade-off is discussed in general and in the context of this particular application. Floating point arithmetic was applied, based on the in-house developed solutions. The concept was implemented using VHDL, verified and successfully synthesized for FPGA programmable logic.
{"title":"Wavelet Processing Implementation in Digital Hardware","authors":"P. Szecówka, M. Kowalski, K. Krysztoforski, A. Wolczowski","doi":"10.1109/MIXDES.2007.4286243","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286243","url":null,"abstract":"The paper describes an architecture and design of digital circuit dedicated for wavelet transform calculation, being a part of complex pattern recognition and control algorithm. The target application is artificial hand controlled by the nervous system of handicapped human, setting strict requirements on timing. Speed/size trade-off is discussed in general and in the context of this particular application. Floating point arithmetic was applied, based on the in-house developed solutions. The concept was implemented using VHDL, verified and successfully synthesized for FPGA programmable logic.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128082183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286251
M. Szpyrka, K. Balicki
A graphical extension of CCS process calculus called XCCS (extended CCS) is proposed in the paper. In the modified process calculus most operators were moved to a graphical layer to eliminate problems typical for CCS language, e.g. elimination of undesirable connections among agents. An XCCS model consists of two layers: a textual and a graphical one. The former is used to define behaviour of single agents, while the latter is used to define interconnections among them in concurrent systems. XCCS calculus is compatible with the CCS one and it is possible to transform an XCCS model into an equivalent CCS script. The paper presents a survey of main features of XCCS language.
{"title":"XCCS - Graphical Extension of CCS Language","authors":"M. Szpyrka, K. Balicki","doi":"10.1109/MIXDES.2007.4286251","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286251","url":null,"abstract":"A graphical extension of CCS process calculus called XCCS (extended CCS) is proposed in the paper. In the modified process calculus most operators were moved to a graphical layer to eliminate problems typical for CCS language, e.g. elimination of undesirable connections among agents. An XCCS model consists of two layers: a textual and a graphical one. The former is used to define behaviour of single agents, while the latter is used to define interconnections among them in concurrent systems. XCCS calculus is compatible with the CCS one and it is possible to transform an XCCS model into an equivalent CCS script. The paper presents a survey of main features of XCCS language.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132310793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286147
O. Mirmotahari, J. Lomsdalen, Y. Berg
In this paper we present a multiple-valued gate using pseudo floating-gate. One of the key advantages is the possibility to operate this gate in continuous mode. The avoidance of recharging the floating-gate (recharge-signal) is shown to be quite liberating and to possess new and powerful qualities. Simulation results are provided.
{"title":"A Continuous MVL Gate using Pseudo Floating-Gate","authors":"O. Mirmotahari, J. Lomsdalen, Y. Berg","doi":"10.1109/MIXDES.2007.4286147","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286147","url":null,"abstract":"In this paper we present a multiple-valued gate using pseudo floating-gate. One of the key advantages is the possibility to operate this gate in continuous mode. The avoidance of recharging the floating-gate (recharge-signal) is shown to be quite liberating and to possess new and powerful qualities. Simulation results are provided.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130228191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286231
K. Tomalczyk, T. Świa̧tczak, B. Więcek
The paper discusses efficiency issues of piezoelectric transformers in a step-down DC/DC converter application. With the development of piezoelectric technology, these compact non-magnetic devices are becoming an interesting alternative to traditional transformers in a wide range of electronic equipment. Despite high declared efficiency (above 90%), heat effects resulting from energy loss are still a great concern. A prototype of ring-shaped piezoelectric transformer specially suited for step-down applications was tested in an experimental converter circuit, driven by a programmable digital control system of the authors' own design, described in the paper. The influence of input voltage, frequency, duty factor and other conditions on the power transformation efficiency was investigated. The safe operation area for the device under test is determined and compared with its declared ratings. The correlation between efficiency and thermal behavior of the transformer is discussed.
{"title":"Piezoelectric Transformer Efficiency Tests in a Digitally Controlled Converter Circuit","authors":"K. Tomalczyk, T. Świa̧tczak, B. Więcek","doi":"10.1109/MIXDES.2007.4286231","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286231","url":null,"abstract":"The paper discusses efficiency issues of piezoelectric transformers in a step-down DC/DC converter application. With the development of piezoelectric technology, these compact non-magnetic devices are becoming an interesting alternative to traditional transformers in a wide range of electronic equipment. Despite high declared efficiency (above 90%), heat effects resulting from energy loss are still a great concern. A prototype of ring-shaped piezoelectric transformer specially suited for step-down applications was tested in an experimental converter circuit, driven by a programmable digital control system of the authors' own design, described in the paper. The influence of input voltage, frequency, duty factor and other conditions on the power transformation efficiency was investigated. The safe operation area for the device under test is determined and compared with its declared ratings. The correlation between efficiency and thermal behavior of the transformer is discussed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286211
D. Franco, J. Naviner, L. Naviner
The arrival of CMOS integrated systems into nanoscale dimensions is presenting many challenges to designers and manufacturers concerning yield and reliability of integrated circuits. Traditional techniques to cope with these subjects are not as effective as they were before and many solutions are considered to allow CMOS evolution to continue according to Moore's law. Among the proposed solutions in the literature there's self-checking design and circuit reconfiguration. In the present work we introduce self-checking arithmetic operators in the design of convolution processors and we verify the penalties of such solutions in terms of area and speed. The self-checking methods considered are parity prediction, duplication and 1-out-of-3 encoding.
{"title":"Convolution Blocks Based on Self-Checking Operators","authors":"D. Franco, J. Naviner, L. Naviner","doi":"10.1109/MIXDES.2007.4286211","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286211","url":null,"abstract":"The arrival of CMOS integrated systems into nanoscale dimensions is presenting many challenges to designers and manufacturers concerning yield and reliability of integrated circuits. Traditional techniques to cope with these subjects are not as effective as they were before and many solutions are considered to allow CMOS evolution to continue according to Moore's law. Among the proposed solutions in the literature there's self-checking design and circuit reconfiguration. In the present work we introduce self-checking arithmetic operators in the design of convolution processors and we verify the penalties of such solutions in terms of area and speed. The self-checking methods considered are parity prediction, duplication and 1-out-of-3 encoding.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"44 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286195
J. Kaczmarek, A. Mazurek
In the paper an example of implementation of new, original DC/DC converter controlling concept is presented. It is designed to be used in regulators with DSP processors. Control device keeps energy accumulated in converter at steady level, and in this way indirectly forces required value of output voltage. To check the possibility of using this method in real life devices, regulators algorithm was analyzed with particular attention set on numerical complexity and duration of necessary calculations. Reference was a fixed-point 32-bit DSP processor designed for energy-electronics applications. Way of compensating influence of processors calculations duration on behavior of converter is also presented. Results of conducted research and analysis confirm possibility and attractiveness of using the method to control DC/DC converters.
{"title":"Compensation of Calculations Duration on Converters Output Voltage in Digitally Controled Converters Based on Law of Conservation of Energy - Project \"Bumblebee\"","authors":"J. Kaczmarek, A. Mazurek","doi":"10.1109/MIXDES.2007.4286195","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286195","url":null,"abstract":"In the paper an example of implementation of new, original DC/DC converter controlling concept is presented. It is designed to be used in regulators with DSP processors. Control device keeps energy accumulated in converter at steady level, and in this way indirectly forces required value of output voltage. To check the possibility of using this method in real life devices, regulators algorithm was analyzed with particular attention set on numerical complexity and duration of necessary calculations. Reference was a fixed-point 32-bit DSP processor designed for energy-electronics applications. Way of compensating influence of processors calculations duration on behavior of converter is also presented. Results of conducted research and analysis confirm possibility and attractiveness of using the method to control DC/DC converters.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286220
S. Musin, A. A. Ivaniuk, V. Yarmolik
This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.
{"title":"Self-Adjusting Output Data Compression for RAM with Word Error Detection and Correction","authors":"S. Musin, A. A. Ivaniuk, V. Yarmolik","doi":"10.1109/MIXDES.2007.4286220","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286220","url":null,"abstract":"This paper presents the reliability improvement of self-adjusting output data compression technique. Our theoretical investigation showed that compression of both address and data allows to achieve single word error detection and correction, and double word error detection. Possible built-in self-test architecture is proposed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"29 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132273447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286213
T. Garbolino, K. Gucwa, M. Kopec, A. Hlawiczka
A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at (SaX) and short types. The paper deals with the hardware that is necessary for implementing the method. The techniques for test data compression, that allow substantial reduction of data volume transferred between SoC and ATE, are also proposed.
{"title":"Crosstalk-Insensitive Method for Testing of Delay Faults in Interconnects Between Cores in SoCs","authors":"T. Garbolino, K. Gucwa, M. Kopec, A. Hlawiczka","doi":"10.1109/MIXDES.2007.4286213","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286213","url":null,"abstract":"A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at (SaX) and short types. The paper deals with the hardware that is necessary for implementing the method. The techniques for test data compression, that allow substantial reduction of data volume transferred between SoC and ATE, are also proposed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114982448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286185
T. Świa̧tczak, B. Więcek, K. Tomalczyk
This paper presents the basis of dynamic thermography, with its application to thermal parameters evaluation. The method is based on windowed FFT analysis, with special attention paid for the phasegrams interpretation. A thermal modeling of the investigated object based on lumped RC network has been made to estimate the sensitivity and accuracy of the method. Heat transfer coefficient, thermal conductivity of the material, and thickness of multilayer structure are the major parameters that can be evaluated. The proposed approach can be used mainly for electronic applications.
{"title":"Convective Cooling Evaluation of Electronic Devices using Lock-in Thermography","authors":"T. Świa̧tczak, B. Więcek, K. Tomalczyk","doi":"10.1109/MIXDES.2007.4286185","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286185","url":null,"abstract":"This paper presents the basis of dynamic thermography, with its application to thermal parameters evaluation. The method is based on windowed FFT analysis, with special attention paid for the phasegrams interpretation. A thermal modeling of the investigated object based on lumped RC network has been made to estimate the sensitivity and accuracy of the method. Heat transfer coefficient, thermal conductivity of the material, and thickness of multilayer structure are the major parameters that can be evaluated. The proposed approach can be used mainly for electronic applications.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115054615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286146
H. Fredriksson, Christer Svensson, A. Alvandpour
This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.
{"title":"A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS","authors":"H. Fredriksson, Christer Svensson, A. Alvandpour","doi":"10.1109/MIXDES.2007.4286146","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286146","url":null,"abstract":"This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130199838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：