Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548454
Seohee Kim, Saungeun Park, D. Akinwande, A. Dodabalapur
Graphene Nanoribbons (GNR) are been being investigated as they possess a bandgap in contrast to graphene sheets which have zero bandgap [1, 2]. Therefore, GNR might be more suitable as a channel material in field-effect transistors (FETs) which requires a high on/off ratio. The other electrical properties of GNR FETs apart from on/off ratio, however, are not as good as those of corresponding graphene sheet FETs. Most GNR FETs have a larger hysteresis, a lower mobility and a larger Dirac voltage than those of graphene sheet FETs. The critical factor that results in degraded performance of GNR FET is edge defects, since GNR due to their geometry have a larger number of edges per active channel width. Moreover, edges of patterned GNR from chemical vapor deposition (CVD) grown graphene do not have a perfect chirality and inevitably have more broken bonds. Thus defect passivation or amelioration assumes considerable importance if the excellent potential of GNR as a semiconducting material is to be realized. In this abstract we report the effect of polar vapors on the electrical characteristics of GNR FET, which is fabricated via patterning from CVD grown graphene monolayer sheet. Our goal is to use these as model studies in designing suitable cap layers that both protect the nanoribbons from the ambient and favorably influence, to a considerable degree, their electrical properties.
{"title":"Electrical performance enhancement of 20 nm scale graphene nanoribbon field-effect transistors with dipolar molecules","authors":"Seohee Kim, Saungeun Park, D. Akinwande, A. Dodabalapur","doi":"10.1109/DRC.2016.7548454","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548454","url":null,"abstract":"Graphene Nanoribbons (GNR) are been being investigated as they possess a bandgap in contrast to graphene sheets which have zero bandgap [1, 2]. Therefore, GNR might be more suitable as a channel material in field-effect transistors (FETs) which requires a high on/off ratio. The other electrical properties of GNR FETs apart from on/off ratio, however, are not as good as those of corresponding graphene sheet FETs. Most GNR FETs have a larger hysteresis, a lower mobility and a larger Dirac voltage than those of graphene sheet FETs. The critical factor that results in degraded performance of GNR FET is edge defects, since GNR due to their geometry have a larger number of edges per active channel width. Moreover, edges of patterned GNR from chemical vapor deposition (CVD) grown graphene do not have a perfect chirality and inevitably have more broken bonds. Thus defect passivation or amelioration assumes considerable importance if the excellent potential of GNR as a semiconducting material is to be realized. In this abstract we report the effect of polar vapors on the electrical characteristics of GNR FET, which is fabricated via patterning from CVD grown graphene monolayer sheet. Our goal is to use these as model studies in designing suitable cap layers that both protect the nanoribbons from the ambient and favorably influence, to a considerable degree, their electrical properties.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548473
Mingda Li, S. Xiao, R. Yan, S. Vishwanath, S. Fullerton‐Shirey, D. Jena, H. Xing
Tin Diselenide (SnSe2) is a two-dimensional layered crystal commonly found in octahedral coordination (1T phase). It has been reported to have a high electron affinity of around 5.1 eV and a bandgap of 1 eV [1-2], which can form staggered band alignment with tungsten diselenide (WSe2) in Thin-TFETs [3]. However, its lack of gate modulation remains a mystery [4]. In this work, we investigate the Fermi level tunability of SnSe2 by counter doping using a polymer electrolyte, PEO:CsClO4. This counter doping technique increases the on/off ratio of SnSe2 field effect transistor (FET) from 2 times to 50 times, a record high value. Meanwhile, a device model of SnSe2 FET with ion doping and subgap density of states (DOS) has been proposed to fit the experimental data. The extracted effective number of acceptor-like subgap states is as high as 4.16 × 1019 cm-3 (in comparison with near 5 × 1017 cm-3 extracted for amorphous thin-film transistors [5]). This can explain the weak Fermi level tunability of SnSe2 and direct future material development towards TFETs.
{"title":"Fermi level tunability of a novel 2D crystal: Tin Diselenide (SnSe2)","authors":"Mingda Li, S. Xiao, R. Yan, S. Vishwanath, S. Fullerton‐Shirey, D. Jena, H. Xing","doi":"10.1109/DRC.2016.7548473","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548473","url":null,"abstract":"Tin Diselenide (SnSe<sub>2</sub>) is a two-dimensional layered crystal commonly found in octahedral coordination (1T phase). It has been reported to have a high electron affinity of around 5.1 eV and a bandgap of 1 eV [1-2], which can form staggered band alignment with tungsten diselenide (WSe<sub>2</sub>) in Thin-TFETs [3]. However, its lack of gate modulation remains a mystery [4]. In this work, we investigate the Fermi level tunability of SnSe<sub>2</sub> by counter doping using a polymer electrolyte, PEO:CsClO<sub>4</sub>. This counter doping technique increases the on/off ratio of SnSe<sub>2</sub> field effect transistor (FET) from 2 times to 50 times, a record high value. Meanwhile, a device model of SnSe<sub>2</sub> FET with ion doping and subgap density of states (DOS) has been proposed to fit the experimental data. The extracted effective number of acceptor-like subgap states is as high as 4.16 × 10<sup>19</sup> cm<sup>-3</sup> (in comparison with near 5 × 10<sup>17</sup> cm<sup>-3</sup> extracted for amorphous thin-film transistors [5]). This can explain the weak Fermi level tunability of SnSe<sub>2</sub> and direct future material development towards TFETs.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548404
J. Moon, H. Seo, K. Son, Jack A. Crowell, D. Le, D. Zehnder
In this talk, we report on GeTe RF switches on silicon substrate with state-of-the-art switch figure-of-merit of ~14 femtosecond or 11 THz, ~20x greater than all of current FET switches. This was accomplished using an embedded refractory micro-heater with reduced parasitics. The spectral responses of the GeTe-based RF switches were tested for the first time under W-CDMA signals. With a 15 dBm interferer, we did not see spectral regrowth of the switches. Under single tone, the harmonic powers were at 90 dBc at 35 dBm with GeTe width of 150 μm. While at a very early development stage, we report that GeTe PCM RF switches are a promising technology upon improved reliability for future wireless RF front-ends.
{"title":"Phase-change materials for reconfigurable RF applications","authors":"J. Moon, H. Seo, K. Son, Jack A. Crowell, D. Le, D. Zehnder","doi":"10.1109/DRC.2016.7548404","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548404","url":null,"abstract":"In this talk, we report on GeTe RF switches on silicon substrate with state-of-the-art switch figure-of-merit of ~14 femtosecond or 11 THz, ~20x greater than all of current FET switches. This was accomplished using an embedded refractory micro-heater with reduced parasitics. The spectral responses of the GeTe-based RF switches were tested for the first time under W-CDMA signals. With a 15 dBm interferer, we did not see spectral regrowth of the switches. Under single tone, the harmonic powers were at 90 dBc at 35 dBm with GeTe width of 150 μm. While at a very early development stage, we report that GeTe PCM RF switches are a promising technology upon improved reliability for future wireless RF front-ends.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548449
F. M. Bayat, X. Guo, M. Klachko, N. Do, K. Likharev, D. Strukov
High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cell's dynamics, fitted to experimental results. The algorithm has allowed tuning of each cell of a 100-cell array to any desired state within a 4-orders-of-magnitude dynamic range. With 10 write pulses, the average tuning accuracy is about 3%, while with 35 pulses the precision reaches ~0.3%. Taking into account the dynamic range, the last number is equivalent to ~1,500 levels, i.e. 10+ bits.
{"title":"Model-based high-precision tuning of NOR flash memory cells for analog computing applications","authors":"F. M. Bayat, X. Guo, M. Klachko, N. Do, K. Likharev, D. Strukov","doi":"10.1109/DRC.2016.7548449","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548449","url":null,"abstract":"High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cell's dynamics, fitted to experimental results. The algorithm has allowed tuning of each cell of a 100-cell array to any desired state within a 4-orders-of-magnitude dynamic range. With 10 write pulses, the average tuning accuracy is about 3%, while with 35 pulses the precision reaches ~0.3%. Taking into account the dynamic range, the last number is equivalent to ~1,500 levels, i.e. 10+ bits.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129795208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548420
A. Sampath, Y. Chen, J. Smith, S. Kelley, J. Schuster, G. Garret, H. Shen, J. Campbell, M. Wraback, M. Reed
High sensitivity deep ultraviolet (DUV) photodetectors operating at wavelengths shorter than 280 nm are useful for various applications, including chemical and biological identification, optical wireless communications, and UV sensing systems (1). While semiconductor avalanche photodiodes (APDs) can be more compact, lower cost and more rugged than the commonly used photomultiplier tubes (PMTs), commercially available devices such as silicon (Si) single photon counting APDs have poor DUV single photon detection efficiency. In contrast, silicon carbide (SiC) APDs are ideal for high-sensitivity detection applications, as they can possess very low dark currents, small k factor, and high gain (2). However, the responsivity of these devices diminishes at wavelengths shorter than 260 nm due to increasing absorption and carrier generation in the top doped layer of this device, the short diffusion length of minority carriers in this region, and the presence of a high density of surface states.
{"title":"Deep ultraviolet enhanced silicon carbide avalanche photodiodes","authors":"A. Sampath, Y. Chen, J. Smith, S. Kelley, J. Schuster, G. Garret, H. Shen, J. Campbell, M. Wraback, M. Reed","doi":"10.1109/DRC.2016.7548420","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548420","url":null,"abstract":"High sensitivity deep ultraviolet (DUV) photodetectors operating at wavelengths shorter than 280 nm are useful for various applications, including chemical and biological identification, optical wireless communications, and UV sensing systems (1). While semiconductor avalanche photodiodes (APDs) can be more compact, lower cost and more rugged than the commonly used photomultiplier tubes (PMTs), commercially available devices such as silicon (Si) single photon counting APDs have poor DUV single photon detection efficiency. In contrast, silicon carbide (SiC) APDs are ideal for high-sensitivity detection applications, as they can possess very low dark currents, small k factor, and high gain (2). However, the responsivity of these devices diminishes at wavelengths shorter than 260 nm due to increasing absorption and carrier generation in the top doped layer of this device, the short diffusion length of minority carriers in this region, and the presence of a high density of surface states.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548456
Jun Z. Huang, P. Long, M. Povolotskyi, M. Rodwell, Gerhard Klimeck
Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (ION). Tunneling field-effect transistors (TFETs) can meet the first requirement but their ION is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost ION is doping engineering. In particular (1)lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design, or inserting a δ doping layer, can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve ION of the SP design without having to increase Np.
{"title":"Exploring channel doping designs for high-performance tunneling FETs","authors":"Jun Z. Huang, P. Long, M. Povolotskyi, M. Rodwell, Gerhard Klimeck","doi":"10.1109/DRC.2016.7548456","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548456","url":null,"abstract":"Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (ION). Tunneling field-effect transistors (TFETs) can meet the first requirement but their ION is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost ION is doping engineering. In particular (1)lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design, or inserting a δ doping layer, can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve ION of the SP design without having to increase Np.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132489578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548516
J. Khurgin
Summary form only given. It has been half a century since the photons have been portended to supplant electrons in information transmission, storage, and processing. While spectacular successes have been achieved in optical communications and these advances are slowly working their way into the chip-scale optical interconnects, optical memories have not displaced magnetic storage and are now losing ground to the all-electronic flash memories, and, in information processing the competitive all-optical switching schemes have never materialized. The fundamental reason for these facts is crystal clear - unlike electrons, photons are bosons that do not have charge and are not subjected to Pauli principle, and hence they are ideally suited for the unhindered propagation over spectacular distances while requiring quite an effort in order to be switched. We confirm this intuitive understanding by comparing switching powers, speeds and noise of electronic and photonic devices, such as modulators, all optical switches and buffers. At the same time we show that in terms of loss and bandwidth photons are unmatchable for information transmission even over the shortest of distances and cannot be replaced by any known entity, including currently popular plasmons. With electrons and photons having their clearly defined niches the main challenge lays in developing means for seamless connectivity between electronics and photonics.
{"title":"Finding a proper place for photons in the world full of electrons and their spins","authors":"J. Khurgin","doi":"10.1109/DRC.2016.7548516","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548516","url":null,"abstract":"Summary form only given. It has been half a century since the photons have been portended to supplant electrons in information transmission, storage, and processing. While spectacular successes have been achieved in optical communications and these advances are slowly working their way into the chip-scale optical interconnects, optical memories have not displaced magnetic storage and are now losing ground to the all-electronic flash memories, and, in information processing the competitive all-optical switching schemes have never materialized. The fundamental reason for these facts is crystal clear - unlike electrons, photons are bosons that do not have charge and are not subjected to Pauli principle, and hence they are ideally suited for the unhindered propagation over spectacular distances while requiring quite an effort in order to be switched. We confirm this intuitive understanding by comparing switching powers, speeds and noise of electronic and photonic devices, such as modulators, all optical switches and buffers. At the same time we show that in terms of loss and bandwidth photons are unmatchable for information transmission even over the shortest of distances and cannot be replaced by any known entity, including currently popular plasmons. With electrons and photons having their clearly defined niches the main challenge lays in developing means for seamless connectivity between electronics and photonics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134236620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548288
S. Datta
Technology scaling has led to unprecedented level of integration with billions of high-speed nanotransistors on a single chip reducing the cost per function. On the device technology front, with continued scaling, device engineers have achieved new transistor breakthroughs and introduced innovations at a rapid pace followed by successful launch of commercially successful products such as high performance microprocessors that power today over a billions of mobile smartphones, personal computers and massive data centers.
{"title":"Transistor innovation in the 21st century — A lesson in serendipity","authors":"S. Datta","doi":"10.1109/DRC.2016.7548288","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548288","url":null,"abstract":"Technology scaling has led to unprecedented level of integration with billions of high-speed nanotransistors on a single chip reducing the cost per function. On the device technology front, with continued scaling, device engineers have achieved new transistor breakthroughs and introduced innovations at a rapid pace followed by successful launch of commercially successful products such as high performance microprocessors that power today over a billions of mobile smartphones, personal computers and massive data centers.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548415
S. Bader, D. Jena
By serendipity, a novel feature has appeared in regrown GaN p-n junctions. When the device is exposed to atmosphere in between the growth of the n and p regions, a sheet layer of donors (primarily oxygen) incorporates at the junction interface [1,2]. This has been argued to decrease the depletion width, which boosts tunneling currents to acceptable levels for contacts to GaN LEDs [1]. While this is useful in its own right, a general analysis of the electrostatics of a sheet charge in a p-n junction yields another interesting regime not yet reported. Given sufficiently large interface charge, the n-side may enter accumulation, forcing a “spike” into an otherwise typical homojunction p-n band diagram. Such spikes may prove relevant for the design of tunnel junctions, or for homojunction gain elements (similar to the delta-doped BJTs of [3]).
{"title":"Introducing the spiked p-n junction for tunnel devices and current gain","authors":"S. Bader, D. Jena","doi":"10.1109/DRC.2016.7548415","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548415","url":null,"abstract":"By serendipity, a novel feature has appeared in regrown GaN p-n junctions. When the device is exposed to atmosphere in between the growth of the n and p regions, a sheet layer of donors (primarily oxygen) incorporates at the junction interface [1,2]. This has been argued to decrease the depletion width, which boosts tunneling currents to acceptable levels for contacts to GaN LEDs [1]. While this is useful in its own right, a general analysis of the electrostatics of a sheet charge in a p-n junction yields another interesting regime not yet reported. Given sufficiently large interface charge, the n-side may enter accumulation, forcing a “spike” into an otherwise typical homojunction p-n band diagram. Such spikes may prove relevant for the design of tunnel junctions, or for homojunction gain elements (similar to the delta-doped BJTs of [3]).","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548418
Dhritiman Bhattacharya, M. Al-Rashid, J. Atulasimha
We propose a novel, non-volatile, completely electrically controlled skyrmionic memory device that can perform two state and four state memory operations and could potentially be 400 times more energy efficient than conventional spintronic memory devices (STT-RAM).
{"title":"An energy efficient memory device based on fixed magnetic skyrmions switched with an electric field","authors":"Dhritiman Bhattacharya, M. Al-Rashid, J. Atulasimha","doi":"10.1109/DRC.2016.7548418","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548418","url":null,"abstract":"We propose a novel, non-volatile, completely electrically controlled skyrmionic memory device that can perform two state and four state memory operations and could potentially be 400 times more energy efficient than conventional spintronic memory devices (STT-RAM).","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124396114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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