Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548508
F. Dirisaglik, G. Bakan, Sadid Muneer, N. Williams, M. Akbulut, H. Silva, A. Gokirmak
Phase change memory (PCM) is a high-speed, scalable, resistive non-volatile memory technology that utilizes melting followed by rapid resolidification and annealing above glass-transition temperature to switch a small volume of phase change material to reversibly switch between conductive crystalline and resistive amorphous phases. PCM offers the potential to fill the gap between dynamic random access memory (DRAM) and flash memory with its density, speed, endurance and non-volatility. This potential can be realized with engineering of materials, devices and the electrical signals used for device operation. However, understanding of PCM is rather complicated compared to conventional solid-state devices due to changing material properties, the high temperatures involved. Furthermore, the critically important metastable materials properties, crystallization dynamics, resistance drift and transport mechanism are not well characterized yet [1]-[8].
{"title":"Electrical pump-probe characterization technique for phase change materials","authors":"F. Dirisaglik, G. Bakan, Sadid Muneer, N. Williams, M. Akbulut, H. Silva, A. Gokirmak","doi":"10.1109/DRC.2016.7548508","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548508","url":null,"abstract":"Phase change memory (PCM) is a high-speed, scalable, resistive non-volatile memory technology that utilizes melting followed by rapid resolidification and annealing above glass-transition temperature to switch a small volume of phase change material to reversibly switch between conductive crystalline and resistive amorphous phases. PCM offers the potential to fill the gap between dynamic random access memory (DRAM) and flash memory with its density, speed, endurance and non-volatility. This potential can be realized with engineering of materials, devices and the electrical signals used for device operation. However, understanding of PCM is rather complicated compared to conventional solid-state devices due to changing material properties, the high temperatures involved. Furthermore, the critically important metastable materials properties, crystallization dynamics, resistance drift and transport mechanism are not well characterized yet [1]-[8].","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129441263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548486
Hema C. P. Movva, Sangwoo Kang, A. Rai, Kyounghwa Kim, B. Fallahazad, T. Taniguchi, Kenji Watanabe, E. Tutuc, S. Banerjee
Heterostructures based on transition metal dichalcogenides (TMDs) are attractive owing to their atomically thin nature and lack of dangling bonds, thereby enabling devices with abrupt junctions. Of particular interest are tunneling devices that manifest a negative differential resistance (NDR), which can pave the path to next generation, low-power tunnel field-effect transistors (TFETs). To date, NDR in TMD heterostructures has been observed only at low temperatures [1], and without gate control [2-4]. Here, we demonstrate dual-gated heterostructures of molybdenum disulfide (MoS2)/hexagonal boron nitride (hBN)/tungsten diselenide (WSe2) which show gate-tunable NDR with a peak-to-valley current ratio (PVCR) of 1.3 at 300 K, and increasing to 2.3 at 77 K.
{"title":"Room temperature gate-tunable negative differential resistance in MoS2/hBN/WSe2 heterostructures","authors":"Hema C. P. Movva, Sangwoo Kang, A. Rai, Kyounghwa Kim, B. Fallahazad, T. Taniguchi, Kenji Watanabe, E. Tutuc, S. Banerjee","doi":"10.1109/DRC.2016.7548486","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548486","url":null,"abstract":"Heterostructures based on transition metal dichalcogenides (TMDs) are attractive owing to their atomically thin nature and lack of dangling bonds, thereby enabling devices with abrupt junctions. Of particular interest are tunneling devices that manifest a negative differential resistance (NDR), which can pave the path to next generation, low-power tunnel field-effect transistors (TFETs). To date, NDR in TMD heterostructures has been observed only at low temperatures [1], and without gate control [2-4]. Here, we demonstrate dual-gated heterostructures of molybdenum disulfide (MoS2)/hexagonal boron nitride (hBN)/tungsten diselenide (WSe2) which show gate-tunable NDR with a peak-to-valley current ratio (PVCR) of 1.3 at 300 K, and increasing to 2.3 at 77 K.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121240611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548413
S. Sant, A. Schenk, K. Moselund, H. Riel
As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter ≈ 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the Dit that still would allow a sub-thermal SS.
{"title":"Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs","authors":"S. Sant, A. Schenk, K. Moselund, H. Riel","doi":"10.1109/DRC.2016.7548413","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548413","url":null,"abstract":"As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter ≈ 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the Dit that still would allow a sub-thermal SS.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548457
Meghna G. Mankalale, Zhaoxin Liang, A. Smith, D. Mahendra, M. Jamali, Jianping Wang, S. Sapatnekar
Several emerging spintronic devices have recently been proposed, performing computation by (a) generating spin currents based on input magnet states to switch an output magnet state using Spin-Transfer Torque (STT) [1,2], (b) using multiple nanopillars to drive a domain wall (DW) that switches an output nanopillar using STT [7], and (c) using magnetoelectric (ME) switching at the input, combined with DW automotion, to switch an output state [3]. All of these devices have delays of several nanoseconds. The energy for (a) and (b) is in the range of femtoJoules, while the ME mechanism in (c) facilitates greater energy-efficiency, in the aJ range. These numbers fall some distance away from CMOS, where gate delays and switching energies are in the range of picoseconds (ps) and attoJoules (aJ), respectively.
{"title":"A fast magnetoelectric device based on current-driven domain wall propagation","authors":"Meghna G. Mankalale, Zhaoxin Liang, A. Smith, D. Mahendra, M. Jamali, Jianping Wang, S. Sapatnekar","doi":"10.1109/DRC.2016.7548457","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548457","url":null,"abstract":"Several emerging spintronic devices have recently been proposed, performing computation by (a) generating spin currents based on input magnet states to switch an output magnet state using Spin-Transfer Torque (STT) [1,2], (b) using multiple nanopillars to drive a domain wall (DW) that switches an output nanopillar using STT [7], and (c) using magnetoelectric (ME) switching at the input, combined with DW automotion, to switch an output state [3]. All of these devices have delays of several nanoseconds. The energy for (a) and (b) is in the range of femtoJoules, while the ME mechanism in (c) facilitates greater energy-efficiency, in the aJ range. These numbers fall some distance away from CMOS, where gate delays and switching energies are in the range of picoseconds (ps) and attoJoules (aJ), respectively.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116518686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548481
D. Schneider, A. Bablich, M. Lemme
Transparent conductive electrodes (TCEs) are ubiquitous and essential for photonic devices like solar cells, touchscreens and photodetectors. An increasing demand for TCEs may be met with graphene, which promises low production cost and an abundance of raw material and may enable flexible optoelectronic devices. We report amorphous silicon (a-Si:H) multispectral photodetectors with a bias-tunable maximum spectral response on rigid and flexible substrates with graphene TCEs. Electrical and optical measurements compare reasonably well to conventional devices with transparent conductive oxide (TCO) TCEs (here: ZnO:Al, [3]), reaching over 50% of their responsivity. Graphene enables flexible multispectral photodiodes, in contrast to the brittle ZnO:Al. A further decisive advantage of the graphene TCEs is a broader spectral response into the UV region, which is otherwise limited by the absorption in the ZnO:Al. Artifacts due to refraction in the 220 nm thick ZnO:Al are suppressed in the atomically thin graphene TCEs. Bilayer graphene (BLG) electrodes improve the responsivity considerably.
{"title":"Flexible graphene-/a-Si:H multispectral photodetectors","authors":"D. Schneider, A. Bablich, M. Lemme","doi":"10.1109/DRC.2016.7548481","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548481","url":null,"abstract":"Transparent conductive electrodes (TCEs) are ubiquitous and essential for photonic devices like solar cells, touchscreens and photodetectors. An increasing demand for TCEs may be met with graphene, which promises low production cost and an abundance of raw material and may enable flexible optoelectronic devices. We report amorphous silicon (a-Si:H) multispectral photodetectors with a bias-tunable maximum spectral response on rigid and flexible substrates with graphene TCEs. Electrical and optical measurements compare reasonably well to conventional devices with transparent conductive oxide (TCO) TCEs (here: ZnO:Al, [3]), reaching over 50% of their responsivity. Graphene enables flexible multispectral photodiodes, in contrast to the brittle ZnO:Al. A further decisive advantage of the graphene TCEs is a broader spectral response into the UV region, which is otherwise limited by the absorption in the ZnO:Al. Artifacts due to refraction in the 220 nm thick ZnO:Al are suppressed in the atomically thin graphene TCEs. Bilayer graphene (BLG) electrodes improve the responsivity considerably.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115960276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548476
C. Skierbiszewski, G. Muzioł, H. Turski, M. Siekacz
In this work we will make survey of different nitride based LDs designs - starting from conventional LDs with AlGaN claddings and GaN or InGaN waveguides, through LDs with GaN claddings, InGaN waveguides and AlGaN electron blocking layer (EBL) and finally we will demonstrate first aluminum free nitride LDs grown by PAMBE. For LDs without Al in the structure an increase of the LDs lifetime is expected as it was demonstrated for arsenide based LDs. In particular, the change of the material system from AlGaAs/GaAs to InGaAsP/GaAs increased the lifetime of LDs operating at 808 nm by few orders of magnitude. This change was solely attributed to elimination of, highly susceptible to oxidation, aluminum from the device structure.
{"title":"“Aluminum free nitride laser diodes grown by plasma assisted MBE”","authors":"C. Skierbiszewski, G. Muzioł, H. Turski, M. Siekacz","doi":"10.1109/DRC.2016.7548476","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548476","url":null,"abstract":"In this work we will make survey of different nitride based LDs designs - starting from conventional LDs with AlGaN claddings and GaN or InGaN waveguides, through LDs with GaN claddings, InGaN waveguides and AlGaN electron blocking layer (EBL) and finally we will demonstrate first aluminum free nitride LDs grown by PAMBE. For LDs without Al in the structure an increase of the LDs lifetime is expected as it was demonstrated for arsenide based LDs. In particular, the change of the material system from AlGaAs/GaAs to InGaAsP/GaAs increased the lifetime of LDs operating at 808 nm by few orders of magnitude. This change was solely attributed to elimination of, highly susceptible to oxidation, aluminum from the device structure.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130682941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548289
D. Ralph
Magnetic devices are a leading contender for the implementation of memory and logic technologies that are non-volatile, that can scale to high density and high speed, and that do not wear out. However, widespread application of magnetic memory and logic devices will require the development of efficient mechanisms for reorienting their magnetization using the least possible current and power. Until recently, the most-efficient known mechanism for manipulating magnetization in practical device geometries was spin-transfer torque from a spin-polarized current. However, this “conventional” spin-transfer torque faces a fundamental limit in efficiency - it can be no stronger than the equivalent of one unit of hbar angular momentum transferred per unit charge in the applied current. I will discuss recent experiments which indicate that new mechanisms based on spin-orbit interactions can be used to generate current-induced torques that are orders of magnitude more efficient than this previous limit.
{"title":"Manipulating magnetic devices with spin-orbit torques","authors":"D. Ralph","doi":"10.1109/DRC.2016.7548289","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548289","url":null,"abstract":"Magnetic devices are a leading contender for the implementation of memory and logic technologies that are non-volatile, that can scale to high density and high speed, and that do not wear out. However, widespread application of magnetic memory and logic devices will require the development of efficient mechanisms for reorienting their magnetization using the least possible current and power. Until recently, the most-efficient known mechanism for manipulating magnetization in practical device geometries was spin-transfer torque from a spin-polarized current. However, this “conventional” spin-transfer torque faces a fundamental limit in efficiency - it can be no stronger than the equivalent of one unit of hbar angular momentum transferred per unit charge in the applied current. I will discuss recent experiments which indicate that new mechanisms based on spin-orbit interactions can be used to generate current-induced torques that are orders of magnitude more efficient than this previous limit.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130425416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548414
R. Sajjad, D. Antoniadis
We present a rigorous compact model for Tunnel Field Effect Transistors (TFET) that captures all essential features including Trap Assisted Tunneling (TAT) originating from surface traps (Dit). Inclusion of the TAT accurately captures the subthreshold behavior matching well with experimental data (Fig. 1). With self-consistent channel potential, ψ and drain injection, we show that the TFET quantum capacitance, Cq and ψ are controlled by both gate and drain biases resulting in Negative Differential Resistance (NDR) for negative drain bias (Fig 2). A Landauer-formalism-based source-drain saturation function Fsd is derived that obtains the effective tunnel energy window based on ψ and also the superlinear current depending on source degeneracy. We apply the model to an In0 53Ga0 47As homojunction TFET but the model is sufficiently general to use for other device structures. The model can be used to assess TFET performance in presence of different amounts of Dit.
{"title":"A compact model for tunnel FET for all operation regimes including trap assisted tunneling","authors":"R. Sajjad, D. Antoniadis","doi":"10.1109/DRC.2016.7548414","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548414","url":null,"abstract":"We present a rigorous compact model for Tunnel Field Effect Transistors (TFET) that captures all essential features including Trap Assisted Tunneling (TAT) originating from surface traps (Dit). Inclusion of the TAT accurately captures the subthreshold behavior matching well with experimental data (Fig. 1). With self-consistent channel potential, ψ and drain injection, we show that the TFET quantum capacitance, Cq and ψ are controlled by both gate and drain biases resulting in Negative Differential Resistance (NDR) for negative drain bias (Fig 2). A Landauer-formalism-based source-drain saturation function Fsd is derived that obtains the effective tunnel energy window based on ψ and also the superlinear current depending on source degeneracy. We apply the model to an In0 53Ga0 47As homojunction TFET but the model is sufficiently general to use for other device structures. The model can be used to assess TFET performance in presence of different amounts of Dit.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548466
C. Gupta, Silvia H. Chan, Yuuki Enatsu, Anchal Agarwal, S. Keller, U. Mishra
GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al2O3) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm2 alongside enhancement mode operation (Vth = 3 V) is demonstrated.
{"title":"A novel device design to lower the on-resistance in GaN trench MOSFETs","authors":"C. Gupta, Silvia H. Chan, Yuuki Enatsu, Anchal Agarwal, S. Keller, U. Mishra","doi":"10.1109/DRC.2016.7548466","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548466","url":null,"abstract":"GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al2O3) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm2 alongside enhancement mode operation (Vth = 3 V) is demonstrated.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548409
A. Chaney, M. Qi, S. Islam, H. Xing, D. Jena
Tunnel Switch Diodes (TSDs) exhibit a S-shaped IV curve with negative differential resistance. Because of tunneling, they are able to switch between a low-current, high-resistance state (HRS) and a high-current, low-resistance state (LRS) fast, making them promising for high-speed memory. The TSD consists of a thin tunnel barrier on top of a pn junction. In the HRS state, the barrier allows only a small tunneling current through. When biased beyond a switching voltage the p-layer of the pn-junction depletes from the surface field-effect, and the surface depletion edge reaches the depletion edge of the buried pn diode. This turns the buried diode on, which floods the p-layer with electrons. Much of these electrons become trapped in the top triangular quantum well barrier, self-biasing the device. Since this state is unstable, the drop in electric field moves from p-layer to barrer, with a sudden onset of tunneling current when the TSD reaches the LRS [Fig. 1(b)]. Reducing the applied bias reverses this process and the TSD switches back to the HRS state. The switching voltage can be found with Vs = qNA(tp - xdep.)2)/2ϵsemi ϵo + tbarrier√2qϵsemiNAφs/ϵbarrierϵo, where NA is the acceptor doping concentration, xdep is the pn junction depletion width in the p-layer, tp and tbarrier are the thicknesses of the p-layer and tunneling barrier, and ϵsemi and ϵbarrier are the relative dielectric constants of p-layer and the barrier and φs is the surface potential needed to deplete the p-layer. TSDs were studied in SiO2/Si and in AlSb/GaSb heterostructures recently. Advances in GaN pn-diodes and polarization physics present an exciting opportunity to realize TSDs with new functionality. This work demonstrates GaN homojunction and heterojunction TSDs for the first time.
{"title":"GaN tunnel switch diodes","authors":"A. Chaney, M. Qi, S. Islam, H. Xing, D. Jena","doi":"10.1109/DRC.2016.7548409","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548409","url":null,"abstract":"Tunnel Switch Diodes (TSDs) exhibit a S-shaped IV curve with negative differential resistance. Because of tunneling, they are able to switch between a low-current, high-resistance state (HRS) and a high-current, low-resistance state (LRS) fast, making them promising for high-speed memory. The TSD consists of a thin tunnel barrier on top of a pn junction. In the HRS state, the barrier allows only a small tunneling current through. When biased beyond a switching voltage the p-layer of the pn-junction depletes from the surface field-effect, and the surface depletion edge reaches the depletion edge of the buried pn diode. This turns the buried diode on, which floods the p-layer with electrons. Much of these electrons become trapped in the top triangular quantum well barrier, self-biasing the device. Since this state is unstable, the drop in electric field moves from p-layer to barrer, with a sudden onset of tunneling current when the TSD reaches the LRS [Fig. 1(b)]. Reducing the applied bias reverses this process and the TSD switches back to the HRS state. The switching voltage can be found with V<sub>s</sub> = qN<sub>A</sub>(t<sub>p</sub> - x<sub>dep.</sub>)<sup>2</sup>)/2ϵ<sub>semi</sub> ϵ<sub>o</sub> + t<sub>barrier</sub>√2qϵ<sub>semi</sub>N<sub>A</sub>φ<sub>s</sub>/ϵ<sub>barrier</sub>ϵ<sub>o</sub>, where N<sub>A</sub> is the acceptor doping concentration, x<sub>dep</sub> is the pn junction depletion width in the p-layer, t<sub>p</sub> and t<sub>barrier</sub> are the thicknesses of the p-layer and tunneling barrier, and ϵ<sub>semi</sub> and ϵ<sub>barrier</sub> are the relative dielectric constants of p-layer and the barrier and φ<sub>s</sub> is the surface potential needed to deplete the p-layer. TSDs were studied in SiO<sub>2</sub>/Si and in AlSb/GaSb heterostructures recently. Advances in GaN pn-diodes and polarization physics present an exciting opportunity to realize TSDs with new functionality. This work demonstrates GaN homojunction and heterojunction TSDs for the first time.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133010461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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