Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548504
B. Juang, D. Prout, B. Liang, A. Chatziioannou, D. Huffaker
The gamma-ray spectral response of MBE-grown homoepitaxial GaSb p-i-n photodiode has been investigated. The GaSb device showed great linearity and promising energy resolution across a wide range of photon energies, confirming that GaSb can offer high stopping power, high carrier mobility and low PCE that would be advantageous for its use in gamma-ray detection.
{"title":"GaSb-based photon counting gamma-ray detectors","authors":"B. Juang, D. Prout, B. Liang, A. Chatziioannou, D. Huffaker","doi":"10.1109/DRC.2016.7548504","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548504","url":null,"abstract":"The gamma-ray spectral response of MBE-grown homoepitaxial GaSb p-i-n photodiode has been investigated. The GaSb device showed great linearity and promising energy resolution across a wide range of photon energies, confirming that GaSb can offer high stopping power, high carrier mobility and low PCE that would be advantageous for its use in gamma-ray detection.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122285224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548494
Xilai Li, Xiaopeng Duan, Y. Semenov, K. W. Kim
Here, we propose an electrical control of antiferromagnet (AFM) by utilizing the proximity interaction between a topological insulator (TI) and an AFM. Following the Bennett clocking scheme, this mechanism shows much faster switching speed and higher logic reliabilities compared to its ferromagnetic counterpart according to micro-magnetic simulations. Consequently, both switching period and power consumption are reduced by 2-3 orders of magnitude making the TI-AFM system a better candidate for spintronic applications.
{"title":"Electrically controlled switching of antiferromagnets via proximity interaction induced by topological insulator","authors":"Xilai Li, Xiaopeng Duan, Y. Semenov, K. W. Kim","doi":"10.1109/DRC.2016.7548494","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548494","url":null,"abstract":"Here, we propose an electrical control of antiferromagnet (AFM) by utilizing the proximity interaction between a topological insulator (TI) and an AFM. Following the Bennett clocking scheme, this mechanism shows much faster switching speed and higher logic reliabilities compared to its ferromagnetic counterpart according to micro-magnetic simulations. Consequently, both switching period and power consumption are reduced by 2-3 orders of magnitude making the TI-AFM system a better candidate for spintronic applications.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116510112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548484
Zhihui Cheng, Jorge A. Cardenas, Felicia A. McGuire, A. Franklin
Contact resistance is a dominant factor in the performance of field-effect transistors (FETs) from two-dimensional MoS2. Several techniques have been shown to improve carrier transport at the metal-MoS2 interface, thus lowering the contact resistance. These approaches include the use of molecular doping, different contact materials, phase transformation of MoS2 [6], and adding an interfacial oxide at the contacts. The challenges for the most effective of these techniques are that they generally require additional processing, sometimes involving very high temperatures, or the addition of materials at the metal-MoS2 interface that may lower contact resistance but still yield relatively poor FET performance. In graphene, it has been demonstrated that intentionally damaging the crystal lattice in the contact region using O2 plasma can substantially reduce the contact resistance. In this work, we examine a related contact engineering approach for MoS2 FETs by using an in situ, broad-beam ion source to modify the MoS2 lattice immediately prior to contact metal deposition. The result is a substantial improvement in key performance metrics, including contact resistance and on-Contact resistance is a dominant factor in the performance of field-effect transistors (FETs) from two-dimensional MoS2. Several techniques have been shown to improve carrier transport at the metal-MoS2 interface, thus lowering the contact resistance. These approaches include the use of molecular doping, different contact materials, phase transformation of MoS2, and adding an interfacial oxide at the contacts. The challenges for the most effective of these techniques are that they generally require additional processing, sometimes involving very high temperatures, or the addition of materials at the metal-MoS2 interface that may lower contact resistance but still yield relatively poor FET performance. In graphene, it has been demonstrated that intentionally damaging the crystal lattice in the contact region using O2 plasma can substantially reduce the contact resistance. In this work, we examine a related contact engineering approach for MoS2 FETs by using an in situ, broad-beam ion source to modify the MoS2 lattice immediately prior to contact metal deposition. The result is a substantial improvement in key performance metrics, including contact resistance and on-current.current.
{"title":"Using Ar Ion beam exposure to improve contact resistance in MoS2 FETs","authors":"Zhihui Cheng, Jorge A. Cardenas, Felicia A. McGuire, A. Franklin","doi":"10.1109/DRC.2016.7548484","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548484","url":null,"abstract":"Contact resistance is a dominant factor in the performance of field-effect transistors (FETs) from two-dimensional MoS2. Several techniques have been shown to improve carrier transport at the metal-MoS2 interface, thus lowering the contact resistance. These approaches include the use of molecular doping, different contact materials, phase transformation of MoS2 [6], and adding an interfacial oxide at the contacts. The challenges for the most effective of these techniques are that they generally require additional processing, sometimes involving very high temperatures, or the addition of materials at the metal-MoS2 interface that may lower contact resistance but still yield relatively poor FET performance. In graphene, it has been demonstrated that intentionally damaging the crystal lattice in the contact region using O2 plasma can substantially reduce the contact resistance. In this work, we examine a related contact engineering approach for MoS2 FETs by using an in situ, broad-beam ion source to modify the MoS2 lattice immediately prior to contact metal deposition. The result is a substantial improvement in key performance metrics, including contact resistance and on-Contact resistance is a dominant factor in the performance of field-effect transistors (FETs) from two-dimensional MoS2. Several techniques have been shown to improve carrier transport at the metal-MoS2 interface, thus lowering the contact resistance. These approaches include the use of molecular doping, different contact materials, phase transformation of MoS2, and adding an interfacial oxide at the contacts. The challenges for the most effective of these techniques are that they generally require additional processing, sometimes involving very high temperatures, or the addition of materials at the metal-MoS2 interface that may lower contact resistance but still yield relatively poor FET performance. In graphene, it has been demonstrated that intentionally damaging the crystal lattice in the contact region using O2 plasma can substantially reduce the contact resistance. In this work, we examine a related contact engineering approach for MoS2 FETs by using an in situ, broad-beam ion source to modify the MoS2 lattice immediately prior to contact metal deposition. The result is a substantial improvement in key performance metrics, including contact resistance and on-current.current.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128865349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548485
S. Fathipour, P. Paletti, S. Fullerton‐Shirey, A. Seabaugh
We demonstrate the first electric double layer p-i-n junction in the channel of a WSe2 field-effect transistor (FET). The measured current-voltage (I-V) characteristics have a nearly constant ideality factor over approximately three orders of magnitude in current. This is better than any prior report on WSe2. The formation technique has wide applicability across materials systems and is of particular interest for the formation of source-channel junctions in tunnel FETs in transition metal dichalcogenides (TMDs) [1]. The most ideal TMD p-n junctions formed to date have been achieved using buried gates under WSe2 by Ross [2], under MoS2 by Sutar [3], by charge transfer doping in MoS2 by Choi [4] and Li [5], and by EDL formation in MoTe2 by Xu [6]. The junction formation described in this paper does not require fabrication of additional field plates to position the ions.
{"title":"Demonstration of electric double layer p-i-n junction in WSe2","authors":"S. Fathipour, P. Paletti, S. Fullerton‐Shirey, A. Seabaugh","doi":"10.1109/DRC.2016.7548485","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548485","url":null,"abstract":"We demonstrate the first electric double layer p-i-n junction in the channel of a WSe2 field-effect transistor (FET). The measured current-voltage (I-V) characteristics have a nearly constant ideality factor over approximately three orders of magnitude in current. This is better than any prior report on WSe2. The formation technique has wide applicability across materials systems and is of particular interest for the formation of source-channel junctions in tunnel FETs in transition metal dichalcogenides (TMDs) [1]. The most ideal TMD p-n junctions formed to date have been achieved using buried gates under WSe2 by Ross [2], under MoS2 by Sutar [3], by charge transfer doping in MoS2 by Choi [4] and Li [5], and by EDL formation in MoTe2 by Xu [6]. The junction formation described in this paper does not require fabrication of additional field plates to position the ions.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129850117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548396
S. Islam, M. Qi, B. Song, K. Nomoto, V. Protasenko, Jingshan Wang, S. Rouvimov, P. Fay, H. Xing, D. Jena
This is the first demonstration of strained AlN/GaN/AlN quantum well FETs on SiC substrates. The device performance, though highly encouraging for the gate lengths used, can be significantly enhanced by scaling [4]. But significant improvements are expected by ensuring the absence of the 2D hole gas, and by exploring high temperature growth of thick AlN buffer layer on SiC. This can potentially reduce the generation of threading dislocations in the subsequent layers and enhance the FET performance, by improving the transport properties.
{"title":"First demonstration of strained AlN/GaN/AlN quantum well FETs on SiC","authors":"S. Islam, M. Qi, B. Song, K. Nomoto, V. Protasenko, Jingshan Wang, S. Rouvimov, P. Fay, H. Xing, D. Jena","doi":"10.1109/DRC.2016.7548396","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548396","url":null,"abstract":"This is the first demonstration of strained AlN/GaN/AlN quantum well FETs on SiC substrates. The device performance, though highly encouraging for the gate lengths used, can be significantly enhanced by scaling [4]. But significant improvements are expected by ensuring the absence of the 2D hole gas, and by exploring high temperature growth of thick AlN buffer layer on SiC. This can potentially reduce the generation of threading dislocations in the subsequent layers and enhance the FET performance, by improving the transport properties.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132337952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548447
F. M. Bufler, M. Frey, A. Erlebach, V. Deshpande, L. Czornomaz, V. Djara, E. O'Connor, D. Caimi, J. Fompeyrine
InGaAs devices are candidates to replace Si devices in future technology nodes due to their promising transport properties. Recently, CMOS-compatiple replacement metal gate (RMG) InGaAs-on-insulator (InGaAs-OI) FinFETs with record performance have been reported [1]. Further optimization and identification of limiting factors by TCAD simulation requires calibration and validation of the underlying device models to measurements of fundamental quantities in devices which are fabricated under similar process conditions as applied in the target technology. Key quantities are trap profiles leading to Fermi-level pinning as well as bulk and long-channel effective mobility. While such investigations have already been done for sample devices [2, 3], we report in this work corresponding measurements for RMG InGaAs-OI technology, calibrate and validate device simulation to these measurements and compare the results with previous literature.
{"title":"Theoretical and experimental analysis of capacitance and mobility in InGaAs","authors":"F. M. Bufler, M. Frey, A. Erlebach, V. Deshpande, L. Czornomaz, V. Djara, E. O'Connor, D. Caimi, J. Fompeyrine","doi":"10.1109/DRC.2016.7548447","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548447","url":null,"abstract":"InGaAs devices are candidates to replace Si devices in future technology nodes due to their promising transport properties. Recently, CMOS-compatiple replacement metal gate (RMG) InGaAs-on-insulator (InGaAs-OI) FinFETs with record performance have been reported [1]. Further optimization and identification of limiting factors by TCAD simulation requires calibration and validation of the underlying device models to measurements of fundamental quantities in devices which are fabricated under similar process conditions as applied in the target technology. Key quantities are trap profiles leading to Fermi-level pinning as well as bulk and long-channel effective mobility. While such investigations have already been done for sample devices [2, 3], we report in this work corresponding measurements for RMG InGaAs-OI technology, calibrate and validate device simulation to these measurements and compare the results with previous literature.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548446
P. Vardhan, S. Mittal, A. S. Shekhawat, S. Ganguly, U. Ganguly
Metal gate granularity (MGG) induced threshold voltage (Vt) variability is a critical process random variations for sub-20nm transistors [1]. It has been studied using either by stochastic TCAD simulations[2] or by analytical modeling of probability distribution[3]. This analytical modeling is based on the approach of finding an effective WF. This is a weighted average on the area of WFs of all the grains. The probability distribution of this effective WF is expected to be correlated with distribution of Vt. The problem with this approach is that positional randomness is ignored and the results depend only on the fraction of the area covered by a particular grain. Hence a physics based analytical model is attractive to address this issue. The electrostatics of NWFETs has been well explained and studied to model Vt and subthreshold slope (SS) are found [4] and [5]. The objective of this work is to develop an analytical model to estimate the metal gate granularity (MGG) induced Vt variability in Silicon nanowire FETs (NWFETs) using analytical solution of equilibrium electrostatics.
{"title":"Analytical modeling of metal gate granularity induced Vt variability in NWFETs","authors":"P. Vardhan, S. Mittal, A. S. Shekhawat, S. Ganguly, U. Ganguly","doi":"10.1109/DRC.2016.7548446","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548446","url":null,"abstract":"Metal gate granularity (MGG) induced threshold voltage (Vt) variability is a critical process random variations for sub-20nm transistors [1]. It has been studied using either by stochastic TCAD simulations[2] or by analytical modeling of probability distribution[3]. This analytical modeling is based on the approach of finding an effective WF. This is a weighted average on the area of WFs of all the grains. The probability distribution of this effective WF is expected to be correlated with distribution of Vt. The problem with this approach is that positional randomness is ignored and the results depend only on the fraction of the area covered by a particular grain. Hence a physics based analytical model is attractive to address this issue. The electrostatics of NWFETs has been well explained and studied to model Vt and subthreshold slope (SS) are found [4] and [5]. The objective of this work is to develop an analytical model to estimate the metal gate granularity (MGG) induced Vt variability in Silicon nanowire FETs (NWFETs) using analytical solution of equilibrium electrostatics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127403044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548445
Cheng Liu, Y. Ooi, Jing Zhang
The optical gain characteristics of AlN-delta-GaN quantum well are investigated for mid-ultraviolet (UV) lasers. The ultra-thin delta-GaN layer is inserted into AlN quantum well (QW) active region with AlN barrier layers. Large TE-polarized optical gain is achieved for AlN-delta-GaN QW structure at 253 nm. The peak emission wavelength can be adjusted by tuning the delta-GaN thickness while maintaining large optical gain for λ ~ 230-300 nm.
{"title":"Proposal of AlN-delta-GaN quantum well ultraviolet lasers","authors":"Cheng Liu, Y. Ooi, Jing Zhang","doi":"10.1109/DRC.2016.7548445","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548445","url":null,"abstract":"The optical gain characteristics of AlN-delta-GaN quantum well are investigated for mid-ultraviolet (UV) lasers. The ultra-thin delta-GaN layer is inserted into AlN quantum well (QW) active region with AlN barrier layers. Large TE-polarized optical gain is achieved for AlN-delta-GaN QW structure at 253 nm. The peak emission wavelength can be adjusted by tuning the delta-GaN thickness while maintaining large optical gain for λ ~ 230-300 nm.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548468
J. Wang, C. Youtsey, R. McCarthy, R. Reddy, L. Guido, A. Xie, E. Beam, P. Fay
GaN-based devices are of increasing importance for a wide range of system applications, such as power conversion and control, displays, and sensing in harsh environments. While dramatic progress in material quality and device performance has been achieved, several key impediments to the widespread adoption of GaN remain, including the high cost of native GaN substrates (needed to achieve low dislocation densities) and limited thermal conductance for through-substrate heat removal. Use of epitaxial lift-off to form devices on thin GaN-based films is one approach to circumvent these limitations, by enabling substrate re-use and close coupling of heatsinks to the active devices, while retaining the advantages of conventional epitaxial techniques. We report the first demonstration of single-crystal thin-film GaN Schottky diodes fabricated using large-area epitaxial lift-off as a step towards economical deployment of GaN-based electronics.
{"title":"Demonstration of thin-film GaN Schottky diodes fabricated with epitaxial lift-off","authors":"J. Wang, C. Youtsey, R. McCarthy, R. Reddy, L. Guido, A. Xie, E. Beam, P. Fay","doi":"10.1109/DRC.2016.7548468","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548468","url":null,"abstract":"GaN-based devices are of increasing importance for a wide range of system applications, such as power conversion and control, displays, and sensing in harsh environments. While dramatic progress in material quality and device performance has been achieved, several key impediments to the widespread adoption of GaN remain, including the high cost of native GaN substrates (needed to achieve low dislocation densities) and limited thermal conductance for through-substrate heat removal. Use of epitaxial lift-off to form devices on thin GaN-based films is one approach to circumvent these limitations, by enabling substrate re-use and close coupling of heatsinks to the active devices, while retaining the advantages of conventional epitaxial techniques. We report the first demonstration of single-crystal thin-film GaN Schottky diodes fabricated using large-area epitaxial lift-off as a step towards economical deployment of GaN-based electronics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122140701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548499
J. Hertzberg, A. Córcoles, M. Takita, N. Bronn, E. Magesan, M. Brink, S. Sheldon, J. Gambetta, J. Chow
Quantum computing holds the promise of a novel form of information processing in which data resides in quantum states. By exploiting superpositions and entanglement among these states, quantum logic operations are expected to far surpass conventional digital logic in certain classes of problems. To realize this prospect, we employ superconducting circuits at millikelvin temperatures. The nonlinearity of a Josephson tunnel junction enables a two-level quantum system, or qubit, with excitation energy in the microwave regime. Key recent advances in such devices are the demonstration of robust and simple multi-qubit gates, the integration of superconducting qubits into arrays of four or more, and gate fidelities reaching 99%. [1,2,3].
{"title":"Building quantum logic circuits using arrays of superconducting qubits","authors":"J. Hertzberg, A. Córcoles, M. Takita, N. Bronn, E. Magesan, M. Brink, S. Sheldon, J. Gambetta, J. Chow","doi":"10.1109/DRC.2016.7548499","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548499","url":null,"abstract":"Quantum computing holds the promise of a novel form of information processing in which data resides in quantum states. By exploiting superpositions and entanglement among these states, quantum logic operations are expected to far surpass conventional digital logic in certain classes of problems. To realize this prospect, we employ superconducting circuits at millikelvin temperatures. The nonlinearity of a Josephson tunnel junction enables a two-level quantum system, or qubit, with excitation energy in the microwave regime. Key recent advances in such devices are the demonstration of robust and simple multi-qubit gates, the integration of superconducting qubits into arrays of four or more, and gate fidelities reaching 99%. [1,2,3].","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125038221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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