Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548467
Min-Chul Sun, M. Pan, Xiang Gao, T. Palacios
Lateral GaN transistors on Si substrates operating at voltage below 650 V are commercially available today. The main drawback of this lateral geometry is that the transistor area (and, therefore, its cost) is proportional to the breakdown voltage. In addition, numerous material interfaces are exposed to high electric fields, which reduces reliability and prevents avalanche breakdown. For higher-voltage high-current applications, the lateral-device size increases dramatically, and very high current levels are difficult to handle on just one surface. It is expected that vertical devices would reduce the die size and be more reliable as the electric field peaks far away from the surface. The most studied vertical GaN transistor, the current aperture vertical electron transistor (CAVET), has made significant progress in performance, but it still faces two challenges [1]. First, the CAVET structure requires a p-doped current blocking layer buried in the n-doped GaN layer. Fully activating the p-dopant Mg in GaN has been found very challenging and the vertical leakage current tends to be high. Second, the needs for a high quality regrowth of the AlGaN/GaN access region substantially increases the manufacturing cost. In this work, a novel vertical FET (VFET) structure on bulk GaN substrate has been developed to address the challenges of conventional power vertical GaN transistors (Fig. 1). This VFET structure does not require a p-doped GaN current-blocking layer or material regrowth. A GaN VFET with 0.5 V threshold voltage and 1011 on/off current ratio was demonstrated.
{"title":"Vertical GaN power FET on bulk GaN substrate","authors":"Min-Chul Sun, M. Pan, Xiang Gao, T. Palacios","doi":"10.1109/DRC.2016.7548467","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548467","url":null,"abstract":"Lateral GaN transistors on Si substrates operating at voltage below 650 V are commercially available today. The main drawback of this lateral geometry is that the transistor area (and, therefore, its cost) is proportional to the breakdown voltage. In addition, numerous material interfaces are exposed to high electric fields, which reduces reliability and prevents avalanche breakdown. For higher-voltage high-current applications, the lateral-device size increases dramatically, and very high current levels are difficult to handle on just one surface. It is expected that vertical devices would reduce the die size and be more reliable as the electric field peaks far away from the surface. The most studied vertical GaN transistor, the current aperture vertical electron transistor (CAVET), has made significant progress in performance, but it still faces two challenges [1]. First, the CAVET structure requires a p-doped current blocking layer buried in the n-doped GaN layer. Fully activating the p-dopant Mg in GaN has been found very challenging and the vertical leakage current tends to be high. Second, the needs for a high quality regrowth of the AlGaN/GaN access region substantially increases the manufacturing cost. In this work, a novel vertical FET (VFET) structure on bulk GaN substrate has been developed to address the challenges of conventional power vertical GaN transistors (Fig. 1). This VFET structure does not require a p-doped GaN current-blocking layer or material regrowth. A GaN VFET with 0.5 V threshold voltage and 1011 on/off current ratio was demonstrated.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116886290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548493
A. Biswas, Saurabh Tomar, A. Ionescu
This work reports for the first time the demonstration of non-volatile memory (NVM) cells using a Tunnel FETs (TFET) with high-k Al2O3/HfO2/Al2O3 dielectric stack and vertical tunneling. Vertical tunneling TFET devices are fabricated and characterized to evaluate their potential as low power memory operation. The memory cell can be programmed with voltages from -10V to -15V (p type) and show extremely stable memory hysteresis up to 106 program cycles with very low leakage. For the first time we experimentally show that, in strong contrast with FET-based NVM, the TFET memory window (VT shift) is highly stable with temperature up to 400K due to the specific band-to-band (BTB) conduction of TFETs.
{"title":"Vertical band-to-band tunneling based non-volatile memory with high-K gate stack and stable hysteresis characteristics up to 400K","authors":"A. Biswas, Saurabh Tomar, A. Ionescu","doi":"10.1109/DRC.2016.7548493","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548493","url":null,"abstract":"This work reports for the first time the demonstration of non-volatile memory (NVM) cells using a Tunnel FETs (TFET) with high-k Al2O3/HfO2/Al2O3 dielectric stack and vertical tunneling. Vertical tunneling TFET devices are fabricated and characterized to evaluate their potential as low power memory operation. The memory cell can be programmed with voltages from -10V to -15V (p type) and show extremely stable memory hysteresis up to 106 program cycles with very low leakage. For the first time we experimentally show that, in strong contrast with FET-based NVM, the TFET memory window (VT shift) is highly stable with temperature up to 400K due to the specific band-to-band (BTB) conduction of TFETs.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548474
M. Mleczko, Chaofan Zhang, H. Lee, H. Kuo, B. Magyari-Kope, Z. Shen, R. Moore, I. Fisher, Y. Nishi, E. Pop
HfSe2 is a layered semiconductor relevant for two-dimensional (2D) field effect transistors (FETs), with recent reports of a bulk band-gap comparable to Silicon (Eg ~ 1.1 eV) [1,2] and oxidation into the high-K insulator HfO2 [1,3]. However, extreme environmental sensitivity has prevented device measurements in samples below bulk (~ 20 nm) thickness [3]. Here, we present the first systematic study of HfSe2 devices, including joint computational and spectroscopic elucidation of its electronic band structure, characterization of ambient degradation, and transport measurements down to carefully encapsulated trilayers. Transistors fabricated in inert atmospheres and capped with AlOx are long-term air-stable, with comparable performance to other 2D dichalcogenide semiconductors (Ion/Ioff ~ 106, current densities ~30 μA/μm) but offering native integration with high-K HfOx dielectrics.
{"title":"Atomically-thin HfSe2 transistors with native metal oxides","authors":"M. Mleczko, Chaofan Zhang, H. Lee, H. Kuo, B. Magyari-Kope, Z. Shen, R. Moore, I. Fisher, Y. Nishi, E. Pop","doi":"10.1109/DRC.2016.7548474","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548474","url":null,"abstract":"HfSe2 is a layered semiconductor relevant for two-dimensional (2D) field effect transistors (FETs), with recent reports of a bulk band-gap comparable to Silicon (Eg ~ 1.1 eV) [1,2] and oxidation into the high-K insulator HfO2 [1,3]. However, extreme environmental sensitivity has prevented device measurements in samples below bulk (~ 20 nm) thickness [3]. Here, we present the first systematic study of HfSe2 devices, including joint computational and spectroscopic elucidation of its electronic band structure, characterization of ambient degradation, and transport measurements down to carefully encapsulated trilayers. Transistors fabricated in inert atmospheres and capped with AlOx are long-term air-stable, with comparable performance to other 2D dichalcogenide semiconductors (Ion/Ioff ~ 106, current densities ~30 μA/μm) but offering native integration with high-K HfOx dielectrics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548399
M. Guillorn, N. Loubet, C. Yeung, R. Chao, R. Muthinti, J. Demarest, R. Robison, Xin He Miao, Jingyun Zhang, T. Hook, P. Oldiges, T. Yamashita
The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process realities and contact architecture limitations. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.
{"title":"Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS","authors":"M. Guillorn, N. Loubet, C. Yeung, R. Chao, R. Muthinti, J. Demarest, R. Robison, Xin He Miao, Jingyun Zhang, T. Hook, P. Oldiges, T. Yamashita","doi":"10.1109/DRC.2016.7548399","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548399","url":null,"abstract":"The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process realities and contact architecture limitations. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548401
W. Hsu, T. Kim, H. Chou, A. Rai, M. J. Arellano-Jimenez, M. José-Yacamán, M. Palard, S. Banerjee
Ge p+/n junctions with a high B activation level ( 2x1020 cm-3) and favorable diffusion behavior (reduced junction depth are demonstrated using novel BF+ implantation. These junctions are integrated with GeO2 high-k gate stack to obtain a high on/off ratio Ge pFET with an enhancement of ON current. With the heavier mass compared to B+, BF+ may offer higher throughput for low-energy implantation applications, which can be essential for Ge FETs to suppress the short channel effect from the higher dielectric constant of Ge.
{"title":"Enhancing the performance of GepFETs using novel BF+ implantation","authors":"W. Hsu, T. Kim, H. Chou, A. Rai, M. J. Arellano-Jimenez, M. José-Yacamán, M. Palard, S. Banerjee","doi":"10.1109/DRC.2016.7548401","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548401","url":null,"abstract":"Ge p+/n junctions with a high B activation level ( 2x1020 cm-3) and favorable diffusion behavior (reduced junction depth are demonstrated using novel BF+ implantation. These junctions are integrated with GeO2 high-k gate stack to obtain a high on/off ratio Ge pFET with an enhancement of ON current. With the heavier mass compared to B+, BF+ may offer higher throughput for low-energy implantation applications, which can be essential for Ge FETs to suppress the short channel effect from the higher dielectric constant of Ge.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548490
M. Ryu, Sang Hyo Ahn, Jong‐Ryul Yang, Woo-Jae Lee, Seong‐Tae Han, Kyung Rok Kim
Terahertz (THz) imaging technology has a great potential application owing to the unique properties of THz wave that has both permeability and feature of straight [1]. Especially for real-time THz imaging detectors, field-effect transistor (FET)-based plasmonic THz detectors [2] are now being intensively developed in multi-pixel array configuration by exploiting the silicon (Si) CMOS technology advantages of low-cost and high integration density. In terms of the circuit design approach, by utilizing resistive self-mixing in the FET channel, a 0.65 THz focal plane array (FPA) detector was reported [3] and more recently, a 1 k-pixel camera has been demonstrated for a real-time THz imaging by 65-nm CMOS technology [4]. In this work, we experimentally demonstrate the real-time terahertz (THz) imaging of moving object on the conveyer belt by implementing asymmetric FET-based plasmonic 2×200 array scanner in 65-nm CMOS technology. Based on the enhanced detecting performance from our previous works [5][6], fast and uniform detection results are presented by novel device and circuit design for real-time THz imaging.
{"title":"Plasmonic 1×200 array scanner based on 65-nm CMOS asymmetric FETs for real-time terahertz","authors":"M. Ryu, Sang Hyo Ahn, Jong‐Ryul Yang, Woo-Jae Lee, Seong‐Tae Han, Kyung Rok Kim","doi":"10.1109/DRC.2016.7548490","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548490","url":null,"abstract":"Terahertz (THz) imaging technology has a great potential application owing to the unique properties of THz wave that has both permeability and feature of straight [1]. Especially for real-time THz imaging detectors, field-effect transistor (FET)-based plasmonic THz detectors [2] are now being intensively developed in multi-pixel array configuration by exploiting the silicon (Si) CMOS technology advantages of low-cost and high integration density. In terms of the circuit design approach, by utilizing resistive self-mixing in the FET channel, a 0.65 THz focal plane array (FPA) detector was reported [3] and more recently, a 1 k-pixel camera has been demonstrated for a real-time THz imaging by 65-nm CMOS technology [4]. In this work, we experimentally demonstrate the real-time terahertz (THz) imaging of moving object on the conveyer belt by implementing asymmetric FET-based plasmonic 2×200 array scanner in 65-nm CMOS technology. Based on the enhanced detecting performance from our previous works [5][6], fast and uniform detection results are presented by novel device and circuit design for real-time THz imaging.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548509
S. Nandakumar, B. Rajendran
Memristive devices are leading candidates for realizing next generation non-volatile memory [1] and brain-inspired neuromorphic computing systems [2]. However, most of these devices operate at high voltages (1-3 V) and require 100s of μA for programming. We recently demonstrated a Cu/SiO2/W memristor device, exhibiting half-integer quantum conductance states at room temperature and sub-300 mV switching [3]. In this paper we develop a physics based model for this device, capturing the observed experimental programming characteristics including its switching response, conductance quantization, and pulse response.
{"title":"Physics-based switching model for Cu/SiO2/W quantum memristor","authors":"S. Nandakumar, B. Rajendran","doi":"10.1109/DRC.2016.7548509","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548509","url":null,"abstract":"Memristive devices are leading candidates for realizing next generation non-volatile memory [1] and brain-inspired neuromorphic computing systems [2]. However, most of these devices operate at high voltages (1-3 V) and require 100s of μA for programming. We recently demonstrated a Cu/SiO2/W memristor device, exhibiting half-integer quantum conductance states at room temperature and sub-300 mV switching [3]. In this paper we develop a physics based model for this device, capturing the observed experimental programming characteristics including its switching response, conductance quantization, and pulse response.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548501
R. Kotlyar, V. Degtyarov, A. Slepko, A. Kaushik, J. Weber, S. Cea
Device modeling has been essential in discovery of innovative concepts, assessing their value proposition and in guiding the process engineering of devices to continue Moore's Law performance scaling for Metal Oxide Semiconductor Field Effect transistors (MOSFET) [1]. TCAD has traditionally relied on continuum model of transport by solving drift-diffusion (DD) equations and including band structures through effective mass descriptions. These approaches break in nanometer scale quantum devices. Higher level models of quantum transport atomistic nonequilibrium Green's function (NEGF) [2] and semiclassical Monte Carlo (MC) [3] simulations are used for assessing new materials and novel concept devices. NEGF device simulations typically do not include realistic structures and assume a simplified form of scattering. Monte-Carlo simulations account for quantum effects, for example, the source-drain tunneling, within effective quantum correction potential approaches. The corrections to the drift-diffusion model through ballistic mobility models [4] [5] and quantum corrections [6] have been used to extend TCAD simulations to scaled devices. In this talk we will use the tool box of these simulation methods to discuss various important aspects of physics in scaled devices and their impact on assessing new materials as alternative channels using TCAD modeling. We will discuss the distribution of resistance at low and high supply voltage in short devices which approach ballistic limit and discuss the implication it has on assessing advantage of Ge vs Si channel on-current performance of PMOSFET. Scaling device crossection size down to a few nanometers brings us to a modeling realm where we can count the number of atoms in a device. In this realm we typically rely on tight-binding atomistic models to capture effects of confinement in devices [2]. We will discuss the dependence of bandgaps on size of the nanowire and ultra-thin body in III-V, Si and Ge materials. Tight-binding atomistic descriptions meet their set of challenges in modeling ultra-scaled devices where the effects of interfaces and imperfections become critical to account for. We will show that using known bulk tight-binding parameters for each material alone cannot in general describe even ideal interfaces between semiconductors. We will discuss this on the example of InAs hydrostatically strained to Si interface. This brings us to use more advanced Hamiltonians, such as, for example, Extended Huckel Theory (EHT) [7], and have a close coupling between tight-binding models and ab-initio Density Functional Theory (DFT) methods. We will apply the Extended Huckel theory to model the bandstructures of bulk semiconductors and nanowires. We will show that the Huckel method is predictive in modeling the effect of confinement in nanowires. We conclude with a discussion of challenges of bridging the gap between detailed material modeling and characterization and semi-classical device level modeling.
{"title":"Device modeling challenges in the realm of overlapping physical scales: From atomistic to continuum, from coherent to diffusive transport","authors":"R. Kotlyar, V. Degtyarov, A. Slepko, A. Kaushik, J. Weber, S. Cea","doi":"10.1109/DRC.2016.7548501","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548501","url":null,"abstract":"Device modeling has been essential in discovery of innovative concepts, assessing their value proposition and in guiding the process engineering of devices to continue Moore's Law performance scaling for Metal Oxide Semiconductor Field Effect transistors (MOSFET) [1]. TCAD has traditionally relied on continuum model of transport by solving drift-diffusion (DD) equations and including band structures through effective mass descriptions. These approaches break in nanometer scale quantum devices. Higher level models of quantum transport atomistic nonequilibrium Green's function (NEGF) [2] and semiclassical Monte Carlo (MC) [3] simulations are used for assessing new materials and novel concept devices. NEGF device simulations typically do not include realistic structures and assume a simplified form of scattering. Monte-Carlo simulations account for quantum effects, for example, the source-drain tunneling, within effective quantum correction potential approaches. The corrections to the drift-diffusion model through ballistic mobility models [4] [5] and quantum corrections [6] have been used to extend TCAD simulations to scaled devices. In this talk we will use the tool box of these simulation methods to discuss various important aspects of physics in scaled devices and their impact on assessing new materials as alternative channels using TCAD modeling. We will discuss the distribution of resistance at low and high supply voltage in short devices which approach ballistic limit and discuss the implication it has on assessing advantage of Ge vs Si channel on-current performance of PMOSFET. Scaling device crossection size down to a few nanometers brings us to a modeling realm where we can count the number of atoms in a device. In this realm we typically rely on tight-binding atomistic models to capture effects of confinement in devices [2]. We will discuss the dependence of bandgaps on size of the nanowire and ultra-thin body in III-V, Si and Ge materials. Tight-binding atomistic descriptions meet their set of challenges in modeling ultra-scaled devices where the effects of interfaces and imperfections become critical to account for. We will show that using known bulk tight-binding parameters for each material alone cannot in general describe even ideal interfaces between semiconductors. We will discuss this on the example of InAs hydrostatically strained to Si interface. This brings us to use more advanced Hamiltonians, such as, for example, Extended Huckel Theory (EHT) [7], and have a close coupling between tight-binding models and ab-initio Density Functional Theory (DFT) methods. We will apply the Extended Huckel theory to model the bandstructures of bulk semiconductors and nanowires. We will show that the Huckel method is predictive in modeling the effect of confinement in nanowires. We conclude with a discussion of challenges of bridging the gap between detailed material modeling and characterization and semi-classical device level modeling.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548440
B. Song, A. Verma, K. Nomoto, M. Zhu, D. Jena, H. Xing
Owing to the large bandgap, breakdown electric field (Eb) and high carrier mobility, wide-bandgap semiconductor (e.g. SiC and GaN) based power devices have been extensively studied for next-generation power-switching applications [1-2]. Recently, a new wide-bandgap oxide semiconductor, gallium oxide (β-Ga2O3), has attracted attention for power-switching applications because it has an extremely large bandgap of 4.5~4.9 eV enabling a high breakdown voltage (Vbr) and a high Baliga's figure of merit [3]. Furthermore, large-area and high-quality bulk substrates of Ga2O3 can be grown by low-cost methods, which remains a significant challenge for both SiC and GaN. Schottky barrier diodes (SBDs), with a low turn-on voltage and a fast switching speed due to majority carrier conduction, are ideal candidates for high-power and high-speed rectifiers. Recently, Higashiwaki et al. have demonstrated excellent device results, which includes SBDs with Vbr ~115 V on (010) Ga2O3 substrates (with a net doping concentration ND-NA ~ 5×1016 cm-3) [4] and SBDs with epitaxial Si-doped n-Ga2O3 drift layers (ND-NA ~ 1.4×1016 cm-3) grown by HVPE on (001) Ga2O3 substrates with Vbr ~ 500 V [5]. Oishi et al reported Ni-based SBDs on (-201) Ga2O3 with a Nd-Na ~ 1×1017 cm-3 and Vbr ~ 40 V [6]. However, no high voltage (Vbr > 100 V) devices have been reported yet on (-201) Ga2O3, the crystal orientation readily available in up to 4 inch diameter wafer. In this work, we report Pt-based SBDs fabricated on unintentionally-doped (UID) (-201) n-type Ga2O3 substrates with Vbr > 100 V.
{"title":"Vertical Ga2O3 Schottky barrier diodes on single-crystal β-Ga2O3 (−201) substrates","authors":"B. Song, A. Verma, K. Nomoto, M. Zhu, D. Jena, H. Xing","doi":"10.1109/DRC.2016.7548440","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548440","url":null,"abstract":"Owing to the large bandgap, breakdown electric field (E<sub>b</sub>) and high carrier mobility, wide-bandgap semiconductor (e.g. SiC and GaN) based power devices have been extensively studied for next-generation power-switching applications [1-2]. Recently, a new wide-bandgap oxide semiconductor, gallium oxide (β-Ga<sub>2</sub>O<sub>3</sub>), has attracted attention for power-switching applications because it has an extremely large bandgap of 4.5~4.9 eV enabling a high breakdown voltage (V<sub>br</sub>) and a high Baliga's figure of merit [3]. Furthermore, large-area and high-quality bulk substrates of Ga<sub>2</sub>O<sub>3</sub> can be grown by low-cost methods, which remains a significant challenge for both SiC and GaN. Schottky barrier diodes (SBDs), with a low turn-on voltage and a fast switching speed due to majority carrier conduction, are ideal candidates for high-power and high-speed rectifiers. Recently, Higashiwaki et al. have demonstrated excellent device results, which includes SBDs with V<sub>br</sub> ~115 V on (010) Ga<sub>2</sub>O<sub>3</sub> substrates (with a net doping concentration N<sub>D</sub>-N<sub>A</sub> ~ 5×10<sup>16</sup> cm<sup>-3</sup>) [4] and SBDs with epitaxial Si-doped n-Ga<sub>2</sub>O<sub>3</sub> drift layers (N<sub>D</sub>-N<sub>A</sub> ~ 1.4×10<sup>16</sup> cm<sup>-3</sup>) grown by HVPE on (001) Ga<sub>2</sub>O<sub>3</sub> substrates with V<sub>br</sub> ~ 500 V [5]. Oishi et al reported Ni-based SBDs on (-201) Ga<sub>2</sub>O<sub>3</sub> with a Nd-Na ~ 1×10<sup>17</sup> cm<sup>-3</sup> and V<sub>br</sub> ~ 40 V [6]. However, no high voltage (V<sub>br</sub> > 100 V) devices have been reported yet on (-201) Ga<sub>2</sub>O<sub>3</sub>, the crystal orientation readily available in up to 4 inch diameter wafer. In this work, we report Pt-based SBDs fabricated on unintentionally-doped (UID) (-201) n-type Ga<sub>2</sub>O<sub>3</sub> substrates with V<sub>br</sub> > 100 V.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"319 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113994733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-19DOI: 10.1109/DRC.2016.7548292
J. Suda
Summary form only given. Wide-bandgap (WBG) semiconductors have attracted great attention as materials for the next-generation power devices since they have superior material properties compared to silicon (Si). The most advanced WBG semiconductor for power devices is silicon carbide (SiC). In 1987, the growth technology called “step-controlled epitaxy”, which enables single-phase (polytype) growth, was developed. In 1993-1994, SiC Schottky-barrier diodes (SBDs) which exceeds the Si material limit was demonstrated. In 2001, SiC SBDs were commercialized. Key technologies for SiC SBDs were edge termination to obtain an ideal breakdown voltage and a junction barrier Schottky (JBS) structure to suppress reverse leakage current. For power MOSFETs, it took longer time due to low channel mobility at SiO2/SiC and oxide reliability issues. Channel mobility was much improved by post-oxidation nitridation in NO or N2O ambient. Now, channel mobility and reliability are well controlled (balanced). SiC power MOSFETs as well as power modules with SiC MOSFETs and SiC SBDs, are commercially available. Last 5 years, the implementation of SiC devices into electronic vehicles and railway trains were extensively investigated, demonstrating a significant improvement of power efficiency. Gallium nitride (GaN) is another candidate for power devices. AlGaN/GaN HEMTs were originally developed for high-power high-frequency amplifiers, however in the last decade extensive development efforts were carried out on AlGaN/GaN HEMTs grown on Si substrates producing cost-effective high-efficiency power switching devices, which commercial companies have started into production. They have a great impact on consumer electronics due to their excellent performance of low on-resistance with high switching speed, which can never be realized by Si power devices. Recently, GaN vertical power devices have attracted great attention for power devices with large breakdown voltage and large current handling capability. Some of technologies of GaN HEMTs can be used for GaN vertical power devices. However, many new technologies should be developed to realize high-performance GaN vertical power devices. Here, we can learn many things from the history of SiC power devices. In this talk, the author would like to discuss challenges for GaN vertical power devices by referring SiC technologies. It is interesting that some of challenges are easy for SiC but very tough for GaN, and vice versa.
{"title":"SiC and GaN from the viewpoint of vertical power devices","authors":"J. Suda","doi":"10.1109/DRC.2016.7548292","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548292","url":null,"abstract":"Summary form only given. Wide-bandgap (WBG) semiconductors have attracted great attention as materials for the next-generation power devices since they have superior material properties compared to silicon (Si). The most advanced WBG semiconductor for power devices is silicon carbide (SiC). In 1987, the growth technology called “step-controlled epitaxy”, which enables single-phase (polytype) growth, was developed. In 1993-1994, SiC Schottky-barrier diodes (SBDs) which exceeds the Si material limit was demonstrated. In 2001, SiC SBDs were commercialized. Key technologies for SiC SBDs were edge termination to obtain an ideal breakdown voltage and a junction barrier Schottky (JBS) structure to suppress reverse leakage current. For power MOSFETs, it took longer time due to low channel mobility at SiO2/SiC and oxide reliability issues. Channel mobility was much improved by post-oxidation nitridation in NO or N2O ambient. Now, channel mobility and reliability are well controlled (balanced). SiC power MOSFETs as well as power modules with SiC MOSFETs and SiC SBDs, are commercially available. Last 5 years, the implementation of SiC devices into electronic vehicles and railway trains were extensively investigated, demonstrating a significant improvement of power efficiency. Gallium nitride (GaN) is another candidate for power devices. AlGaN/GaN HEMTs were originally developed for high-power high-frequency amplifiers, however in the last decade extensive development efforts were carried out on AlGaN/GaN HEMTs grown on Si substrates producing cost-effective high-efficiency power switching devices, which commercial companies have started into production. They have a great impact on consumer electronics due to their excellent performance of low on-resistance with high switching speed, which can never be realized by Si power devices. Recently, GaN vertical power devices have attracted great attention for power devices with large breakdown voltage and large current handling capability. Some of technologies of GaN HEMTs can be used for GaN vertical power devices. However, many new technologies should be developed to realize high-performance GaN vertical power devices. Here, we can learn many things from the history of SiC power devices. In this talk, the author would like to discuss challenges for GaN vertical power devices by referring SiC technologies. It is interesting that some of challenges are easy for SiC but very tough for GaN, and vice versa.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"38 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127830521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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