Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726040
A. Choudhary, S. K. Nagar
This paper presents a direct truncation methodology for reducing the order of large scale interval systems. The algorithm is computationally simple, and intuitively appealing. Numerical examples illustrating the effectiveness of the proposed method are included.
{"title":"Direct truncation method for order reduction of discrete interval system","authors":"A. Choudhary, S. K. Nagar","doi":"10.1109/INDCON.2013.6726040","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726040","url":null,"abstract":"This paper presents a direct truncation methodology for reducing the order of large scale interval systems. The algorithm is computationally simple, and intuitively appealing. Numerical examples illustrating the effectiveness of the proposed method are included.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726069
P. Borkar, J. Kalambe, R. Patrikar
Microcantilveres are important micomachined components used in many applications. Modeling, simulation and fabrication of a microcantilever designed to achieve less actuation voltage and response time for electrostatically actuated microcantilever based device is presented in this paper. The effects of various design parameters and materials on sensitivity and response time of the microcantilever is investigated. The sensitivity of a microcantilever beam is studied by varying physical parameters of cantilever such as length, width and thickness. Results indicate that for a fixed displacement of 1um between top beam and bottom electrode, increasing microcantilever beam thickness increased the actuation voltage on the other hand an increase in the length of the microcantilever decreases the actuation voltage. Simulations were also done to study the effects of varying physical properties such as length and thickness on response time. It was observed that length and thickness of beam tends to be the most influencing parameters for actuation voltage and response time, which needs to be tightly controlled. Polysilicon microcantilever is fabricated with surface micromachining technology. The simulated values of pull in voltage and response time are experimentally validated on the fabricated device. A comparison between simulation and experimental results for response time showed close agreement.
{"title":"Impact of design parameters on actuation voltage and response time for micro-cantilever based device","authors":"P. Borkar, J. Kalambe, R. Patrikar","doi":"10.1109/INDCON.2013.6726069","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726069","url":null,"abstract":"Microcantilveres are important micomachined components used in many applications. Modeling, simulation and fabrication of a microcantilever designed to achieve less actuation voltage and response time for electrostatically actuated microcantilever based device is presented in this paper. The effects of various design parameters and materials on sensitivity and response time of the microcantilever is investigated. The sensitivity of a microcantilever beam is studied by varying physical parameters of cantilever such as length, width and thickness. Results indicate that for a fixed displacement of 1um between top beam and bottom electrode, increasing microcantilever beam thickness increased the actuation voltage on the other hand an increase in the length of the microcantilever decreases the actuation voltage. Simulations were also done to study the effects of varying physical properties such as length and thickness on response time. It was observed that length and thickness of beam tends to be the most influencing parameters for actuation voltage and response time, which needs to be tightly controlled. Polysilicon microcantilever is fabricated with surface micromachining technology. The simulated values of pull in voltage and response time are experimentally validated on the fabricated device. A comparison between simulation and experimental results for response time showed close agreement.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6725967
Mohd Ayyub Khan, A. A. Moinuddin, E. Khan
In this paper, an optimized unequal error protection scheme using Forward Error Correction (FEC) for transmission of embedded video bitstream over AWGN channel is investigated. The scheme exploits the non-uniform importance and error sensitivity of the bits generated by the a wavelet video coder. Depending upon their importance in the reconstruction of the video, the bitstream is first divided into High Priority (HP) and Low Priority (LP) substreams. Then appropriate FEC is applied to these substreams to protect them against the channel errors. The optimal FEC parameters are searched using an offline optimization technique subject to constraint that end-to-end transmission distortion is minimized. A look-up table with optimal FEC parameters for wide range of channel conditions, is designed. Furthermore, this paper also argues that whether optimized UEP has any advantage over EEP for protection of embedded bitstream. This scheme is suitable for real-time video communication using portable devices which possess low processing capabilities and small battery power.
{"title":"Unequal error protection of embedded video bitstream with optimized FEC","authors":"Mohd Ayyub Khan, A. A. Moinuddin, E. Khan","doi":"10.1109/INDCON.2013.6725967","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6725967","url":null,"abstract":"In this paper, an optimized unequal error protection scheme using Forward Error Correction (FEC) for transmission of embedded video bitstream over AWGN channel is investigated. The scheme exploits the non-uniform importance and error sensitivity of the bits generated by the a wavelet video coder. Depending upon their importance in the reconstruction of the video, the bitstream is first divided into High Priority (HP) and Low Priority (LP) substreams. Then appropriate FEC is applied to these substreams to protect them against the channel errors. The optimal FEC parameters are searched using an offline optimization technique subject to constraint that end-to-end transmission distortion is minimized. A look-up table with optimal FEC parameters for wide range of channel conditions, is designed. Furthermore, this paper also argues that whether optimized UEP has any advantage over EEP for protection of embedded bitstream. This scheme is suitable for real-time video communication using portable devices which possess low processing capabilities and small battery power.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128858359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726012
S. G. Kambalimath, P. C. Pandey, P. N. Kulkarni, S. Mahant-Shetti, Sangmesh G. Hiremath
Sensorineural hearing impairment is associated with decreased speech perception due to increased intraspeech spectral masking. For persons with moderate bilateral sensorineural loss, binaural dichotic presentation using a pair of complementary comb filters can reduce the effects of increased intraspeech spectral masking and thereby improve speech perception. It has been earlier shown that use of comb filters based on auditory critical bandwidths, with magnitude responses designed for perceptual balance of loudness and linear phase responses, resulted in a significant improvement in speech perception without adversely affecting localization of broadband sound sources. An FPGA-based implementation of these 513-coefficient filters with sampling frequency of 10 kHz is carried out for use in binaural hearing aids. Implementation using a 16bit codec and 15-bit integer filter coefficients used 47%, 34%, and 53% of combinational functions, logic registers, and logic elements, respectively, available on “Altera Cyclone II EP2C70F896C6” FPGA. The resulting magnitude responses have a close match to the offline floating-point implementation.
感音神经性听力障碍与由于语音频谱掩蔽增加而导致的语音感知下降有关。对于中度双侧感觉神经丧失的患者，使用一对互补梳状滤波器的双耳二分呈现可以减少增加的语音频谱掩蔽的影响，从而改善语音感知。先前已有研究表明，使用基于听觉临界带宽的梳状滤波器，其幅度响应设计用于响度和线性相位响应的感知平衡，可以显著改善语音感知，而不会对宽带声源的定位产生不利影响。基于fpga的513系数滤波器的实现，采样频率为10 kHz，用于双耳助听器。使用16位编解码器和15位整数滤波器系数的实现分别使用47%，34%和53%的组合功能，逻辑寄存器和逻辑元件，可在Altera Cyclone II EP2C70F896C6 FPGA上获得。得到的幅度响应与脱机浮点实现非常接近。
{"title":"FPGA based implementation of comb filters for use in binaural hearing aids for reducing intraspeech spectral masking","authors":"S. G. Kambalimath, P. C. Pandey, P. N. Kulkarni, S. Mahant-Shetti, Sangmesh G. Hiremath","doi":"10.1109/INDCON.2013.6726012","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726012","url":null,"abstract":"Sensorineural hearing impairment is associated with decreased speech perception due to increased intraspeech spectral masking. For persons with moderate bilateral sensorineural loss, binaural dichotic presentation using a pair of complementary comb filters can reduce the effects of increased intraspeech spectral masking and thereby improve speech perception. It has been earlier shown that use of comb filters based on auditory critical bandwidths, with magnitude responses designed for perceptual balance of loudness and linear phase responses, resulted in a significant improvement in speech perception without adversely affecting localization of broadband sound sources. An FPGA-based implementation of these 513-coefficient filters with sampling frequency of 10 kHz is carried out for use in binaural hearing aids. Implementation using a 16bit codec and 15-bit integer filter coefficients used 47%, 34%, and 53% of combinational functions, logic registers, and logic elements, respectively, available on “Altera Cyclone II EP2C70F896C6” FPGA. The resulting magnitude responses have a close match to the offline floating-point implementation.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133825543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6725910
R. Dhavse, Fyroos Muhammed, Chetna Sinha, V. Mishra, R. Patrikar
Tox scaling, which is otherwise saturated, is expected to get improved by the use of quantum dots in the floating gate layer of flash memory devices. Silicon quantum dots serve the task of multiple charge storage nodes and allow the use of ultra-thin tunnel oxides. Here, conventional Floating Gate Metal Oxide Semiconductor (FGMOS) gate stack capacitor is compared with similar structure where silicon nanocrystals are embedded in a thin oxide layer to behave like a floating gate. Their C-V curves exhibit similar memory effects. In this work, oxide thickness of 3.3 nm is used for target technology of 65 nm. Device threshold of 0.2 V is obtained with supply voltage of 1 V. The structures exhibit significant memory window with tunneling voltages as less as 12 V for a 65 nm device. All the simulations are performed using Sentaurus TCAD tools.
{"title":"Memory characteristics of a 65 nm FGMOS capacitor with Si quantum dots as floating gates","authors":"R. Dhavse, Fyroos Muhammed, Chetna Sinha, V. Mishra, R. Patrikar","doi":"10.1109/INDCON.2013.6725910","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6725910","url":null,"abstract":"Tox scaling, which is otherwise saturated, is expected to get improved by the use of quantum dots in the floating gate layer of flash memory devices. Silicon quantum dots serve the task of multiple charge storage nodes and allow the use of ultra-thin tunnel oxides. Here, conventional Floating Gate Metal Oxide Semiconductor (FGMOS) gate stack capacitor is compared with similar structure where silicon nanocrystals are embedded in a thin oxide layer to behave like a floating gate. Their C-V curves exhibit similar memory effects. In this work, oxide thickness of 3.3 nm is used for target technology of 65 nm. Device threshold of 0.2 V is obtained with supply voltage of 1 V. The structures exhibit significant memory window with tunneling voltages as less as 12 V for a 65 nm device. All the simulations are performed using Sentaurus TCAD tools.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115449173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726014
Rahul Jain, Joy Bose, T. Arif
In this paper we propose a framework to adapt the user interface (UI) of mobile computing devices like smartphones or tablets, based on the context or scenario in which user is present, and incorporating learning from past user actions. This will allow the user to perform actions in minimal steps and also reduce the clutter. The user interface in question can include application icons, menus, buttons window positioning or layout, color scheme and so on. The framework profiles the user device usage pattern and uses machine learning algorithms to predict the best possible screen configuration with respect to the user context. The prediction will improve with time and will provide best user experience possible to the user. To predict the utility of our model, we measure average response times for a number of users to access certain applications randomly on a smartphone, and on that basis predict time saved by adapting the UI in this way.
{"title":"Contextual adaptive user interface for Android devices","authors":"Rahul Jain, Joy Bose, T. Arif","doi":"10.1109/INDCON.2013.6726014","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726014","url":null,"abstract":"In this paper we propose a framework to adapt the user interface (UI) of mobile computing devices like smartphones or tablets, based on the context or scenario in which user is present, and incorporating learning from past user actions. This will allow the user to perform actions in minimal steps and also reduce the clutter. The user interface in question can include application icons, menus, buttons window positioning or layout, color scheme and so on. The framework profiles the user device usage pattern and uses machine learning algorithms to predict the best possible screen configuration with respect to the user context. The prediction will improve with time and will provide best user experience possible to the user. To predict the utility of our model, we measure average response times for a number of users to access certain applications randomly on a smartphone, and on that basis predict time saved by adapting the UI in this way.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6725859
J. Sandhya, V. B. Raju
In analyzing the electrical networks power flow solution is very essential. There are numerous power flow models for transmission as well as distribution systems. It is also evident from the literatures that several new models exclusively for distribution networks are being developed. It is suggested here that instead of having many models, the models applied for transmission networks can be applied to distribution networks with some modifications. This paper presents the study of several transmission and distribution power systems to explore applicability of the Constant Complex Matrix Power Flow Model (CCMPFM) [1] and also gives comparison with General Purpose Fast Decoupled Power Flow (GFDPF) model [3]. The results demonstrate that the CCMPF model possess more stable convergence for both well-behaved and ill-conditioned systems when compared to GFDPF. This model has strong convergence characteristics for distribution networks also when compared to Stott's model. This CCMPF model can be applied for transmission networks, stand alone radial as well as weakly meshed distribution networks. Also the whole interconnection of transmission and distribution network is studied with one single model and good converging results are obtained. From the results, this paper suggests that a single power flow model is sufficient for studying the entire electric power network right from the generation point to load point without many models.
{"title":"General Purpose Efficient power flow model representation of network from generation bus to load bus","authors":"J. Sandhya, V. B. Raju","doi":"10.1109/INDCON.2013.6725859","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6725859","url":null,"abstract":"In analyzing the electrical networks power flow solution is very essential. There are numerous power flow models for transmission as well as distribution systems. It is also evident from the literatures that several new models exclusively for distribution networks are being developed. It is suggested here that instead of having many models, the models applied for transmission networks can be applied to distribution networks with some modifications. This paper presents the study of several transmission and distribution power systems to explore applicability of the Constant Complex Matrix Power Flow Model (CCMPFM) [1] and also gives comparison with General Purpose Fast Decoupled Power Flow (GFDPF) model [3]. The results demonstrate that the CCMPF model possess more stable convergence for both well-behaved and ill-conditioned systems when compared to GFDPF. This model has strong convergence characteristics for distribution networks also when compared to Stott's model. This CCMPF model can be applied for transmission networks, stand alone radial as well as weakly meshed distribution networks. Also the whole interconnection of transmission and distribution network is studied with one single model and good converging results are obtained. From the results, this paper suggests that a single power flow model is sufficient for studying the entire electric power network right from the generation point to load point without many models.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"60 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124320014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6725950
Baisakhi Maity, A. Kundu, I. S. Misra, S. Sanyal
In today's world 70-90% wireless communication occurs inside the building area. However, due to high wallpenetration loss the signal quality falls below the desired level. Therefore, low power femto base stations are deployed inside the buildings to enhance the indoor coverage and signal strength. In this paper, we have considered a building area located at the cell edge. In the first part of the paper, we have observed the variation of signal to interference plus noise ratio (SINR), packet loss rate and throughput for varied user density and number of channels. However, a huge number of femto cells may create significant amount of interference. Hence, the effect of the interference scenario is discussed and a power optimization algorithm to reduce the cross layer interference is proposed in the rest of the paper. After deploying power optimized femto cells, it is observed that the signal quality within the building has improved significantly.
{"title":"Coverage extension and power optimization for closed group femto cells in BWA network","authors":"Baisakhi Maity, A. Kundu, I. S. Misra, S. Sanyal","doi":"10.1109/INDCON.2013.6725950","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6725950","url":null,"abstract":"In today's world 70-90% wireless communication occurs inside the building area. However, due to high wallpenetration loss the signal quality falls below the desired level. Therefore, low power femto base stations are deployed inside the buildings to enhance the indoor coverage and signal strength. In this paper, we have considered a building area located at the cell edge. In the first part of the paper, we have observed the variation of signal to interference plus noise ratio (SINR), packet loss rate and throughput for varied user density and number of channels. However, a huge number of femto cells may create significant amount of interference. Hence, the effect of the interference scenario is discussed and a power optimization algorithm to reduce the cross layer interference is proposed in the rest of the paper. After deploying power optimized femto cells, it is observed that the signal quality within the building has improved significantly.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124557593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726009
I. V. Singh, M. S. Alam
This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “Tsi”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain Av, IP3, maximum oscillation frequency fMAX and dc power consumption PDC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of fMAX, Av and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (Ion/Ioff) as specified in current International Technology Road map for Semiconductors (ITRS).
{"title":"Linearity characterization of nano-scale underlap SOI MOSFETs","authors":"I. V. Singh, M. S. Alam","doi":"10.1109/INDCON.2013.6726009","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726009","url":null,"abstract":"This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “T<sub>si</sub>”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain A<sub>v</sub>, IP3, maximum oscillation frequency f<sub>MAX</sub> and dc power consumption P<sub>DC</sub>, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of f<sub>MAX</sub>, A<sub>v</sub> and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (I<sub>on</sub>/I<sub>off</sub>) as specified in current International Technology Road map for Semiconductors (ITRS).","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114913923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/INDCON.2013.6726032
Tsepo Sadeq Montsi, A. Mishra
Recent works indicate that through the non-invasive application of low current waveforms to the brain, systems implementing both cortical stimulation (Transcranial Direct Current Stimulation) and imaging (Electrical Impedance Tomography) with a high degree of accuracy and effectiveness can be realised. Safety and physical constraints along with the individually unique and fractal-like functional, structural and electrical complexity of the brain and surrounding cranial tissue hinders legacy systems from achieving enough precision and effectiveness for neurological treatment and investigation. This paper describes a novel system capable of achieving both stimulation and imaging while also ameliorating the shortcomings of legacy systems. Both these functions require multiple independently controlled electrodes distributed on the scalp and have complimentary functional requirements, therefore minimal additional resources are required to achieve both goals. Meeting these requirements also result in the ability to improve on legacy modalities. The system exceeds all appropriate safety requirements and is implemented with a modular architecture enabling cascading of the hardware such that the system capability and cost can be scaled according to the requirements of the application. While resource constraints precluded meeting critical functional requirements, tests and simulation of the subsystems proved the concept justifying further development.
{"title":"Multielectrode system for transcranial stimulation and impedance imaging","authors":"Tsepo Sadeq Montsi, A. Mishra","doi":"10.1109/INDCON.2013.6726032","DOIUrl":"https://doi.org/10.1109/INDCON.2013.6726032","url":null,"abstract":"Recent works indicate that through the non-invasive application of low current waveforms to the brain, systems implementing both cortical stimulation (Transcranial Direct Current Stimulation) and imaging (Electrical Impedance Tomography) with a high degree of accuracy and effectiveness can be realised. Safety and physical constraints along with the individually unique and fractal-like functional, structural and electrical complexity of the brain and surrounding cranial tissue hinders legacy systems from achieving enough precision and effectiveness for neurological treatment and investigation. This paper describes a novel system capable of achieving both stimulation and imaging while also ameliorating the shortcomings of legacy systems. Both these functions require multiple independently controlled electrodes distributed on the scalp and have complimentary functional requirements, therefore minimal additional resources are required to achieve both goals. Meeting these requirements also result in the ability to improve on legacy modalities. The system exceeds all appropriate safety requirements and is implemented with a modular architecture enabling cascading of the hardware such that the system capability and cost can be scaled according to the requirements of the application. While resource constraints precluded meeting critical functional requirements, tests and simulation of the subsystems proved the concept justifying further development.","PeriodicalId":313185,"journal":{"name":"2013 Annual IEEE India Conference (INDICON)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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