Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706625
M. Masar, M. Tomáška, M. Klasovitý
We present fast, robust and accurate method for field-effect transistor small-signal equivalent circuit identification. Transistor is characterized using measured S-parameters in the microwave range at every bias point of interest. All extrinsic parasitic elements are determined using single set of measured data at the pinched coldfet state. Intrinsic parameters are estimated at every bias point using analytical expression and then fine-tuned via optimization. The procedure was implemented in MATLAB as the fully automated tool, which does not require the user interaction. This makes it suitable as a first step for large-signal modeling, where large amount of small-signal circuits has to be extracted
{"title":"Fast And Accurate Method For Small-signal Fet Equivalent Circuit Identification","authors":"M. Masar, M. Tomáška, M. Klasovitý","doi":"10.1109/MIXDES.2006.1706625","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706625","url":null,"abstract":"We present fast, robust and accurate method for field-effect transistor small-signal equivalent circuit identification. Transistor is characterized using measured S-parameters in the microwave range at every bias point of interest. All extrinsic parasitic elements are determined using single set of measured data at the pinched coldfet state. Intrinsic parameters are estimated at every bias point using analytical expression and then fine-tuned via optimization. The procedure was implemented in MATLAB as the fully automated tool, which does not require the user interaction. This makes it suitable as a first step for large-signal modeling, where large amount of small-signal circuits has to be extracted","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706637
R. Banchuin, B. Chipipop, B. Sirinaovakul
In this research, we have studied the practical OTA-based floating inductor and propose its complete passive equivalent circuit where the finite bandwidth effect which used to be neglected in the previous work is now included. Furthermore, we also propose the accuracy evaluation of this passive equivalent circuit by comparing it with the target active OTA-based floating inductor. Finally, we mention our further studies which are the inclusion of the mismatch among each OTA and the modelling of the passive equivalent circuit of the other type of the OTA-based floating inductor
{"title":"The Complete Passive Equivalent Circuit Of The Practical OTA-based Floating Inductor","authors":"R. Banchuin, B. Chipipop, B. Sirinaovakul","doi":"10.1109/MIXDES.2006.1706637","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706637","url":null,"abstract":"In this research, we have studied the practical OTA-based floating inductor and propose its complete passive equivalent circuit where the finite bandwidth effect which used to be neglected in the previous work is now included. Furthermore, we also propose the accuracy evaluation of this passive equivalent circuit by comparing it with the target active OTA-based floating inductor. Finally, we mention our further studies which are the inclusion of the mismatch among each OTA and the modelling of the passive equivalent circuit of the other type of the OTA-based floating inductor","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131813968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706563
C. Hsiao, M. Kao, C. Jen, Y. Hsu, P. Yang, C. Chiu, J. Wu, S. Hsu, Y. Hsu
In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s
{"title":"A 3.2 Gbit/s CML Transmitter With 20:1 Multiplexer In 0.18 CMOS Technology","authors":"C. Hsiao, M. Kao, C. Jen, Y. Hsu, P. Yang, C. Chiu, J. Wu, S. Hsu, Y. Hsu","doi":"10.1109/MIXDES.2006.1706563","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706563","url":null,"abstract":"In this paper, a 3.2Gb/s CML transmitter with 20:1 multiplexer was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers or switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serialization with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer could provide 250mV output voltage swing up to 10Gb/s. The overall chip size is 650mumtimes950mum with power consumption of 104 mW at 3.2Gb/s","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133809871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706649
M. Kaminska, E. Kulak, O. Guz, V. Yeliseev
It is proposed more suitable method of the testability analysis of the digital systems in comparison with known classical algorithmic and probabilistic methods. It is oriented on the complex combinational and sequential asynchronous logic circuits. Estimation of the testability is based on the topological analysis of the circuit. The new method and above mentioned methods were approved on the circuits of different complexity, including circuits from ISCAS'85, '89 Libraries. Proposed method can be used on gate-level and RT-level circuit description
{"title":"Probabilistic Testability Measure Before Pseudorandom Test Generation","authors":"M. Kaminska, E. Kulak, O. Guz, V. Yeliseev","doi":"10.1109/MIXDES.2006.1706649","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706649","url":null,"abstract":"It is proposed more suitable method of the testability analysis of the digital systems in comparison with known classical algorithmic and probabilistic methods. It is oriented on the complex combinational and sequential asynchronous logic circuits. Estimation of the testability is based on the topological analysis of the circuit. The new method and above mentioned methods were approved on the circuits of different complexity, including circuits from ISCAS'85, '89 Libraries. Proposed method can be used on gate-level and RT-level circuit description","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115325062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706656
M. Janicki, D. Makowski, P. Kędziora, L. Starzak, G. Jablonski, S. Bek
This paper discusses the possible benefits of the application of silicon carbide devices in power electronic circuits. The theoretical considerations are illustrated with the measurement results of a 500 W power factor correction (PFC) boost converter. The energy performance of the original converter has been improved owing to the application of silicon carbide Schottky barrier diode (SBD). As expected from the theory, the SiC boost diode allowed the decrease of power losses, thus improving converter efficiency. The ultimate measure of the converter energy performance used by the authors throughout this paper was the product of the energy efficiency and the power factor
{"title":"Improvement Of PFC Boost Converter Energy Performance Using Silicon Carbide Diode","authors":"M. Janicki, D. Makowski, P. Kędziora, L. Starzak, G. Jablonski, S. Bek","doi":"10.1109/MIXDES.2006.1706656","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706656","url":null,"abstract":"This paper discusses the possible benefits of the application of silicon carbide devices in power electronic circuits. The theoretical considerations are illustrated with the measurement results of a 500 W power factor correction (PFC) boost converter. The energy performance of the original converter has been improved owing to the application of silicon carbide Schottky barrier diode (SBD). As expected from the theory, the SiC boost diode allowed the decrease of power losses, thus improving converter efficiency. The ultimate measure of the converter energy performance used by the authors throughout this paper was the product of the energy efficiency and the power factor","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706582
P. Grybos, M. Idzik, P. Maj, K. Swientek
This paper presents the design and results of first measurements of a fast binary readout architecture ASIC aimed for digital X-ray imaging. The ASIC called DEDIX includes 64 readout channels, a number of DACs for different bias and threshold settings, voltage reference, temperature sensor circuit, calibration circuit, I/O circuit and a control logic circuit. Each readout channel consists of charge amplifier, PZC circuit, shaper, two discriminators and two 20-bit counters. The DEDIX is supposed to work in relatively complex systems featuring several hundred detector channels. For this reason particular attention was paid to general system solutions and the circuit testability. This paper is essentially dedicated to these aspects of DEDIX operation. The circuit was implemented in a 3.3 V 0.35 mum CMOS technology. First tests confirm full functionality of the ASIC
本文介绍了一种用于数字x射线成像的快速二进制读出结构ASIC的设计和首次测量结果。称为DEDIX的ASIC包括64个读出通道，许多用于不同偏置和阈值设置的dac，电压基准，温度传感器电路，校准电路，I/O电路和控制逻辑电路。每个读出通道由电荷放大器、PZC电路、整形器、两个鉴别器和两个20位计数器组成。DEDIX应该在相对复杂的系统中工作，具有数百个探测器通道。因此，特别注意一般系统解决方案和电路的可测试性。本文主要致力于DEDIX操作的这些方面。该电路采用3.3 V 0.35 μ m CMOS技术实现。首次测试确认了ASIC的全部功能
{"title":"Design, Functionality And Testability Of A Multichannel Asic For Digital X-ray Imaging","authors":"P. Grybos, M. Idzik, P. Maj, K. Swientek","doi":"10.1109/MIXDES.2006.1706582","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706582","url":null,"abstract":"This paper presents the design and results of first measurements of a fast binary readout architecture ASIC aimed for digital X-ray imaging. The ASIC called DEDIX includes 64 readout channels, a number of DACs for different bias and threshold settings, voltage reference, temperature sensor circuit, calibration circuit, I/O circuit and a control logic circuit. Each readout channel consists of charge amplifier, PZC circuit, shaper, two discriminators and two 20-bit counters. The DEDIX is supposed to work in relatively complex systems featuring several hundred detector channels. For this reason particular attention was paid to general system solutions and the circuit testability. This paper is essentially dedicated to these aspects of DEDIX operation. The circuit was implemented in a 3.3 V 0.35 mum CMOS technology. First tests confirm full functionality of the ASIC","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125730113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706533
H. Przewlocki
New generation of MOS (metal-oxide-semiconductor) system photoelectric measurement methods has been developed. These methods are based on a new approach to the photoelectric phenomena occurring at low electric fields in the dielectric layer. Basic features of this approach were outlined, with the emphasis on its practical applications. Principles underlying some of the new measurement methods were presented, underscoring the importance of the effective contact potential difference (ECPD or PhiMS) determination method. This method is the most sensitive and accurate of the existing methods of PhiMS determination. These measurement methods have been recently improved, allowing for the first time, to determine distributions of local PhiMS values over the gate area of MOS structures. Distributions of PhiMSvalues were determined for metal-gate and silicon-gate MOS structures. Comparison of the results obtained was presented. Methods were also developed to determine distributions of potential barrier height local values at gate-dielectric and semiconductor-dielectric interfaces. Examples of such distributions were given and their causes, as well as consequences were discussed
{"title":"The new generation of the photoelectric measurement methods of mos structure parameters","authors":"H. Przewlocki","doi":"10.1109/MIXDES.2006.1706533","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706533","url":null,"abstract":"New generation of MOS (metal-oxide-semiconductor) system photoelectric measurement methods has been developed. These methods are based on a new approach to the photoelectric phenomena occurring at low electric fields in the dielectric layer. Basic features of this approach were outlined, with the emphasis on its practical applications. Principles underlying some of the new measurement methods were presented, underscoring the importance of the effective contact potential difference (ECPD or PhiMS) determination method. This method is the most sensitive and accurate of the existing methods of PhiMS determination. These measurement methods have been recently improved, allowing for the first time, to determine distributions of local PhiMS values over the gate area of MOS structures. Distributions of PhiMSvalues were determined for metal-gate and silicon-gate MOS structures. Comparison of the results obtained was presented. Methods were also developed to determine distributions of potential barrier height local values at gate-dielectric and semiconductor-dielectric interfaces. Examples of such distributions were given and their causes, as well as consequences were discussed","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127582520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706664
A. Borys
In this paper, some issues of the design of recursive digital filters in view of their robustness are discussed. After giving some general remarks regarding the mechanisms of arising nonlinear distortion in filters, and regarding the robustness property, two problems are considered in detail. That is the forced-response stability and occurrence of harmonic distortion, are investigated. It is shown here that the forced-response stability is equivalent to the attractivity property of the (realized) filter. Furthermore, the harmonic distortion due to the finite wordlength in a class of digital filters of which poles lie near the point z = 1 is analysed, too. It is shown that by applying the method of harmonics balance it is possible to obtain the closed-form results for the higher harmonics and for the change in the filter transfer function. The expressions obtained describe, however, only qualitatively the phenomenon discussed; they do not provide quantitative results
{"title":"Design Of Recursive Digital Filters In View Of Their Robustness","authors":"A. Borys","doi":"10.1109/MIXDES.2006.1706664","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706664","url":null,"abstract":"In this paper, some issues of the design of recursive digital filters in view of their robustness are discussed. After giving some general remarks regarding the mechanisms of arising nonlinear distortion in filters, and regarding the robustness property, two problems are considered in detail. That is the forced-response stability and occurrence of harmonic distortion, are investigated. It is shown here that the forced-response stability is equivalent to the attractivity property of the (realized) filter. Furthermore, the harmonic distortion due to the finite wordlength in a class of digital filters of which poles lie near the point z = 1 is analysed, too. It is shown that by applying the method of harmonics balance it is possible to obtain the closed-form results for the higher harmonics and for the change in the filter transfer function. The expressions obtained describe, however, only qualitatively the phenomenon discussed; they do not provide quantitative results","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124512987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706602
R. Suszynski, K. Wawryn
A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of field programmable analog arrays to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. The circuit characteristics have been measured and then structure of the converter has been reconfigured to satisfy input specifications
{"title":"Rapid Prototyping Of Algorithmic Analog Digital Converters Based On FPAA Devices","authors":"R. Suszynski, K. Wawryn","doi":"10.1109/MIXDES.2006.1706602","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706602","url":null,"abstract":"A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of field programmable analog arrays to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. The circuit characteristics have been measured and then structure of the converter has been reconfigured to satisfy input specifications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123438270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706696
M. Stanislawski, W. Zabierowski, A. Napieralski
With the invention and growth of the Internet web-based tutoring systems are now more popular than ever. Although being widely available and easy to use, their role in the process of education is often limited due to the lack of interaction between the machine and the student. ICT, interactive web-based C tutor, being developed at the Technical University of Lodz, Poland, is an attempt to create a system with emphasis on the practical activities. It takes advantage of new web technologies for both server and client side and is implemented using open source software. ICT consists of several modules closely interacting with each other. It allows simple course management and dynamic content generation from XML based description files, quizzes and tests and on-the-fly web-based compilation and execution of user edited programs, removing the need for external software. Description of each module is given as well as overall view of the system. Important security issues are investigated and the flexibility of the system is discussed
{"title":"Interactive web-based C tutor","authors":"M. Stanislawski, W. Zabierowski, A. Napieralski","doi":"10.1109/MIXDES.2006.1706696","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706696","url":null,"abstract":"With the invention and growth of the Internet web-based tutoring systems are now more popular than ever. Although being widely available and easy to use, their role in the process of education is often limited due to the lack of interaction between the machine and the student. ICT, interactive web-based C tutor, being developed at the Technical University of Lodz, Poland, is an attempt to create a system with emphasis on the practical activities. It takes advantage of new web technologies for both server and client side and is implemented using open source software. ICT consists of several modules closely interacting with each other. It allows simple course management and dynamic content generation from XML based description files, quizzes and tests and on-the-fly web-based compilation and execution of user edited programs, removing the need for external software. Description of each module is given as well as overall view of the system. Important security issues are investigated and the flexibility of the system is discussed","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131855875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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