Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706583
K. Arshak, E. Jafer
The goal of this work is to fabricate a miniaturized, low power, bi-directional wireless communication system that can be used for in vivo pressure and temperature monitoring. The system prototype consists of miniature frequency shift keying (FSK) transceiver integrated with microcontroller unit (MCU) in one small package, chip antenna, and capacitive interface circuitry based on delta-sigma (SigmaDelta) modulator integrated with a on-chip temperature sensor. At the base station side, an FSK receiver/transmitter is connected to another MCU unit, which sends the received data or received instructions from a PC through a graphical user interface GUI. Industrial, scientific and medical (ISM) band RF (433 MHz) was used to achieve half duplex communication between the two sides. ShockBursttrade RF protocol has been used to achieve high data rate of 50Kbps. Gaussian frequency shift keying (GFSK) modulation scheme was adopted to ensure a reliable and high-speed digital RF link. A digital filtering has been used in the capacitive interface to reduce noise effects forming capacitance to digital converter (CDC). All the modules of the mixed signal system are integrated in a printed circuit board (PCB) of size 22.46times20.168 mm. The overall system supply voltage is 2.7V maximum
{"title":"Development Of Programmable Wireless Module For In Vivo Pressure And Temperature Monitoring","authors":"K. Arshak, E. Jafer","doi":"10.1109/MIXDES.2006.1706583","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706583","url":null,"abstract":"The goal of this work is to fabricate a miniaturized, low power, bi-directional wireless communication system that can be used for in vivo pressure and temperature monitoring. The system prototype consists of miniature frequency shift keying (FSK) transceiver integrated with microcontroller unit (MCU) in one small package, chip antenna, and capacitive interface circuitry based on delta-sigma (SigmaDelta) modulator integrated with a on-chip temperature sensor. At the base station side, an FSK receiver/transmitter is connected to another MCU unit, which sends the received data or received instructions from a PC through a graphical user interface GUI. Industrial, scientific and medical (ISM) band RF (433 MHz) was used to achieve half duplex communication between the two sides. ShockBursttrade RF protocol has been used to achieve high data rate of 50Kbps. Gaussian frequency shift keying (GFSK) modulation scheme was adopted to ensure a reliable and high-speed digital RF link. A digital filtering has been used in the capacitive interface to reduce noise effects forming capacitance to digital converter (CDC). All the modules of the mixed signal system are integrated in a printed circuit board (PCB) of size 22.46times20.168 mm. The overall system supply voltage is 2.7V maximum","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706530
D. Foty
While there is growing demand for wireless bandwidth, the most pressing problem affecting this situation today is the attempt to increase bandwidth by extending the same technologies with tricks - rather than by using innovation. Opportunities for innovation are quite good with higher carrier frequencies, since these enable simplicity and low power consumption -opening the door to truly portable wireless peer-to-peer (WP2P) networking. Numerous challenges exist in technology and design methods; however, meeting these intellectual challenges is the only route to new and exciting wireless data technologies
{"title":"New directions in technology for high-speed wireless data communications","authors":"D. Foty","doi":"10.1109/MIXDES.2006.1706530","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706530","url":null,"abstract":"While there is growing demand for wireless bandwidth, the most pressing problem affecting this situation today is the attempt to increase bandwidth by extending the same technologies with tricks - rather than by using innovation. Opportunities for innovation are quite good with higher carrier frequencies, since these enable simplicity and low power consumption -opening the door to truly portable wireless peer-to-peer (WP2P) networking. Numerous challenges exist in technology and design methods; however, meeting these intellectual challenges is the only route to new and exciting wireless data technologies","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116779129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706564
S. Alavi, O. Shoaei
The design of a 625 MHz fully differential phase-locked loop (PLL) is described. The circuit incorporates a phase-frequency detector, a charge pump, a novel quadrature ring oscillator with a new active load and frequency dividers. This PLL CMOS circuit is used in the lock detector for aiding frequency acquisition for the clock and data recovery circuit. This circuit is supported by system and circuit (CMOS 0.35mum) level simulation by CPP simulator and HSPICE
{"title":"A 625 MHz CMOS Phase-locked Loop Used In Lock Detector Application","authors":"S. Alavi, O. Shoaei","doi":"10.1109/MIXDES.2006.1706564","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706564","url":null,"abstract":"The design of a 625 MHz fully differential phase-locked loop (PLL) is described. The circuit incorporates a phase-frequency detector, a charge pump, a novel quadrature ring oscillator with a new active load and frequency dividers. This PLL CMOS circuit is used in the lock detector for aiding frequency acquisition for the clock and data recovery circuit. This circuit is supported by system and circuit (CMOS 0.35mum) level simulation by CPP simulator and HSPICE","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115170397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706677
Z. Kulesza, W. Tylman
The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted
{"title":"Implementation Of Bayesian Network In FPGA Circuit","authors":"Z. Kulesza, W. Tylman","doi":"10.1109/MIXDES.2006.1706677","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706677","url":null,"abstract":"The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132591024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706631
M. Tomáška, M. Klasovitý, M. Masar
This article deals with characterization of on-membrane pseudomorphic HFET fabricated by micromechanical technology. The basic transistor parameters important for design of more complex circuits were calculated from S-parameters, measured in the frequency range 100 MHz up to 20 GHz. The small signal equivalent circuit was identified using genetic optimization algorithms as well. This permits a closer insight on parasitic elements affecting the device performance
{"title":"On-membrane Micromechanical Pseudomorphic HFET Microwave Char","authors":"M. Tomáška, M. Klasovitý, M. Masar","doi":"10.1109/MIXDES.2006.1706631","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706631","url":null,"abstract":"This article deals with characterization of on-membrane pseudomorphic HFET fabricated by micromechanical technology. The basic transistor parameters important for design of more complex circuits were calculated from S-parameters, measured in the frequency range 100 MHz up to 20 GHz. The small signal equivalent circuit was identified using genetic optimization algorithms as well. This permits a closer insight on parasitic elements affecting the device performance","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131837735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706588
F. Kalantari, N. Masoumi, A. R. Hoseini
This paper presents a 5.25 GHz high linearity high gain LNA design for a receiver architecture based on IEEE802.16a WMAN standard. The targeted frequency band is the unlicensed band UNII 5 GHz. In our design we consider the effect of induced gate noise in MOS devices. Also we optimize our design with a random search algorithm named simulated annealing and we compare the results. The amplifier achieves voltage gain of 27.1 and 28.5 dB, noise figure of 2.03 and 2.26 dB, the IIP3 of 13.1 and 14 dBm, and the reverse isolation is about -11.03 and -11.22 dB, the LNA dissipates 7.5, 6.0 mW using a 1.8 V supply voltage respectively. Optimized design is simulated with Hspice in 0.18 mum CMOS technology
{"title":"High Gain LNA Design For WMAN Receiver & Optimization With Simulated Annealing Algorithm","authors":"F. Kalantari, N. Masoumi, A. R. Hoseini","doi":"10.1109/MIXDES.2006.1706588","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706588","url":null,"abstract":"This paper presents a 5.25 GHz high linearity high gain LNA design for a receiver architecture based on IEEE802.16a WMAN standard. The targeted frequency band is the unlicensed band UNII 5 GHz. In our design we consider the effect of induced gate noise in MOS devices. Also we optimize our design with a random search algorithm named simulated annealing and we compare the results. The amplifier achieves voltage gain of 27.1 and 28.5 dB, noise figure of 2.03 and 2.26 dB, the IIP3 of 13.1 and 14 dBm, and the reverse isolation is about -11.03 and -11.22 dB, the LNA dissipates 7.5, 6.0 mW using a 1.8 V supply voltage respectively. Optimized design is simulated with Hspice in 0.18 mum CMOS technology","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706626
A. Jarosz, A. Pfitzner
An analytical model, taking into account the further neighbourhood influence on interconnection capacitances was proposed in our previous works (Jarosz, 2002). In this paper a method of experimental verification of those formulas and a test chip designed for the AMS 0.35mum technology are presented. Results of measurements and the correctness of the model are discussed
{"title":"Interconnection Capacitances Dependence On Further Neighbourhood In The Bus - Experimental Verification Of The Model","authors":"A. Jarosz, A. Pfitzner","doi":"10.1109/MIXDES.2006.1706626","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706626","url":null,"abstract":"An analytical model, taking into account the further neighbourhood influence on interconnection capacitances was proposed in our previous works (Jarosz, 2002). In this paper a method of experimental verification of those formulas and a test chip designed for the AMS 0.35mum technology are presented. Results of measurements and the correctness of the model are discussed","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114696244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706541
B. Kosęda, W. Cichalewski
Superconducting linear accelerators are becoming more and more complex. Despite of the growth of their scale they have to meet very demanding norms concerning availability and reliability. Taking into account these facts, high degree of automation is obligatory for several accelerator subsystems. This article aims at summing up the effort of improvement of expert system for RF-power station for the FLASH. The main purpose of this software is to facilitate operators with automatic driving the power supply subsystem. Owing to the high level of autonomy possessed by the software special care has to be taken to assure predictability and safety of AI-aided operation. To assure sound engineering foundations of the project, techniques that facilitate the reasoning about correctness and predictability its behaviour have been used. As a starting point of design finite state machine computational model has been chosen. After a couple of months of lighting with several approaches of the FSM design and facing state explosion problem new design emerged which is expected to be a lot easier to maintain and adapt to new requirements
{"title":"Improvements of expert system for RF-power stations","authors":"B. Kosęda, W. Cichalewski","doi":"10.1109/MIXDES.2006.1706541","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706541","url":null,"abstract":"Superconducting linear accelerators are becoming more and more complex. Despite of the growth of their scale they have to meet very demanding norms concerning availability and reliability. Taking into account these facts, high degree of automation is obligatory for several accelerator subsystems. This article aims at summing up the effort of improvement of expert system for RF-power station for the FLASH. The main purpose of this software is to facilitate operators with automatic driving the power supply subsystem. Owing to the high level of autonomy possessed by the software special care has to be taken to assure predictability and safety of AI-aided operation. To assure sound engineering foundations of the project, techniques that facilitate the reasoning about correctness and predictability its behaviour have been used. As a starting point of design finite state machine computational model has been chosen. After a couple of months of lighting with several approaches of the FSM design and facing state explosion problem new design emerged which is expected to be a lot easier to maintain and adapt to new requirements","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115595294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706670
G. Rubin
This paper presents rapid prototyping of embedded time varying digital fourier transform (TVDFT) implementation on DSP/FPGA board. Efficiency of TVDFT is mostly of fast algorithm of sine wave generation with time-varying frequency and almost perfect quality. The SignalWAVe board is one of the most powerful DSP/FPGA entry-level development board on the market, with extensive support for basic development tools: Texas Instruments' code composer studio and Xilinx foundation. Combined with system-level tool Matlab/Simulink for an advanced rapid-prototyping platform. This board provide increased performance, cost effectiveness and overall efficiency in developed systems. Implementation and verification of TVDFT algorithm on SignalWAVe rapid prototyping board are also given
{"title":"Rapid Prototyping Of Embedded Time Varying Digital Fourier Transform Based On Signalwave DSP/FPGA Combo Board","authors":"G. Rubin","doi":"10.1109/MIXDES.2006.1706670","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706670","url":null,"abstract":"This paper presents rapid prototyping of embedded time varying digital fourier transform (TVDFT) implementation on DSP/FPGA board. Efficiency of TVDFT is mostly of fast algorithm of sine wave generation with time-varying frequency and almost perfect quality. The SignalWAVe board is one of the most powerful DSP/FPGA entry-level development board on the market, with extensive support for basic development tools: Texas Instruments' code composer studio and Xilinx foundation. Combined with system-level tool Matlab/Simulink for an advanced rapid-prototyping platform. This board provide increased performance, cost effectiveness and overall efficiency in developed systems. Implementation and verification of TVDFT algorithm on SignalWAVe rapid prototyping board are also given","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121068954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706685
P. Hottowy, W. Dąbrowski, A. Skoczeń, P. Wia̧cek
We present an ASIC designed for electrical stimulation of neural tissue using multielectrode arrays. The ASIC is foreseen for applications in systems requiring simultaneous stimulation and recording of signals from various types of neural tissue, both in-vitro and in-vivo. The developed STIM64 ASIC includes 64 independent stimulation channels, which are capable to generate arbitrarily defined bipolar current or voltage waveforms, controlled in real time with time resolution of 50 mus and amplitude resolution of 7 bits. The amplitude range of output signal can be scaled over a very wide range, what ensures compatibility with various electrode arrays of different size and geometry. Each channel is equipped with a real-time controlled stimulation artifact suppressor, which reduces the 'dead time' between the stimulation pulse and system being ready for signal recording
{"title":"Design Of A Multichannel Asic For Large Scale Spatio-temporal Distributed Stimulation Of Neural Tissue","authors":"P. Hottowy, W. Dąbrowski, A. Skoczeń, P. Wia̧cek","doi":"10.1109/MIXDES.2006.1706685","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706685","url":null,"abstract":"We present an ASIC designed for electrical stimulation of neural tissue using multielectrode arrays. The ASIC is foreseen for applications in systems requiring simultaneous stimulation and recording of signals from various types of neural tissue, both in-vitro and in-vivo. The developed STIM64 ASIC includes 64 independent stimulation channels, which are capable to generate arbitrarily defined bipolar current or voltage waveforms, controlled in real time with time resolution of 50 mus and amplitude resolution of 7 bits. The amplitude range of output signal can be scaled over a very wide range, what ensures compatibility with various electrode arrays of different size and geometry. Each channel is equipped with a real-time controlled stimulation artifact suppressor, which reduces the 'dead time' between the stimulation pulse and system being ready for signal recording","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125229167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：