Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706605
P. Pietrzak, W. Tylman, Z. Kulesza, B. Pękosławski, M. Mularczyk, A. Napieralski
Programmable circuits are commonly used class of electronic devices. In practice this term usually refers to microcontrollers with different kind of programmable memories and to programmable logic circuits (PAL, CPLD, FPGA). Most of these devices are digital circuits. Thanks to the huge progress in miniaturization of electronic circuits, the new class of devices -programmable analog circuits - was put on the market. These circuits bring new possibilities to design electronic circuit. One of the most promising fields of application is construction of analog signal conditioning circuits. This paper describes feature and parameters of sample programmable analog circuits. It depicts internal structure and theory of operation of these devices. One of commercially available programmable analog circuits was used in development of signal conditioning block for vibration measurement system. It works as programmable gain amplifier and low-pass anti-aliasing filter with programmable cut-off frequency. Amplifier transient characteristics for different gain values and frequency response of the filter were measured
{"title":"Signal Conditioning Based On Programmable Analog Circuits","authors":"P. Pietrzak, W. Tylman, Z. Kulesza, B. Pękosławski, M. Mularczyk, A. Napieralski","doi":"10.1109/MIXDES.2006.1706605","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706605","url":null,"abstract":"Programmable circuits are commonly used class of electronic devices. In practice this term usually refers to microcontrollers with different kind of programmable memories and to programmable logic circuits (PAL, CPLD, FPGA). Most of these devices are digital circuits. Thanks to the huge progress in miniaturization of electronic circuits, the new class of devices -programmable analog circuits - was put on the market. These circuits bring new possibilities to design electronic circuit. One of the most promising fields of application is construction of analog signal conditioning circuits. This paper describes feature and parameters of sample programmable analog circuits. It depicts internal structure and theory of operation of these devices. One of commercially available programmable analog circuits was used in development of signal conditioning block for vibration measurement system. It works as programmable gain amplifier and low-pass anti-aliasing filter with programmable cut-off frequency. Amplifier transient characteristics for different gain values and frequency response of the filter were measured","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115061632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706614
P. Szabó, V. Székely
We have developed a simple emissivity meter device with control electronic. The first part of the paper discusses the main laws of the thermal radiation, the structure of the measure chamber of the equipment. We present the two basic measurement methods, and the simple thermal resistance model of the system. The second part deals with the correlation between the half space average emissivity of surfaces and the emissivity measured by the equipment. For this characterisation we made detailed simulations using the FLOTHERM thermal flow simulator software and thermal transient measurements by the T3Ster equipment. The third part describes the method to reduce the settling time of the measurement. The paper is closed by the presentations of the results of the emissivity measurements of several surfaces
{"title":"Investigations Of A Simple Emissivity Meter","authors":"P. Szabó, V. Székely","doi":"10.1109/MIXDES.2006.1706614","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706614","url":null,"abstract":"We have developed a simple emissivity meter device with control electronic. The first part of the paper discusses the main laws of the thermal radiation, the structure of the measure chamber of the equipment. We present the two basic measurement methods, and the simple thermal resistance model of the system. The second part deals with the correlation between the half space average emissivity of surfaces and the emissivity measured by the equipment. For this characterisation we made detailed simulations using the FLOTHERM thermal flow simulator software and thermal transient measurements by the T3Ster equipment. The third part describes the method to reduce the settling time of the measurement. The paper is closed by the presentations of the results of the emissivity measurements of several surfaces","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706640
D. Guihal, L. Andrieux, D. Esteve, A. Cazarré
In analog and mixed-signal design, there is a growing interest to move away from proprietary modelling languages and to adopt a market standard, such as VHDL-AMS (IEEE 1076.1999). But many questions still remain about the risk of the migration path. Is there any possibility to convert directly the existing models, or is it necessary to rebuild the library? How much effort and expertise will be needed? In this paper, we try to answer to some of those concerns. We will explore the possible methodologies for generating VHDL-AMS model from other hardware description languages (HDL). Firstly, we focus on how to create a model based on the available information. In a second part, we investigate the automation tools available which can be used. Finally, we share our experience in converting a MAST amplifier model, coming from our research laboratory, to VHDL-AMS
{"title":"VHDL-AMS Model Creation","authors":"D. Guihal, L. Andrieux, D. Esteve, A. Cazarré","doi":"10.1109/MIXDES.2006.1706640","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706640","url":null,"abstract":"In analog and mixed-signal design, there is a growing interest to move away from proprietary modelling languages and to adopt a market standard, such as VHDL-AMS (IEEE 1076.1999). But many questions still remain about the risk of the migration path. Is there any possibility to convert directly the existing models, or is it necessary to rebuild the library? How much effort and expertise will be needed? In this paper, we try to answer to some of those concerns. We will explore the possible methodologies for generating VHDL-AMS model from other hardware description languages (HDL). Firstly, we focus on how to create a model based on the available information. In a second part, we investigate the automation tools available which can be used. Finally, we share our experience in converting a MAST amplifier model, coming from our research laboratory, to VHDL-AMS","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121188672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706622
G. De Mey, A. Martinez
Resistive layers are often used as gas sensors. During the measurements the contaminating gas diffuses into the layer while changing its resistivity. If one measures the impedance of the resistors for various frequencies, one often obtains an impedance plot which can be modelled by an equivalent network involving capacitances and inductances. Although a resistive layer does not show any intrinsic capacitive or inductive properties, it will be shown theoretically here that a diffusion process can give rise to such phenomena
{"title":"Capacitive And Inductive Effects In Resistors Induced By Diffusion","authors":"G. De Mey, A. Martinez","doi":"10.1109/MIXDES.2006.1706622","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706622","url":null,"abstract":"Resistive layers are often used as gas sensors. During the measurements the contaminating gas diffuses into the layer while changing its resistivity. If one measures the impedance of the resistors for various frequencies, one often obtains an impedance plot which can be modelled by an equivalent network involving capacitances and inductances. Although a resistive layer does not show any intrinsic capacitive or inductive properties, it will be shown theoretically here that a diffusion process can give rise to such phenomena","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121196352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706668
B. Karunya, R. Uma
Filtering data in real time requires dedicated hardware to meet demanding time requirements. One important feature of signal processing is coping with noise. To be able to achieve the required output signal for a wide range of input signals and noise, it is desirable to be able to adjust both the filter characteristics and the type of filter. In this way the resulting filter is said to be an adaptive filter. We propose an on-chip solution for evolving an adaptive digital filter using an on-chip evolvable hardware method. This project is about implementing evolvable hardware using genetic algorithms. It gives a formal introduction to evolvable hardware, which is a new hardware paradigm in which hardware is built on reconfigurable devices such as PLDs and FPGAs whose architectures can be reconfigured by using evolutionary computation techniques such as genetic algorithms, to adapt to the new environment
{"title":"Functional Level Implementation Of Evolvable Hardware Using Genetic Algorithms","authors":"B. Karunya, R. Uma","doi":"10.1109/MIXDES.2006.1706668","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706668","url":null,"abstract":"Filtering data in real time requires dedicated hardware to meet demanding time requirements. One important feature of signal processing is coping with noise. To be able to achieve the required output signal for a wide range of input signals and noise, it is desirable to be able to adjust both the filter characteristics and the type of filter. In this way the resulting filter is said to be an adaptive filter. We propose an on-chip solution for evolving an adaptive digital filter using an on-chip evolvable hardware method. This project is about implementing evolvable hardware using genetic algorithms. It gives a formal introduction to evolvable hardware, which is a new hardware paradigm in which hardware is built on reconfigurable devices such as PLDs and FPGAs whose architectures can be reconfigured by using evolutionary computation techniques such as genetic algorithms, to adapt to the new environment","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116301375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706593
P. Mandal, P. Khan, R. Pandey
Higher supply line selector is an integral part of a multi-supply power management integrated circuit (IC). This document talks about a CMOS implementation of higher-supply-line selector circuit. The selector circuit uses a proposed supply line comparator. To avoid unwanted hazard for equal potential at the supply lines, the comparator has hysteresis in its switching characteristic. Operating principle of the proposed comparator discussed in detail. The higher-supply-line selector circuit is used in a 3.0V/5.0V power supervisor chip which is implemented in a 0.5mum CMOS process. The silicon-measured data is consistent with predicted simulation results. The proposed circuit idea can be extended for more than two supplies environment. Additionally, similar implementation can be adopted using bi-polar or in Bi-CMOS circuits
高等电源选择器是多电源管理集成电路(IC)的重要组成部分。本文讨论了一种高供线选择电路的CMOS实现。选择电路使用一个建议的供电线路比较器。为了避免供电线路上的等电位产生不必要的危险，比较器在其开关特性中具有迟滞。详细讨论了所建议的比较器的工作原理。高电源选择电路用于3.0V/5.0V电源监控芯片，该芯片采用0.5 μ m CMOS工艺实现。硅测得的数据与预测的模拟结果一致。所提出的电路思想可以扩展到两个以上电源的环境。此外，类似的实现可以采用双极或双cmos电路
{"title":"Max-supply selector using a voltage comparator","authors":"P. Mandal, P. Khan, R. Pandey","doi":"10.1109/MIXDES.2006.1706593","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706593","url":null,"abstract":"Higher supply line selector is an integral part of a multi-supply power management integrated circuit (IC). This document talks about a CMOS implementation of higher-supply-line selector circuit. The selector circuit uses a proposed supply line comparator. To avoid unwanted hazard for equal potential at the supply lines, the comparator has hysteresis in its switching characteristic. Operating principle of the proposed comparator discussed in detail. The higher-supply-line selector circuit is used in a 3.0V/5.0V power supervisor chip which is implemented in a 0.5mum CMOS process. The silicon-measured data is consistent with predicted simulation results. The proposed circuit idea can be extended for more than two supplies environment. Additionally, similar implementation can be adopted using bi-polar or in Bi-CMOS circuits","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127216075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706653
L. Starzak, A. Napieralski
There is a growing need for power device models that would be both accurate and fast. A pin diode model developed earlier and implemented in Berkeley SPICE through code modification is used to design a simple IGBT model that fulfills these requirements. The approach adopted in this work is also applicable to other power semiconductor devices that contain the wide and lightly doped base layer
{"title":"A new IGBT model based on distribution PIN model for spice","authors":"L. Starzak, A. Napieralski","doi":"10.1109/MIXDES.2006.1706653","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706653","url":null,"abstract":"There is a growing need for power device models that would be both accurate and fast. A pin diode model developed earlier and implemented in Berkeley SPICE through code modification is used to design a simple IGBT model that fulfills these requirements. The approach adopted in this work is also applicable to other power semiconductor devices that contain the wide and lightly doped base layer","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706561
D. Dimitrov, T. Vasileva
An 8-bit semi-flash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. In the proposed circuit there are no DAC, no subtraction circuit sand no residue amplifier. As a result, moderate conversion speed has been combined with drastically reduced power consumption
{"title":"8-bit Semi-flash A/D Converter","authors":"D. Dimitrov, T. Vasileva","doi":"10.1109/MIXDES.2006.1706561","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706561","url":null,"abstract":"An 8-bit semi-flash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. In the proposed circuit there are no DAC, no subtraction circuit sand no residue amplifier. As a result, moderate conversion speed has been combined with drastically reduced power consumption","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130881815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706687
W. Więcławek
This document describes modification of the live-wire algorithm also known as the intelligent scissors. This tool is utilized to interactive segmentation of the digitized images. Unfortunately, traditional live-wire algorithm suffers from high computational cost and is time consuming method, highly dependent on image size. Numerical complexity follows that live-wire algorithm takes all image pixels into consideration but only some pixels are situated on the edges in image. In connection with this fact in this paper condition of essential pixels is proposed. FCM algorithm utilized to classification of image pixels is proposed to describe this condition. This modification significantly shortens computational time. Obtained results will be presented based on medical images from magnetic resonance imaging (MRI) or computer tomography (CT). However this method is not limited only to medical or black and white images
{"title":"Live-wire Method With FCM Classification","authors":"W. Więcławek","doi":"10.1109/MIXDES.2006.1706687","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706687","url":null,"abstract":"This document describes modification of the live-wire algorithm also known as the intelligent scissors. This tool is utilized to interactive segmentation of the digitized images. Unfortunately, traditional live-wire algorithm suffers from high computational cost and is time consuming method, highly dependent on image size. Numerical complexity follows that live-wire algorithm takes all image pixels into consideration but only some pixels are situated on the edges in image. In connection with this fact in this paper condition of essential pixels is proposed. FCM algorithm utilized to classification of image pixels is proposed to describe this condition. This modification significantly shortens computational time. Obtained results will be presented based on medical images from magnetic resonance imaging (MRI) or computer tomography (CT). However this method is not limited only to medical or black and white images","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706635
Y. A. Durrani, T. Riesgo, F. Machado
In this paper, we propose a macromodeling approach that allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs. Our approach can handle combinational and sequential circuits for register transfer level. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and power dissipation is predicted by a macromodel function. In our experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of just 1%. Our model is parameterizable and provides accurate power estimation
{"title":"Statistical Power Estimation For Register Transfer Level","authors":"Y. A. Durrani, T. Riesgo, F. Machado","doi":"10.1109/MIXDES.2006.1706635","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706635","url":null,"abstract":"In this paper, we propose a macromodeling approach that allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs. Our approach can handle combinational and sequential circuits for register transfer level. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and power dissipation is predicted by a macromodel function. In our experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of just 1%. Our model is parameterizable and provides accurate power estimation","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127706763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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