Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706562
S. Alavi, O. Shoaei
An OC-48 phase-lock clock and data recovery (CDR) circuit is proposed, supported by system and circuit (CMOS 0.35mum) level simulation for SONET (2.488/2.688-Gb/s) transceiver applications. The CDR circuit exploits quarter rate linear phase detector. A novel quadrature ring oscillator using new active inductor is also introduced that operates at quarter rate of the original clock. Also for frequency locking this paper uses a lock detector. Making use of the frac14 linear phase detector (PD) facilitates the design of voltage controlled oscillator (VCO) and eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recovered data
{"title":"A 2.5-Gb/s CMOS Clock And Data Recovery Circuit With A 1/4 Rate Linear Phase Detector And Lock Detector","authors":"S. Alavi, O. Shoaei","doi":"10.1109/MIXDES.2006.1706562","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706562","url":null,"abstract":"An OC-48 phase-lock clock and data recovery (CDR) circuit is proposed, supported by system and circuit (CMOS 0.35mum) level simulation for SONET (2.488/2.688-Gb/s) transceiver applications. The CDR circuit exploits quarter rate linear phase detector. A novel quadrature ring oscillator using new active inductor is also introduced that operates at quarter rate of the original clock. Also for frequency locking this paper uses a lock detector. Making use of the frac14 linear phase detector (PD) facilitates the design of voltage controlled oscillator (VCO) and eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recovered data","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706634
E. Gadjeva, V. Durev, M. Hristov, D. Pukneva
An approach for optimal design of spiral inductors with the use of genetic algorithm is proposed. The approach is applied to optimal geometry design of planar spiral inductors for RF applications with respect to the quality factor Q. MATLAB methodology was implemented, based on the genetic algorithm toolbox
{"title":"Optimization Of Geometric Parameters Of Spiral Inductors Using Genetic Algorithms","authors":"E. Gadjeva, V. Durev, M. Hristov, D. Pukneva","doi":"10.1109/MIXDES.2006.1706634","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706634","url":null,"abstract":"An approach for optimal design of spiral inductors with the use of genetic algorithm is proposed. The approach is applied to optimal geometry design of planar spiral inductors for RF applications with respect to the quality factor Q. MATLAB methodology was implemented, based on the genetic algorithm toolbox","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706571
Q. Hu, Z.H. Liu, L. Yan, W. Zhou
This paper demonstrates a silicon-germanium (SiGe) HBT power amplifier for time division synchronous code-division multiple-access (TD-SCDMA) application with a single positive 3.3V supply and fully integrated on-chip input and interstage matching network. For the code-division multiple-access environment, the power amplifier delivers 30dBm power output and provides power-added efficiency (PAE) of 34.8% and an adjacent channel power ratio (ACPR) less than -35 dBc at 28 dBm. The power amplifier includes dynamic control bias circuits and a fully integrated power detector
{"title":"A SiGe Power Amplifier With Power Detector And VSWR Protection For TD-SCDMA Application","authors":"Q. Hu, Z.H. Liu, L. Yan, W. Zhou","doi":"10.1109/MIXDES.2006.1706571","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706571","url":null,"abstract":"This paper demonstrates a silicon-germanium (SiGe) HBT power amplifier for time division synchronous code-division multiple-access (TD-SCDMA) application with a single positive 3.3V supply and fully integrated on-chip input and interstage matching network. For the code-division multiple-access environment, the power amplifier delivers 30dBm power output and provides power-added efficiency (PAE) of 34.8% and an adjacent channel power ratio (ACPR) less than -35 dBc at 28 dBm. The power amplifier includes dynamic control bias circuits and a fully integrated power detector","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706636
I. Humenyuk, S. Palomar, D. Lagrange, S. Assié, B. Franck, P. Marcoul, D. Medale, A. Martinez, P. Temple-Boyer
This paper deals with the investigation of the temperature behavior of MOS-based sensors operating in the saturation region. A MOSFET transistor was integrated together with an N-pH-ISFET and used as temperature sensor to reduce the ISFET's temperature effect. The threshold voltage shifts of the MOSFET and pH-ISFETs transistors with temperature variations have been studied in real time. A result demonstrate the use of the MOSFET transistors as a temperature sensor and enables the understanding of the temperature influence on the pH-ISFET response using a FPGA signal acquisition system
{"title":"Study On pH-ISFET Temperature Effect Using Implemented MOS Transistor","authors":"I. Humenyuk, S. Palomar, D. Lagrange, S. Assié, B. Franck, P. Marcoul, D. Medale, A. Martinez, P. Temple-Boyer","doi":"10.1109/MIXDES.2006.1706636","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706636","url":null,"abstract":"This paper deals with the investigation of the temperature behavior of MOS-based sensors operating in the saturation region. A MOSFET transistor was integrated together with an N-pH-ISFET and used as temperature sensor to reduce the ISFET's temperature effect. The threshold voltage shifts of the MOSFET and pH-ISFETs transistors with temperature variations have been studied in real time. A result demonstrate the use of the MOSFET transistors as a temperature sensor and enables the understanding of the temperature influence on the pH-ISFET response using a FPGA signal acquisition system","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131101981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706627
M. A. Karami, N. Masoumi
In this paper a new method for accelerating substrate coupling modeling and analysis is introduced. This method is based on separating substrate to two different parts for simulation. The separation achieved by using a multi layer perceptron neural network, by approximating the middle surface of substrate for finding other points potentials. By separating the substrate, it could be simulated by different parallel processors and time of simulation in this modeling method, decreased typically by 57%. The simulation procedure distributes by applying different boundary conditions resulted from neural network approximation
{"title":"Middle Surface Approximtaion For Parallel And Distributed Substrate Coupling Analysis","authors":"M. A. Karami, N. Masoumi","doi":"10.1109/MIXDES.2006.1706627","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706627","url":null,"abstract":"In this paper a new method for accelerating substrate coupling modeling and analysis is introduced. This method is based on separating substrate to two different parts for simulation. The separation achieved by using a multi layer perceptron neural network, by approximating the middle surface of substrate for finding other points potentials. By separating the substrate, it could be simulated by different parallel processors and time of simulation in this modeling method, decreased typically by 57%. The simulation procedure distributes by applying different boundary conditions resulted from neural network approximation","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127631977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706598
A. Barkalov, M. Kolopienczyk, L. Titarenko
The method of design of compositional microprogram control unit with codes sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair code of operational linear chain, code of components. Such approach permits to use all positive features of codes sharing independently on characteristics of interpreted flow-chart of algorithm. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given
{"title":"Optimization Of Control Memory Size Of Control Unit With Codes Sharing","authors":"A. Barkalov, M. Kolopienczyk, L. Titarenko","doi":"10.1109/MIXDES.2006.1706598","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706598","url":null,"abstract":"The method of design of compositional microprogram control unit with codes sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair code of operational linear chain, code of components. Such approach permits to use all positive features of codes sharing independently on characteristics of interpreted flow-chart of algorithm. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115954475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706643
B. Goll, M. Spinola Durante, H. Zimmermann
The delay time of a regenerative comparator can be in the range of some tens of picoseconds. In this paper, an on-chip measurement technique is presented to obtain this delay time. For this task simple RC low-passes and different variants of implementing a fast XOR gate are examined to determine a short time difference, where after sampling the logic decision at the inverted and non-inverted output of the comparator, both outputs overlap with the same logical value. This time-difference is identified as the delay time of the comparator and occurs, if in the reset phase of the comparator the output nodes are pulled to the same logical value. An advantage of this technique is that only a DC voltage has to be measured outside the chip, which is proportional to the delay time and which is not influenced by bond wire inductances. A test-chip with the low-power comparator and a test-bed for delay-time detection was manufactured in a 120nm CMOS technology with a supply voltage of 1.5V. Compared with simulation results it turns out that a simple RC low-pass is sufficient for delay measurements. When applying a rectangular signal at the input of the implemented comparator, a minimal resolution of 8mV at a clock frequency of 1.5GHz was reached. The power consumption of the comparator was 160muW at 1.5GHz and the offset voltage was typically l0mV
{"title":"A Measurement Technique To Obtain The Delay Time Of A Comparator In 120nm CMOS","authors":"B. Goll, M. Spinola Durante, H. Zimmermann","doi":"10.1109/MIXDES.2006.1706643","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706643","url":null,"abstract":"The delay time of a regenerative comparator can be in the range of some tens of picoseconds. In this paper, an on-chip measurement technique is presented to obtain this delay time. For this task simple RC low-passes and different variants of implementing a fast XOR gate are examined to determine a short time difference, where after sampling the logic decision at the inverted and non-inverted output of the comparator, both outputs overlap with the same logical value. This time-difference is identified as the delay time of the comparator and occurs, if in the reset phase of the comparator the output nodes are pulled to the same logical value. An advantage of this technique is that only a DC voltage has to be measured outside the chip, which is proportional to the delay time and which is not influenced by bond wire inductances. A test-chip with the low-power comparator and a test-bed for delay-time detection was manufactured in a 120nm CMOS technology with a supply voltage of 1.5V. Compared with simulation results it turns out that a simple RC low-pass is sufficient for delay measurements. When applying a rectangular signal at the input of the implemented comparator, a minimal resolution of 8mV at a clock frequency of 1.5GHz was reached. The power consumption of the comparator was 160muW at 1.5GHz and the offset voltage was typically l0mV","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116422547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706604
P. Sniatala, R. Rudnicki
This paper presents AMPLE language utilization for a layout generation. A current mirror generator is described. Next, the proposed solution is presented as a part of a design flow for SI circuits. Another tool improving the design - Current Mirror Maker is also presented. This tool calculates transistors' sizes, which fulfil the given requirements of the circuit for the desired technology. The whole approach was practically verified during the design of fabricated testing chip
{"title":"Si Circuits Design Automation Using Ample Language","authors":"P. Sniatala, R. Rudnicki","doi":"10.1109/MIXDES.2006.1706604","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706604","url":null,"abstract":"This paper presents AMPLE language utilization for a layout generation. A current mirror generator is described. Next, the proposed solution is presented as a part of a design flow for SI circuits. Another tool improving the design - Current Mirror Maker is also presented. This tool calculates transistors' sizes, which fulfil the given requirements of the circuit for the desired technology. The whole approach was practically verified during the design of fabricated testing chip","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126699625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706559
S. Schmidt, M. Franke
High voltage MOS transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard Spice simulator. A drain resistance can be described by a behavioural source and a resistance in series. The source could be a current or voltage source controlled by drain current and gate voltage. The example discussed in this paper describes a sub-circuit containing a current source with a resistor in series as well as a model of the voltage dependent gate to drain capacitance. One of the most important goals of development was a fast convergence of the transient simulation. This was achieved by a restriction of the mathematical formula for the current function. The model is tested by means of a ring oscillator. The results have been satisfactory for DC, AC as well as transient analysis
{"title":"Lumped Element Behavioural High Voltage MOS Model","authors":"S. Schmidt, M. Franke","doi":"10.1109/MIXDES.2006.1706559","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706559","url":null,"abstract":"High voltage MOS transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard Spice simulator. A drain resistance can be described by a behavioural source and a resistance in series. The source could be a current or voltage source controlled by drain current and gate voltage. The example discussed in this paper describes a sub-circuit containing a current source with a resistor in series as well as a model of the voltage dependent gate to drain capacitance. One of the most important goals of development was a fast convergence of the transient simulation. This was achieved by a restriction of the mathematical formula for the current function. The model is tested by means of a ring oscillator. The results have been satisfactory for DC, AC as well as transient analysis","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129130058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706597
N. Christoffers, T. Fedtschenko, T. Stucke, R. Kokozinski, S. Kolnsberg
The channel selection in direct-downconversion receivers can be performed using analog or digital filters or a combination of both. For an appropriate partitioning in early design phase knowledge about the power-performance tradeoffs of the building blocks is necessary without knowledge about too many implementation details. This paper proposes a method to carry out the noise-power trade-off of analog Gm-C filters. For a particular example where the demand on adjacent channel rejection is very high it is shown that the analog solution is very promising when compared to the digital channel selection
{"title":"Noise-power Trade-off In CMOS-G/sub M/-C Channel Select Filters","authors":"N. Christoffers, T. Fedtschenko, T. Stucke, R. Kokozinski, S. Kolnsberg","doi":"10.1109/MIXDES.2006.1706597","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706597","url":null,"abstract":"The channel selection in direct-downconversion receivers can be performed using analog or digital filters or a combination of both. For an appropriate partitioning in early design phase knowledge about the power-performance tradeoffs of the building blocks is necessary without knowledge about too many implementation details. This paper proposes a method to carry out the noise-power trade-off of analog Gm-C filters. For a particular example where the demand on adjacent channel rejection is very high it is shown that the analog solution is very promising when compared to the digital channel selection","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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