Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706540
K. Przygoda, M. Grecki
This paper presents programmable FPGA-based divider of high frequency reference signal dedicated to generate various frequencies for synchronization of particle accelerator subsystems. The digital circuit was synthesized using pure VHDL description thus can be implemented not only in target Altera Stratix II high-speed FPGA chip but other FPGAs as well. The implemented circuit operates up to the FPGA frequency limit of 500 MHz. The generated frequency signals can be time shifted by programmable multiplicity of the clock period (2ps) without introducing additional phase skew to the output signals
{"title":"High speed synchronization module implemented in altera stratix II FPGA","authors":"K. Przygoda, M. Grecki","doi":"10.1109/MIXDES.2006.1706540","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706540","url":null,"abstract":"This paper presents programmable FPGA-based divider of high frequency reference signal dedicated to generate various frequencies for synchronization of particle accelerator subsystems. The digital circuit was synthesized using pure VHDL description thus can be implemented not only in target Altera Stratix II high-speed FPGA chip but other FPGAs as well. The implemented circuit operates up to the FPGA frequency limit of 500 MHz. The generated frequency signals can be time shifted by programmable multiplicity of the clock period (2ps) without introducing additional phase skew to the output signals","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130363166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706589
R. Wojtyna
A specific application CMOS voltage follower is presented, which is well suited to be used as a component of VLSI analog electronics such as hardware implemented artificial neural networks (ANN's) or switched-capacitor filters (SC-filters). The main advantages of the follower are: a very high precision of operation and low power consumption. Another advantage is a low input capacitance (about 2fF) and extremely high input resistance. Compared with general purpose followers, its disadvantage is a restricted range of input voltage variations. This is the price we pay for the achieved positive features. Apart from the general idea and some previous versions of the follower, a new circuit realization is presented. SPICE simulation results concerning layouts made for a 0.35mum CMOS process are shown. These results are in good agreement with theoretical predictions as well as experimental results achieved for a 0.8mum prototype. Prototypes designed for the 0.18mum technology are currently being fabricated (in cooperation with University of Alberta in Canada) and no measurements have been performed yet
介绍了一种特殊应用的CMOS电压跟随器，它非常适合用于VLSI模拟电子元件，如硬件实现的人工神经网络(ANN)或开关电容滤波器(sc -滤波器)。从动件的主要优点是:操作精度非常高，功耗低。另一个优点是低输入电容(约2fF)和极高的输入电阻。与通用从动器相比，其缺点是输入电压变化范围有限。这是我们为实现积极特性所付出的代价。除了一般的思想和以前的一些版本的从动器，提出了一个新的电路实现。给出了0.35 μ m CMOS工艺版图的SPICE仿真结果。这些结果与理论预测以及0.8 mm原型机的实验结果很好地吻合。为0.18 μ m技术设计的原型目前正在制造中(与加拿大阿尔伯塔大学合作)，尚未进行任何测量
{"title":"High-precision Low-power Voltage Follower For Hardware Signal Processing","authors":"R. Wojtyna","doi":"10.1109/MIXDES.2006.1706589","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706589","url":null,"abstract":"A specific application CMOS voltage follower is presented, which is well suited to be used as a component of VLSI analog electronics such as hardware implemented artificial neural networks (ANN's) or switched-capacitor filters (SC-filters). The main advantages of the follower are: a very high precision of operation and low power consumption. Another advantage is a low input capacitance (about 2fF) and extremely high input resistance. Compared with general purpose followers, its disadvantage is a restricted range of input voltage variations. This is the price we pay for the achieved positive features. Apart from the general idea and some previous versions of the follower, a new circuit realization is presented. SPICE simulation results concerning layouts made for a 0.35mum CMOS process are shown. These results are in good agreement with theoretical predictions as well as experimental results achieved for a 0.8mum prototype. Prototypes designed for the 0.18mum technology are currently being fabricated (in cooperation with University of Alberta in Canada) and no measurements have been performed yet","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706663
A. Kuncheva, L. Fujcik, T. Mougel, B. Donchev, M. Hristov
This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (SigmaDelta) modulator. Parameters of decimation filter are derived from the specification of the multibit SigmaDelta modulator with two-step quantization architecture. Using Matlab tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA -Spartan 3 XC3S200-5FT256
{"title":"Design Of Decimation Filter For Multibit Sigmadelta Modulator With Two-step Quantization","authors":"A. Kuncheva, L. Fujcik, T. Mougel, B. Donchev, M. Hristov","doi":"10.1109/MIXDES.2006.1706663","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706663","url":null,"abstract":"This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (SigmaDelta) modulator. Parameters of decimation filter are derived from the specification of the multibit SigmaDelta modulator with two-step quantization architecture. Using Matlab tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA -Spartan 3 XC3S200-5FT256","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130918386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706595
R. Dlugosz
New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications
{"title":"New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology","authors":"R. Dlugosz","doi":"10.1109/MIXDES.2006.1706595","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706595","url":null,"abstract":"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134411752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706648
H. Kadim
With the improvement of VLSI technologies, many components of highly complex functions can be fabricated into a single chip. However, the high density and complexity of integrated circuits brought with it challenges to traditional test techniques. According to the silicon industry, the cost of fabricating a chip will drop below that of test. Hence, it is imperative that test techniques lower testing costs. The work presented in this paper is an attempt to reduce the cost of testing by the modelling the circuit under test in a manner suitable for hierarchical implementation and the introduction of partial analysis. A limited analysis requires less time and effort compared to a complete analysis
{"title":"Partial Analysis For Functional Testing Of Digital IP-cores","authors":"H. Kadim","doi":"10.1109/MIXDES.2006.1706648","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706648","url":null,"abstract":"With the improvement of VLSI technologies, many components of highly complex functions can be fabricated into a single chip. However, the high density and complexity of integrated circuits brought with it challenges to traditional test techniques. According to the silicon industry, the cost of fabricating a chip will drop below that of test. Hence, it is imperative that test techniques lower testing costs. The work presented in this paper is an attempt to reduce the cost of testing by the modelling the circuit under test in a manner suitable for hierarchical implementation and the introduction of partial analysis. A limited analysis requires less time and effort compared to a complete analysis","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132178393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706623
D. Kasprowicz
Grids of metal wires are widely used for distributing the clock signal in large digital circuits. These structures inherently suffer from clock skew, as there always exists some delay between the grid's perimeter and its center. This paper presents an empirical model of clock skew in square grids. It's formulated in terms of four parameters: wire resistance, the number of wires, size of buffers driving the grid and the total capacitance of the grid and its load. The model's accuracy is within 5% of SPICE results for a wide range of grid sizes, wire widths, load capacitances, and other parameters. Also presented are a couple of possible applications in grid design and optimization. As those tasks are iterative, they would take on the order of hours if performed by SPICE-simulating netlists extracted from grid layouts. The proposed model allows reducing the analysis time to less than a second
{"title":"Empirical model of skew in clock-distribution grids","authors":"D. Kasprowicz","doi":"10.1109/MIXDES.2006.1706623","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706623","url":null,"abstract":"Grids of metal wires are widely used for distributing the clock signal in large digital circuits. These structures inherently suffer from clock skew, as there always exists some delay between the grid's perimeter and its center. This paper presents an empirical model of clock skew in square grids. It's formulated in terms of four parameters: wire resistance, the number of wires, size of buffers driving the grid and the total capacitance of the grid and its load. The model's accuracy is within 5% of SPICE results for a wide range of grid sizes, wire widths, load capacitances, and other parameters. Also presented are a couple of possible applications in grid design and optimization. As those tasks are iterative, they would take on the order of hours if performed by SPICE-simulating netlists extracted from grid layouts. The proposed model allows reducing the analysis time to less than a second","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132936632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706603
T. Levi, N. Lewis, J. Tomas, P. Fouillat
In this paper we propose a methodology for analog design reuse during technology scaling. This method is based on resizing rules resulting in the application of a MOS transistor model. The aims of this scaling are the conservation of the performances of the original circuit and the reduction of power consumption and area. This resizing methodology has been applied on different analog circuits. The original circuit has been designed in 0.8 mum AMS technology with a supply voltage of 5 V and then scaled in 0.35 mum AMS technology with a 3.3 V supply voltage. Finally, the methodology is validated by simulation results
本文提出了一种在技术扩展过程中实现模拟设计重用的方法。该方法基于调整尺寸的规则，导致了MOS晶体管模型的应用。这种缩放的目的是保持原有电路的性能，减少功耗和面积。这种调整尺寸的方法已经应用于不同的模拟电路。原始电路采用0.8 μ m AMS技术，供电电压为5 V，然后采用0.35 μ m AMS技术，供电电压为3.3 V。最后，通过仿真结果验证了该方法的有效性
{"title":"Scaling Rules For Mos Analog Design Reuse","authors":"T. Levi, N. Lewis, J. Tomas, P. Fouillat","doi":"10.1109/MIXDES.2006.1706603","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706603","url":null,"abstract":"In this paper we propose a methodology for analog design reuse during technology scaling. This method is based on resizing rules resulting in the application of a MOS transistor model. The aims of this scaling are the conservation of the performances of the original circuit and the reduction of power consumption and area. This resizing methodology has been applied on different analog circuits. The original circuit has been designed in 0.8 mum AMS technology with a supply voltage of 5 V and then scaled in 0.35 mum AMS technology with a 3.3 V supply voltage. Finally, the methodology is validated by simulation results","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706548
F. Haned, M. B. Chouikha, G. Alquié
In this paper, we present a study of the buried double pn junction color detector dark current to take a more comprehensive view of the dominant mechanisms. For this purpose a variety of BDJ test cells with different dimensions have been designed and manufactured in AMS' 0.35mum CMOS process. Reverse current-voltage characteristics and temperature dependence are used to distinguish the different mechanisms that contribute to the BDJ dark currents. We found that tunneling effect is the dominant mechanism for the shallow junction dark current, while for the deep junction thermal Shockley-Read-Hall generation is the main mechanism
在本文中，我们提出了一种埋置双pn结颜色探测器暗电流的研究，以采取更全面的主要机制的观点。为此，在AMS的0.35 μ m CMOS工艺中设计和制造了各种不同尺寸的BDJ测试单元。反向电流-电压特性和温度依赖性被用来区分导致BDJ暗电流的不同机制。我们发现隧道效应是浅结暗电流的主要机制，而深结的热肖克利-里德-霍尔产生是主要机制
{"title":"Temperature effect on the buried double junction color detector behavior","authors":"F. Haned, M. B. Chouikha, G. Alquié","doi":"10.1109/MIXDES.2006.1706548","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706548","url":null,"abstract":"In this paper, we present a study of the buried double pn junction color detector dark current to take a more comprehensive view of the dominant mechanisms. For this purpose a variety of BDJ test cells with different dimensions have been designed and manufactured in AMS' 0.35mum CMOS process. Reverse current-voltage characteristics and temperature dependence are used to distinguish the different mechanisms that contribute to the BDJ dark currents. We found that tunneling effect is the dominant mechanism for the shallow junction dark current, while for the deep junction thermal Shockley-Read-Hall generation is the main mechanism","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"808 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132997361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706612
A. Golda, A. Kos
The paper presents theoretical analyses, simulations and design of a PTAT (proportional to absolute temperature) temperature sensor that is based on the vertical PNP structure and dedicated to CMOS VLSI circuits. Performed considerations take into account specific properties of materials that forms electronic elements. The electrothermal simulations are performed in order to verify the unwanted self-heating effect of the sensor
本文介绍了一种基于垂直PNP结构、专用于CMOS VLSI电路的PTAT (proportional to absolute temperature)温度传感器的理论分析、仿真和设计。执行的考虑考虑到形成电子元件的材料的特定属性。为了验证传感器的自热效应，进行了电热模拟
{"title":"Analysis And Design Of Ptat Temperature Sensor In Digital CMOS VLSI Circuits","authors":"A. Golda, A. Kos","doi":"10.1109/MIXDES.2006.1706612","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706612","url":null,"abstract":"The paper presents theoretical analyses, simulations and design of a PTAT (proportional to absolute temperature) temperature sensor that is based on the vertical PNP structure and dedicated to CMOS VLSI circuits. Performed considerations take into account specific properties of materials that forms electronic elements. The electrothermal simulations are performed in order to verify the unwanted self-heating effect of the sensor","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133372624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706647
J. Dabrowski, R. Ramzan
In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade
{"title":"Offset Loopback Test For IC RF Transceivers","authors":"J. Dabrowski, R. Ramzan","doi":"10.1109/MIXDES.2006.1706647","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706647","url":null,"abstract":"In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116421200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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