Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224369
W. Che, I. Koren
Repairing a reconfigurable array by row and column replacement using SR rows and SC columns was shown to be an NP-complete problem. In order to reduce the search time, the authors propose to apply a three phase procedure. In the first phase, they suggest using a heuristic to find good, but not necessarily optimal, feasible cover for the faulty array. Only if the heuristic method fails to generate a feasible cover, the array is examined to find out whether it is repairable at all. If deemed economical, repairable chips will undergo an exhaustive analysis. This three phase strategy can considerably reduce the average time for repair analysis. Searching for a good heuristic to be applied in phase 1, the authors investigated the fault distribution pattern on the faulty array and considered the effect of a row or column replacement on this fault distribution. Accordingly, a k degree fault spectrum for a bipartite graph is defined and a maximum spectrum is introduced as a heuristic for selecting vertices. They prove that the vertices which are most likely to be included in the feasible cover will be selected by heuristic. Consequently, a fast method to generate a feasible cover is proposed and a suitable algorithm is developed.<>
{"title":"Fault spectrum analysis for fast spare allocation in reconfigurable arrays","authors":"W. Che, I. Koren","doi":"10.1109/DFTVS.1992.224369","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224369","url":null,"abstract":"Repairing a reconfigurable array by row and column replacement using SR rows and SC columns was shown to be an NP-complete problem. In order to reduce the search time, the authors propose to apply a three phase procedure. In the first phase, they suggest using a heuristic to find good, but not necessarily optimal, feasible cover for the faulty array. Only if the heuristic method fails to generate a feasible cover, the array is examined to find out whether it is repairable at all. If deemed economical, repairable chips will undergo an exhaustive analysis. This three phase strategy can considerably reduce the average time for repair analysis. Searching for a good heuristic to be applied in phase 1, the authors investigated the fault distribution pattern on the faulty array and considered the effect of a row or column replacement on this fault distribution. Accordingly, a k degree fault spectrum for a bipartite graph is defined and a maximum spectrum is introduced as a heuristic for selecting vertices. They prove that the vertices which are most likely to be included in the feasible cover will be selected by heuristic. Consequently, a fast method to generate a feasible cover is proposed and a suitable algorithm is developed.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224343
C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia
The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lower bound.<>
{"title":"Improved layer assignment for packaging multichip modules","authors":"C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia","doi":"10.1109/DFTVS.1992.224343","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224343","url":null,"abstract":"The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lower bound.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"51 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125561032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224363
J. Sousa, João Paulo Teixeira
Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach.<>
{"title":"Defect level estimation for digital ICs","authors":"J. Sousa, João Paulo Teixeira","doi":"10.1109/DFTVS.1992.224363","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224363","url":null,"abstract":"Defect level (DL) projections are very important in determining test quality and, thus, the market competitiveness of an integrated circuit (IC) product. However, at present, there is no way of accurately predicting DL in the IC design environment, since no accurate fault models are used. This paper presents a formalism and a method for DL estimation, based on a realistic fault model close to physical defects. A definition of weighted fault coverage is introduced, and an extension of Williams formula to handle non-equiprobable faults is proposed. Results of applying this method to a set of real IC design examples confirm the usefulness of this approach.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116651171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224351
C. Oh, H. Youn, V. K. Raj
Fault tolerance has been an important issue for systems involving intensive computations using a large number of processing elements. To effectively tolerate operation time faults in the systems, algorithm-based fault tolerance designs have been developed. Extended rearranged Hamming checksum scheme is proposed as an algorithm-based fault tolerance design. It is based on the rearranged Hamming checksum code with newly introduced negative elements in the checksum matrix. The overflow and round-off error probability of the scheme are greatly reduced compared to earlier designs, while both time latency and hardware overheads are small. Two important matrix computations are selected to show how the scheme works. Performance of the proposed design is evaluated and compared with those of existing schemes through computer simulation.<>
{"title":"An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum","authors":"C. Oh, H. Youn, V. K. Raj","doi":"10.1109/DFTVS.1992.224351","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224351","url":null,"abstract":"Fault tolerance has been an important issue for systems involving intensive computations using a large number of processing elements. To effectively tolerate operation time faults in the systems, algorithm-based fault tolerance designs have been developed. Extended rearranged Hamming checksum scheme is proposed as an algorithm-based fault tolerance design. It is based on the rearranged Hamming checksum code with newly introduced negative elements in the checksum matrix. The overflow and round-off error probability of the scheme are greatly reduced compared to earlier designs, while both time latency and hardware overheads are small. Two important matrix computations are selected to show how the scheme works. Performance of the proposed design is evaluated and compared with those of existing schemes through computer simulation.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128950680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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