Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224364
R. Harris
Two complementary approaches used to detect and quantify defects in a wafer fabrication line are described. The first approach uses data from the automated inspection of wafers. Defects that are likely to become electrical faults are identified and classified with the aid of a KLA 2020 inspection system. The second approach uses electrical fault data from the automated testing of defect test structures. The defects responsible for the faults are classified by visual inspection. This paper describes the models used to report the data from each of these sources. A clustering model is used in both cases to report the data as a defect density or a limited yield. Examples show the use of these reports to guide yield improvement activities in a production wafer fabrication facility.<>
{"title":"Defect density assessment in an integrated circuit fabrication line","authors":"R. Harris","doi":"10.1109/DFTVS.1992.224364","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224364","url":null,"abstract":"Two complementary approaches used to detect and quantify defects in a wafer fabrication line are described. The first approach uses data from the automated inspection of wafers. Defects that are likely to become electrical faults are identified and classified with the aid of a KLA 2020 inspection system. The second approach uses electrical fault data from the automated testing of defect test structures. The defects responsible for the faults are classified by visual inspection. This paper describes the models used to report the data from each of these sources. A clustering model is used in both cases to report the data as a defect density or a limited yield. Examples show the use of these reports to guide yield improvement activities in a production wafer fabrication facility.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122806820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224342
V. Chiluvuri, I. Koren
Improvements in manufacturing lines alone can not compensate for the yield losses due to the increase in complexity of logic. Manufacturing yield improvement needs to be addressed during the physical layout synthesis stage itself. Several layout strategies for yield enhancement are proposed and they are illustrated with respect to channel compaction and routing in standard cell design. Algorithms and other implementation issues are discussed and examples illustrating these algorithms are presented.<>
{"title":"New routing and compaction strategies for yield enhancement","authors":"V. Chiluvuri, I. Koren","doi":"10.1109/DFTVS.1992.224342","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224342","url":null,"abstract":"Improvements in manufacturing lines alone can not compensate for the yield losses due to the increase in complexity of logic. Manufacturing yield improvement needs to be addressed during the physical layout synthesis stage itself. Several layout strategies for yield enhancement are proposed and they are illustrated with respect to channel compaction and routing in standard cell design. Algorithms and other implementation issues are discussed and examples illustrating these algorithms are presented.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129879175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224378
Arun Kumar Somani, J. Wang
Studies fault diagnosis based on a realistic probabilistic model for wafer-scale multiprocessor systems. In this model, an individual processor fails independently with probability p. The authors use a comparison testing approach. The testing is performed in multiple stages by the processors. They assume that different testing tasks are executed in different stages, and the coverage of each testing task is imperfect and is represented by a parameter c/sub v/. Imperfect coverage can be used to model intermittent faults where individual test may be incapable of detecting a fault. The authors present an efficient distributed self-diagnosis algorithm that probabilistically identifies faulty and fault free units. They show that our algorithm achieves very high accuracy even when the system is sparsely interconnected, and a large number of faulty units are present in the system.<>
{"title":"Probabilistic diagnosis in wafer-scale systems","authors":"Arun Kumar Somani, J. Wang","doi":"10.1109/DFTVS.1992.224378","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224378","url":null,"abstract":"Studies fault diagnosis based on a realistic probabilistic model for wafer-scale multiprocessor systems. In this model, an individual processor fails independently with probability p. The authors use a comparison testing approach. The testing is performed in multiple stages by the processors. They assume that different testing tasks are executed in different stages, and the coverage of each testing task is imperfect and is represented by a parameter c/sub v/. Imperfect coverage can be used to model intermittent faults where individual test may be incapable of detecting a fault. The authors present an efficient distributed self-diagnosis algorithm that probabilistically identifies faulty and fault free units. They show that our algorithm achieves very high accuracy even when the system is sparsely interconnected, and a large number of faulty units are present in the system.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121985078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224352
H. Ito, E. Hosoya
A novel design of a hypercube network (HC) on WSI (wafer scale integration) is proposed. the design makes both static and dynamic reconfigurations feasible. A WSI HC design by applying the Diogenes method to a planar structure has been proposed. However, in Diogenes method, every time a wire passes a processing element (PE), it passes at least one FET. Therefore, the design has a drawback that there are many FETs in a link between PEs and then it brings a large communication delay time. The design proposed here reduces the number of FETs in a link between PEs by utilizing two channels, called shift channel and basic channel for reconfiguration. The design can be accomplished by using a structure in which FETs are contained only in shift channels but not in basic channels. The channel is a bundle of wires which has a track width sufficient to make sub-HCs. A switch in the shift channel is similar to the switch of Diogenes method, but it is newly designed as a dedicated one.<>
{"title":"A WSI hypercube design using shift channels","authors":"H. Ito, E. Hosoya","doi":"10.1109/DFTVS.1992.224352","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224352","url":null,"abstract":"A novel design of a hypercube network (HC) on WSI (wafer scale integration) is proposed. the design makes both static and dynamic reconfigurations feasible. A WSI HC design by applying the Diogenes method to a planar structure has been proposed. However, in Diogenes method, every time a wire passes a processing element (PE), it passes at least one FET. Therefore, the design has a drawback that there are many FETs in a link between PEs and then it brings a large communication delay time. The design proposed here reduces the number of FETs in a link between PEs by utilizing two channels, called shift channel and basic channel for reconfiguration. The design can be accomplished by using a structure in which FETs are contained only in shift channels but not in basic channels. The channel is a bundle of wires which has a track width sufficient to make sub-HCs. A switch in the shift channel is similar to the switch of Diogenes method, but it is newly designed as a dedicated one.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224350
Y. Hsu, E. Swartzlander
Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<>
{"title":"Time redundant error correcting adders and multipliers","authors":"Y. Hsu, E. Swartzlander","doi":"10.1109/DFTVS.1992.224350","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224350","url":null,"abstract":"Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224349
D. Dance, R. Jarvis
Yield models may be applied to increase the yield learning rate in semiconductor manufacture. Detailed equipment models can be used to predict the defect-limited yield from estimates of particles added per wafer pass. These general yield models may be refined to reflect specific processes, equipment, and design rules in more accurate critical area estimates. After validation, refined models can be applied to direct particle reduction and yield improvement efforts amid conflicting priorities. Yield improvements have been demonstrated by applying defect-limited yield models in a production manufacturing facility.<>
{"title":"Application of yield models for semiconductor yield improvement","authors":"D. Dance, R. Jarvis","doi":"10.1109/DFTVS.1992.224349","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224349","url":null,"abstract":"Yield models may be applied to increase the yield learning rate in semiconductor manufacture. Detailed equipment models can be used to predict the defect-limited yield from estimates of particles added per wafer pass. These general yield models may be refined to reflect specific processes, equipment, and design rules in more accurate critical area estimates. After validation, refined models can be applied to direct particle reduction and yield improvement efforts amid conflicting priorities. Yield improvements have been demonstrated by applying defect-limited yield models in a production manufacturing facility.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224370
A. Nayak, L. Pagli, N. Santoro
For a given design, it is not difficult to identify a set of elements whose failure will have catastrophic consequence. There exist many patterns (random distribution) of faults, not in a block, which can be fatal for the system. Therefore, the characterization of such fault patterns is crucial for the identification, testing and detection of such catastrophic events. This paper, is concerned with the development of efficient recognition schemes; that is, efficient mechanisms which automatically determine whether or not an observed/detected pattern of faults will have catastrophic consequences. The problem of recognizing whether a fault pattern is catastrophic has been addressed.<>
{"title":"Recognition of catastrophic faults","authors":"A. Nayak, L. Pagli, N. Santoro","doi":"10.1109/DFTVS.1992.224370","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224370","url":null,"abstract":"For a given design, it is not difficult to identify a set of elements whose failure will have catastrophic consequence. There exist many patterns (random distribution) of faults, not in a block, which can be fatal for the system. Therefore, the characterization of such fault patterns is crucial for the identification, testing and detection of such catastrophic events. This paper, is concerned with the development of efficient recognition schemes; that is, efficient mechanisms which automatically determine whether or not an observed/detected pattern of faults will have catastrophic consequences. The problem of recognizing whether a fault pattern is catastrophic has been addressed.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126764811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224373
N. Faroughi
The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maximum regeneration distance be applied last. For the non-OISAs, reconfigurable functional routers in each cell is proposed. A non-OISA can be reconfigured into one or more OISAs.<>
{"title":"Time complexity of systolic array testing","authors":"N. Faroughi","doi":"10.1109/DFTVS.1992.224373","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224373","url":null,"abstract":"The testing time for a C-testable orthogonal iterative systolic array (OISA) is derived where no knowledge on cell functions are assumed. The test inputs are regenerated as inputs for some inner cells at some future times at known distances (regeneration distances) from the outputs of those cells which are currently being tested. For minimum test time, it is required that the test input with maximum regeneration distance be applied last. For the non-OISAs, reconfigurable functional routers in each cell is proposed. A non-OISA can be reconfigured into one or more OISAs.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"376 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123438039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224375
D. Wessels, J. Muzio
Proposes a combination of PLA decomposition and unidirectional error detecting techniques which permits concurrent testing for all single faults in a circuit (both in the decomposed modules and on the interconnection lines), for a lower area overhead cost than is normally associated with unidirectional error detecting codes.<>
{"title":"PLA decomposition to reduce the cost of concurrent checking","authors":"D. Wessels, J. Muzio","doi":"10.1109/DFTVS.1992.224375","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224375","url":null,"abstract":"Proposes a combination of PLA decomposition and unidirectional error detecting techniques which permits concurrent testing for all single faults in a circuit (both in the decomposed modules and on the interconnection lines), for a lower area overhead cost than is normally associated with unidirectional error detecting codes.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224343
C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia
The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lower bound.<>
{"title":"Improved layer assignment for packaging multichip modules","authors":"C.-H. Chen, M.H. Heydari, I. Tollis, C. Xia","doi":"10.1109/DFTVS.1992.224343","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224343","url":null,"abstract":"The layer assignment problem plays an important role in packaging multichip modules, since the number of layers is directly related to the cost of the final product. In this paper, the authors propose a new model for the problem and a heuristic layer assignment algorithm based on the new model. The experimental results presented show that the solution provided by the algorithm is close to the lower bound.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"51 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125561032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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