Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224347
L. Breveglieri, V. Piuri, D. Sciuto
A comprehensive discussion of a dedicated device for serial complex multiplication is presented, covering architectural, reliability and fault tolerance properties. The pipelined architecture is briefly described. It is optimized w.r.t. several figure of merits: clock rate, external pipelining and pipeline filling degree. Testability features are analyzed under functional fault models by means of graph-theoretic methods, showing full testability of the device. Error detection is introduced by means of arithmetic codes and the tradeoff between error detection and cost is evaluated. Eventually on-line reconfiguration is introduced through the Diogenes approach and the tradeoff between fault tolerance and cost is also discussed. Discussion are based on analytic interpolation software simulation and the evaluation of prototypal layouts in CMOS technology.<>
{"title":"A fast pipelined complex multiplier: the fault tolerance issues","authors":"L. Breveglieri, V. Piuri, D. Sciuto","doi":"10.1109/DFTVS.1992.224347","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224347","url":null,"abstract":"A comprehensive discussion of a dedicated device for serial complex multiplication is presented, covering architectural, reliability and fault tolerance properties. The pipelined architecture is briefly described. It is optimized w.r.t. several figure of merits: clock rate, external pipelining and pipeline filling degree. Testability features are analyzed under functional fault models by means of graph-theoretic methods, showing full testability of the device. Error detection is introduced by means of arithmetic codes and the tradeoff between error detection and cost is evaluated. Eventually on-line reconfiguration is introduced through the Diogenes approach and the tradeoff between fault tolerance and cost is also discussed. Discussion are based on analytic interpolation software simulation and the evaluation of prototypal layouts in CMOS technology.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133438819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224348
I. Koren, Z. Koren, C. Stapper
Defect maps of 57 wafers containing large area VLSI ICs were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. The main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area ICs. Even the recently proposed medium size clustering model, although closer to the empirical distribution than other known distributions, is not good enough. To obtain a good match, either a combination of two theoretical distributions or a 'censoring' procedure (i.e. ignoring the worst chips) is necessary.<>
{"title":"Analysis of defect maps of large area VLSI ICs","authors":"I. Koren, Z. Koren, C. Stapper","doi":"10.1109/DFTVS.1992.224348","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224348","url":null,"abstract":"Defect maps of 57 wafers containing large area VLSI ICs were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. The main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area ICs. Even the recently proposed medium size clustering model, although closer to the empirical distribution than other known distributions, is not good enough. To obtain a good match, either a combination of two theoretical distributions or a 'censoring' procedure (i.e. ignoring the worst chips) is necessary.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125978838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224358
P. Furth, A. Andreou
Investigates the estimation of fault probabilities and yield for analog VLSI implementations of neural computation. The analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. The work improves on the framework suggested recently by Feltham and Maly (1991) and is also applicable to analog or mixed analog/digital VLSI systems.<>
{"title":"On fault probabilities and yield models for analog VLSI neural networks","authors":"P. Furth, A. Andreou","doi":"10.1109/DFTVS.1992.224358","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224358","url":null,"abstract":"Investigates the estimation of fault probabilities and yield for analog VLSI implementations of neural computation. The analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. The work improves on the framework suggested recently by Feltham and Maly (1991) and is also applicable to analog or mixed analog/digital VLSI systems.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224374
J. Li, E. Swartzlander
Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used to make RERO feasible. This control hardware may add additional faults which are different from the bit-slice faults in the ALU. In this approach, by adding only one spare bit slice in the arithmetic logic unit, RERO is possible for error detection of logical and arithmetic operations in either ripple carry adders and carry lookahead adders without any additional hardware control unit. Proof will be given that RERO-k can detect (k mod n) consecutive errors in logical operations and (k mod (n+1)-1) consecutive errors in arithmetic operations, where n is the length of the original arithmetic logic unit. This demonstrates that RERO preserves all the error detection features of RESO. With less hardware, time redundancy and more flexibility for error detection, the approach makes RERO more appropriate for VLSI designs.<>
分析了在算术逻辑单元中通过k位旋转操作数重计算(RERO-k)的并发错误检测。尽管RERO-k被认为是对操作数移位k位的重计算的扩展(RESO-k)，但RERO对算术运算的实现及其在前瞻加法上的应用并没有被展示。它声称，应该使用复杂的控制单元，使reo可行。这种控制硬件可能会增加与ALU中的位片故障不同的额外故障。在这种方法中，通过在算术逻辑单元中仅添加一个备用位片，RERO可以在不需要任何额外硬件控制单元的情况下对纹波进位加法器和进位前瞻加法器中的逻辑和算术操作进行错误检测。证明RERO-k可以检测出逻辑运算中的(k mod n)个连续错误和算术运算中的(k mod (n+1)-1)个连续错误，其中n为原算术逻辑单元的长度。这说明reo保留了RESO的所有错误检测特征。该方法具有更少的硬件，时间冗余和更灵活的错误检测，使RERO更适合VLSI设计。
{"title":"Concurrent error detection in ALUs by recomputing with rotated operands","authors":"J. Li, E. Swartzlander","doi":"10.1109/DFTVS.1992.224374","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224374","url":null,"abstract":"Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used to make RERO feasible. This control hardware may add additional faults which are different from the bit-slice faults in the ALU. In this approach, by adding only one spare bit slice in the arithmetic logic unit, RERO is possible for error detection of logical and arithmetic operations in either ripple carry adders and carry lookahead adders without any additional hardware control unit. Proof will be given that RERO-k can detect (k mod n) consecutive errors in logical operations and (k mod (n+1)-1) consecutive errors in arithmetic operations, where n is the length of the original arithmetic logic unit. This demonstrates that RERO preserves all the error detection features of RESO. With less hardware, time redundancy and more flexibility for error detection, the approach makes RERO more appropriate for VLSI designs.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132945335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224365
S. Riley
In the absence of in-line electrical test monitors, semiconductor manufacturers must rely on data from optical inspections to identify and control defects. To be effective, optical inspection must be reduced to terms which have physical significance to the process engineer. The data must be able to show trends over time, distributions of defect types causing the most harm to the product, and net change after elimination of defects. Further, it must be able to predict the health of product with a high degree of consistency. This paper describes how optical defect inspection, using large-area detection and a consistent automatic sampling algorithm, can be used to monitor and control defect levels on product. This method has been a significant contributor to rapid defect learning on the 16-Mb DRAM manufacturing line at IBM.<>
{"title":"Optical inspection of wafers using large-area defect detection and sampling","authors":"S. Riley","doi":"10.1109/DFTVS.1992.224365","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224365","url":null,"abstract":"In the absence of in-line electrical test monitors, semiconductor manufacturers must rely on data from optical inspections to identify and control defects. To be effective, optical inspection must be reduced to terms which have physical significance to the process engineer. The data must be able to show trends over time, distributions of defect types causing the most harm to the product, and net change after elimination of defects. Further, it must be able to predict the health of product with a high degree of consistency. This paper describes how optical defect inspection, using large-area detection and a consistent automatic sampling algorithm, can be used to monitor and control defect levels on product. This method has been a significant contributor to rapid defect learning on the 16-Mb DRAM manufacturing line at IBM.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"97 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224345
M. Maccanelli, A. Halliday, B. Bell, D. Steiss, K. Butler
As the sizes of electronic products grow larger, the process of diagnosing failed components becomes increasingly complex. The problem is compounded by the fact that there exists no unified system with which to diagnose problems at all levels of the product design-integrated circuit (IC), printed circuit board (PCB), and system. This paper presents the results of an industrial experiment with techniques for automating the diagnosis process. The authors have developed a prototype automated fault diagnosis (AFD) system which can input a fault dictionary from either of two different commercial ATPG systems along with results from test pattern application and produce a list of candidate defect sites within a given circuit. The authors ran the prototype against simulated single and multiple stuck-at faults in a portion of a commercial floating point unit and at the PCB level using a special test PCB. Results have been encouraging in that the authors have obtained fairly accurate diagnoses with relatively low coverage stuck-at fault sets and in the presence of simulated non-classical defects. It is possible to produce a uniform methodology for AFD at the IC and PCB levels.<>
{"title":"Practical application of automated fault diagnosis at the chip and board levels","authors":"M. Maccanelli, A. Halliday, B. Bell, D. Steiss, K. Butler","doi":"10.1109/DFTVS.1992.224345","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224345","url":null,"abstract":"As the sizes of electronic products grow larger, the process of diagnosing failed components becomes increasingly complex. The problem is compounded by the fact that there exists no unified system with which to diagnose problems at all levels of the product design-integrated circuit (IC), printed circuit board (PCB), and system. This paper presents the results of an industrial experiment with techniques for automating the diagnosis process. The authors have developed a prototype automated fault diagnosis (AFD) system which can input a fault dictionary from either of two different commercial ATPG systems along with results from test pattern application and produce a list of candidate defect sites within a given circuit. The authors ran the prototype against simulated single and multiple stuck-at faults in a portion of a commercial floating point unit and at the PCB level using a special test PCB. Results have been encouraging in that the authors have obtained fairly accurate diagnoses with relatively low coverage stuck-at fault sets and in the presence of simulated non-classical defects. It is possible to produce a uniform methodology for AFD at the IC and PCB levels.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123883176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224353
W.B. Noghani, I. Jalowiecki
A yield model is developed to estimate yield values for an associative processing chip based largely on content addressable memory (CAM). The yield model combines analysis of a row redundant strategy for the CAM with a relaxation of design rules to minimise column defects.<>
{"title":"Design rule centring for row redundant content addressable memories","authors":"W.B. Noghani, I. Jalowiecki","doi":"10.1109/DFTVS.1992.224353","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224353","url":null,"abstract":"A yield model is developed to estimate yield values for an associative processing chip based largely on content addressable memory (CAM). The yield model combines analysis of a row redundant strategy for the CAM with a relaxation of design rules to minimise column defects.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"64 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114117892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224367
R. Libeskind-Hadas, N. Shrivastava, R. Melhem, C.L. Liu
Considers the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable. Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. It is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that this algorithm is very effective.<>
{"title":"Efficient bi-level reconfiguration algorithms for fault tolerant arrays","authors":"R. Libeskind-Hadas, N. Shrivastava, R. Melhem, C.L. Liu","doi":"10.1109/DFTVS.1992.224367","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224367","url":null,"abstract":"Considers the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable. Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. It is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that this algorithm is very effective.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115943649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224346
L. Dadda, M. Sami
A family of convolvers for high sample rate is proposed, based on the composition of subconvolvers characterized by one bit samples and by modular, regular structures decomposable in identical bit-slices. Samples are represented in parallel or in skew form and the whole circuit is a sequential circuit whose combinatorial part is an array of full adders, assuring a high sampling rate. Fault tolerance provisions are also discussed.<>
{"title":"High-speed parallel input-output bit-sliced fault-tolerant convolvers","authors":"L. Dadda, M. Sami","doi":"10.1109/DFTVS.1992.224346","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224346","url":null,"abstract":"A family of convolvers for high sample rate is proposed, based on the composition of subconvolvers characterized by one bit samples and by modular, regular structures decomposable in identical bit-slices. Samples are represented in parallel or in skew form and the whole circuit is a sequential circuit whose combinatorial part is an array of full adders, assuring a high sampling rate. Fault tolerance provisions are also discussed.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-04DOI: 10.1109/DFTVS.1992.224377
A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe
Describes how defect tolerance is achieved for a wafer scale architecture that has been implemented on silicon. It gives an overview of a long-term research effort and describes software methods and tools as well as hardware switching devices used to create a defect free 2D array at end of manufacturing. This wafer scale architecture is called ELSA (European Large SIMD Array) and has been studied within an ESPRIT project on wafer scale integration.<>
{"title":"Lessons learnt from designing a wafer scale 2D array","authors":"A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe","doi":"10.1109/DFTVS.1992.224377","DOIUrl":"https://doi.org/10.1109/DFTVS.1992.224377","url":null,"abstract":"Describes how defect tolerance is achieved for a wafer scale architecture that has been implemented on silicon. It gives an overview of a long-term research effort and describes software methods and tools as well as hardware switching devices used to create a defect free 2D array at end of manufacturing. This wafer scale architecture is called ELSA (European Large SIMD Array) and has been studied within an ESPRIT project on wafer scale integration.<<ETX>>","PeriodicalId":319218,"journal":{"name":"Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"663 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123048709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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