Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620192
Satwik Gali, Eric Wauer, T. Nikoubin
For decades, Error Correction Codes (ECC) have been extensively used to protect the data in registers and memory from errors. The most used ECC’s are Single Error Correction (SEC) codes, which can correct a one-bit error for each word. Due to the recent scale-down in the size of technology, the demand for low power, high speed, and area & energy efficient SEC encoders and decoders have become prominent. Many applications, like IoT devices, memory storage and security applications employing SECs, need reliable hardware at low cost and low power consumption. Significant research has been going on to design efficient ECC’s for energy efficiency and cost optimization. In this paper, Cell Design Methodology (CDM) as an efficient logic style is used for optimization of ECC at the transistor level for improving circuit characteristics. A significant improvement has been recorded by comparing the performance of the SEC codes in terms of power and energy between conventional CMOS (C-CMOS) and CDM logic structures. C-CMOS and CDM standard cells of 10nm, 14nm, 16nm, and 20nm technologies are used to compare the circuit characteristics of the SEC encoder and decoder. The traditional Hamming code and Pedro’s SEC [1] have been used for effective comparison and performance analysis of the cell libraries. This analysis has shown an average improvement of 32.4% on power consumption and 30% on energy consumption by using CDM logic style over the C-CMOS structure.
{"title":"Low Power and Energy Efficient Single Error Correction Code using CDM logic style for IoT devices","authors":"Satwik Gali, Eric Wauer, T. Nikoubin","doi":"10.1109/DCAS.2018.8620192","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620192","url":null,"abstract":"For decades, Error Correction Codes (ECC) have been extensively used to protect the data in registers and memory from errors. The most used ECC’s are Single Error Correction (SEC) codes, which can correct a one-bit error for each word. Due to the recent scale-down in the size of technology, the demand for low power, high speed, and area & energy efficient SEC encoders and decoders have become prominent. Many applications, like IoT devices, memory storage and security applications employing SECs, need reliable hardware at low cost and low power consumption. Significant research has been going on to design efficient ECC’s for energy efficiency and cost optimization. In this paper, Cell Design Methodology (CDM) as an efficient logic style is used for optimization of ECC at the transistor level for improving circuit characteristics. A significant improvement has been recorded by comparing the performance of the SEC codes in terms of power and energy between conventional CMOS (C-CMOS) and CDM logic structures. C-CMOS and CDM standard cells of 10nm, 14nm, 16nm, and 20nm technologies are used to compare the circuit characteristics of the SEC encoder and decoder. The traditional Hamming code and Pedro’s SEC [1] have been used for effective comparison and performance analysis of the cell libraries. This analysis has shown an average improvement of 32.4% on power consumption and 30% on energy consumption by using CDM logic style over the C-CMOS structure.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132083560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620115
A. Adha, M. Nourani
In this paper, we present a methodology to test faults induced by large deviations in components in analog circuits through multi-frequency test based on sensitivity analysis. Final compaction of the test frequencies is done using a covering table optimization method. Test Frequency compaction and choice of observation points are based on a novel notation of fault equivalence and sensitivity curves. Our case study shows this method can effectively minimize the sinusoid test frequencies to separate the fault-free and faulty operations of the circuit under test for all faulty components.
{"title":"Test Frequency Compaction for Fault Detection in Analog Circuits Using Sensitivity Analysis","authors":"A. Adha, M. Nourani","doi":"10.1109/DCAS.2018.8620115","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620115","url":null,"abstract":"In this paper, we present a methodology to test faults induced by large deviations in components in analog circuits through multi-frequency test based on sensitivity analysis. Final compaction of the test frequencies is done using a covering table optimization method. Test Frequency compaction and choice of observation points are based on a novel notation of fault equivalence and sensitivity curves. Our case study shows this method can effectively minimize the sinusoid test frequencies to separate the fault-free and faulty operations of the circuit under test for all faulty components.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129275659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620117
Zhengyu Peng, Prateek Nallabolu, Changzhi Li
This paper presents a portable 24-GHz multiple-input multiple-output (MIMO) radar with 16 transmit (Tx) channels and 16 receive (Rx) channels. The radar is intended for short-range localization and three-dimensional (3-D) imaging by detecting the ranges, azimuth angles, and zenith angles of targets in front of the radar. The radar is capable of two-dimensional (2-D) beamforming achieved using a non-uniformly spaced planar array. A prototype of this 16×16 radar has been built to demonstrate its short-range localization capability.
{"title":"Design and Calibration of a Portable 24-GHz 3-D MIMO FMCW Radar with a Non-uniformly Spaced Array and RF Front-End Coexisting on the Same PCB Layer","authors":"Zhengyu Peng, Prateek Nallabolu, Changzhi Li","doi":"10.1109/DCAS.2018.8620117","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620117","url":null,"abstract":"This paper presents a portable 24-GHz multiple-input multiple-output (MIMO) radar with 16 transmit (Tx) channels and 16 receive (Rx) channels. The radar is intended for short-range localization and three-dimensional (3-D) imaging by detecting the ranges, azimuth angles, and zenith angles of targets in front of the radar. The radar is capable of two-dimensional (2-D) beamforming achieved using a non-uniformly spaced planar array. A prototype of this 16×16 radar has been built to demonstrate its short-range localization capability.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123932073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620191
Heechai Kang, R. Gharpurey
A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.
{"title":"A Harmonic Rejection Downconverter with a GHz PWM-Based LO","authors":"Heechai Kang, R. Gharpurey","doi":"10.1109/DCAS.2018.8620191","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620191","url":null,"abstract":"A harmonic rejection downconverter that employs a pulse-width modulated local oscillator (PWM-LO) signal is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with signal-path switches decreases the sensitivity of the harmonic rejection ratio (HRR) to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620184
Md. Sakib Hasan, I. Mahbub, S. Islam, G. Rose
A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.
{"title":"A MOS-JFET Macromodel of SOI Four-Gate Transistors (G4FET) to Aid Innovative Circuit Design","authors":"Md. Sakib Hasan, I. Mahbub, S. Islam, G. Rose","doi":"10.1109/DCAS.2018.8620184","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620184","url":null,"abstract":"A MOS-JFET macromodel of silicon-on-insulator (SOI) four-gate transistor (G4FET) is presented in this paper to facilitate innovative circuit design with this novel multi-gate transistor. Designing interesting and innovative circuits with any new device requires a SPICE model that will work sufficiently well throughout the desired operating regions. A macromodel approach is adopted in this work which can provide a reasonably fast and accurate circuit simulation. Since G4FET combines the functionality of MOSFET and JFET devcies and robust, fast and reliable models of both MOSFET and JFET are already available, a macromodel combining these existing models is desirable from the perspective of a circuit designer. The model captures the essential interaction between multiple gates and accounts for both the volume and the surface conduction. In order to justify the feasibility of the macromodel, it is used to simulate two analog multiplier circuits which have been previously demonstrated experimentally and the simulation results match quite well with experimental findings.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131870547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620194
A. T. Zavareh, Julian Camilo Gomez Diaz, S. Hoyos
This work introduces a digital adaptive approach for the cancellation of harmonic distortion and inter-modulation products present in any receiver architecture. Principally, the low-noise amplifier (LNA), that is the first block on the receiver chain, must tolerate interference and guarantee high sensitivity. Linearization techniques must tackle several challenges such as adding minimum power consumption, preserving noise figure, and maintaining high matching and gain. In this article, a digital dual-path component based linearization technique will be introduced. The linearization is implemented by adding a nonlinear auxiliary path along with two constant coefficients used to cancel out the third order nonlinearities from the main path. Interestingly and unlike similar two path linearization techniques, the idea proposed in this paper requires a more non-linear auxiliary path, effectively relaxing the specifications to design the second path.
{"title":"Dual-Path Component Based Digital Receiver Linearization With a Very Non-linear Auxiliary Path","authors":"A. T. Zavareh, Julian Camilo Gomez Diaz, S. Hoyos","doi":"10.1109/DCAS.2018.8620194","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620194","url":null,"abstract":"This work introduces a digital adaptive approach for the cancellation of harmonic distortion and inter-modulation products present in any receiver architecture. Principally, the low-noise amplifier (LNA), that is the first block on the receiver chain, must tolerate interference and guarantee high sensitivity. Linearization techniques must tackle several challenges such as adding minimum power consumption, preserving noise figure, and maintaining high matching and gain. In this article, a digital dual-path component based linearization technique will be introduced. The linearization is implemented by adding a nonlinear auxiliary path along with two constant coefficients used to cancel out the third order nonlinearities from the main path. Interestingly and unlike similar two path linearization techniques, the idea proposed in this paper requires a more non-linear auxiliary path, effectively relaxing the specifications to design the second path.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/DCAS.2018.8620113
N. Tasneem, I. Mahbub
Significant advancements in miniaturized implantable electronics has given rise to a new dimension in the study of neuroscience. A low-noise neural amplifier is the first stage of an implantable electrophysiological signal recording system. This paper presents the design of a two-stage BiCMOS operational transconductance amplifier with reconfigurable bandwidth for the neural signal recording applications. The amplifier is designed using the standard 130 nm BiCMOS process. The designed amplifier achieves a closed-loop gain of 55.75 dB with a reconfigurable lower cut-off frequency of 0.13 Hz to 0.33 Hz and a higher cut-off frequency of 1.4 kHz. The reconfigurable bandwidth has been implemented by controlling the gate bias voltage of a pair of triple-well nMOS transistors working as the pseudoresistors in the feedback path. The simulated input-referred noise of the amplifier is 3.89, 3.59, 2.77 μVrms integrated over the 0.13, 0.17 and 0.33 Hz to 1 kHz frequency band respectively. The total power consumption of the amplifier is 1.5 μW with a dc-offset voltage of 12.3 mV. The designed amplifier has a CMRR (common-mode rejection ratio) and PSRR (power supply rejection ratio) of 104.8 dB and 97 dB respectively. The performance of the designed amplifier shows a good compatibility with the low-frequency neural signal recording systems.
{"title":"A Low-power Low-noise Reconfigurable Bandwidth BiCMOS Neural Amplifier","authors":"N. Tasneem, I. Mahbub","doi":"10.1109/DCAS.2018.8620113","DOIUrl":"https://doi.org/10.1109/DCAS.2018.8620113","url":null,"abstract":"Significant advancements in miniaturized implantable electronics has given rise to a new dimension in the study of neuroscience. A low-noise neural amplifier is the first stage of an implantable electrophysiological signal recording system. This paper presents the design of a two-stage BiCMOS operational transconductance amplifier with reconfigurable bandwidth for the neural signal recording applications. The amplifier is designed using the standard 130 nm BiCMOS process. The designed amplifier achieves a closed-loop gain of 55.75 dB with a reconfigurable lower cut-off frequency of 0.13 Hz to 0.33 Hz and a higher cut-off frequency of 1.4 kHz. The reconfigurable bandwidth has been implemented by controlling the gate bias voltage of a pair of triple-well nMOS transistors working as the pseudoresistors in the feedback path. The simulated input-referred noise of the amplifier is 3.89, 3.59, 2.77 μVrms integrated over the 0.13, 0.17 and 0.33 Hz to 1 kHz frequency band respectively. The total power consumption of the amplifier is 1.5 μW with a dc-offset voltage of 12.3 mV. The designed amplifier has a CMRR (common-mode rejection ratio) and PSRR (power supply rejection ratio) of 104.8 dB and 97 dB respectively. The performance of the designed amplifier shows a good compatibility with the low-frequency neural signal recording systems.","PeriodicalId":320317,"journal":{"name":"2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126645659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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