Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292188
Y. Ko, Hyun-Soo Kang, Jae-Won Suh
This paper presents an enhanced fast motion estimation method where a search point sampling technique is combined with the adaptive search range algorithm (ASRA) based on the distribution of motion vector differences, which is our previous work. Since the ASRA is based on downsizing of search ranges for less computational complexity rather than sub-sampling of search points that is adopted by most of the fast algorithms, it results in smaller search areas where all points are considered as search points. Therefore, the conventional fast algorithms based on search point sampling techniques such as three-step search algorithm can be easily employed to the ASRA. As a result, we propose an algorithm where a part of the points within the search areas determined by the ASRA are sampled as the search points. Experimental results show that the proposed method reduces complexity of our ASRA by about 60% without quality degradation.
{"title":"Fast motion estimation algorithm combining search point sampling technique with adaptive search range algorithm","authors":"Y. Ko, Hyun-Soo Kang, Jae-Won Suh","doi":"10.1109/MWSCAS.2012.6292188","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292188","url":null,"abstract":"This paper presents an enhanced fast motion estimation method where a search point sampling technique is combined with the adaptive search range algorithm (ASRA) based on the distribution of motion vector differences, which is our previous work. Since the ASRA is based on downsizing of search ranges for less computational complexity rather than sub-sampling of search points that is adopted by most of the fast algorithms, it results in smaller search areas where all points are considered as search points. Therefore, the conventional fast algorithms based on search point sampling techniques such as three-step search algorithm can be easily employed to the ASRA. As a result, we propose an algorithm where a part of the points within the search areas determined by the ASRA are sampled as the search points. Experimental results show that the proposed method reduces complexity of our ASRA by about 60% without quality degradation.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134388165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292011
Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren
The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.
{"title":"A digitally calibrated current-steering DAC with current-splitting array","authors":"Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren","doi":"10.1109/MWSCAS.2012.6292011","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292011","url":null,"abstract":"The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292097
Hemant Balijepalli, M. Niamat
This paper presents a novel design of a Configurable Logic Block (CLB) for a Field Programmable Gate Array (FPGA) based on a computing scheme in nanoscale technology called the Quantum-dot Cellular Automata (QCA). In QCA technology, the cells made of quantum dots transmit information from one cell to the other based on Coulombic repulsion between the electrons. The main goal behind the design of the CLB is to ultimately design a miniscule nano FPGA without transistors for the `beyond CMOS era' of the 2020s. Unlike previous research in this area, the attempt here is to take advantage of the unique QCA features in building the architecture. It is found that the proposed CLB has less latency and occupies less number of cells as compared to earlier designs. Different components of the CLB including a (4×16) decoder, a D-latch, a multiplexer and an RS-flip flop are designed, and simulated using the QCADesigner tool for functional correctness.
{"title":"Design of a nanoscale Quantum-dot Cellular Automata Configurable Logic Block for FPGAs","authors":"Hemant Balijepalli, M. Niamat","doi":"10.1109/MWSCAS.2012.6292097","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292097","url":null,"abstract":"This paper presents a novel design of a Configurable Logic Block (CLB) for a Field Programmable Gate Array (FPGA) based on a computing scheme in nanoscale technology called the Quantum-dot Cellular Automata (QCA). In QCA technology, the cells made of quantum dots transmit information from one cell to the other based on Coulombic repulsion between the electrons. The main goal behind the design of the CLB is to ultimately design a miniscule nano FPGA without transistors for the `beyond CMOS era' of the 2020s. Unlike previous research in this area, the attempt here is to take advantage of the unique QCA features in building the architecture. It is found that the proposed CLB has less latency and occupies less number of cells as compared to earlier designs. Different components of the CLB including a (4×16) decoder, a D-latch, a multiplexer and an RS-flip flop are designed, and simulated using the QCADesigner tool for functional correctness.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134084900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292081
Amin Ojani, B. Mesgarzadeh, A. Alvandpour
A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.
{"title":"A process variation tolerant DLL-based UWB frequency synthesizer","authors":"Amin Ojani, B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/MWSCAS.2012.6292081","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292081","url":null,"abstract":"A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292202
Phi-Hung Pham, D. Jelača, C. Farabet, B. Martini, Yann LeCun, E. Culurciello
This paper presents a bio-inspired vision system-on-a-chip - neuFlow SoC implemented in the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks and other complex vision algorithms based on large numbers of convolutions and matrix-to-matrix operations. Post-layout characterization shows that the system delivers up to 320 GOPS with an average power consumption of 0.6 W. The power-efficiency and portability of this system is ideal for embedded vision-based devices, such as driver assistance, and robotic vision.
{"title":"NeuFlow: Dataflow vision processing system-on-a-chip","authors":"Phi-Hung Pham, D. Jelača, C. Farabet, B. Martini, Yann LeCun, E. Culurciello","doi":"10.1109/MWSCAS.2012.6292202","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292202","url":null,"abstract":"This paper presents a bio-inspired vision system-on-a-chip - neuFlow SoC implemented in the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks and other complex vision algorithms based on large numbers of convolutions and matrix-to-matrix operations. Post-layout characterization shows that the system delivers up to 320 GOPS with an average power consumption of 0.6 W. The power-efficiency and portability of this system is ideal for embedded vision-based devices, such as driver assistance, and robotic vision.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114304443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292017
Brandon M. Kelly, B. Rumberg, D. Graham
Sleep states are used in resource-constrained systems to conserve power, but they necessitate a wake-up circuit for detecting unpredictable events. In such systems, all information preceding a wake-up event will be forfeited. In this paper, we present an analog memory system that adaptively samples and records an input signal while the rest of the system sleeps, thereby preserving the information that would otherwise be lost. This system does so while consuming less than 3.52 μW. We also show how the adaptive sampling rate can be utilized to approximate the original signal using a minimal number of samples.
{"title":"An ultra-low-power analog memory system with an adaptive sampling rate","authors":"Brandon M. Kelly, B. Rumberg, D. Graham","doi":"10.1109/MWSCAS.2012.6292017","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292017","url":null,"abstract":"Sleep states are used in resource-constrained systems to conserve power, but they necessitate a wake-up circuit for detecting unpredictable events. In such systems, all information preceding a wake-up event will be forfeited. In this paper, we present an analog memory system that adaptively samples and records an input signal while the rest of the system sleeps, thereby preserving the information that would otherwise be lost. This system does so while consuming less than 3.52 μW. We also show how the adaptive sampling rate can be utilized to approximate the original signal using a minimal number of samples.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116864164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292171
Y. Hinamoto, A. Doi
Based on a pure l2 norm, the l2-sensitivity for canonical forms in one-dimensional (1-D) and two-dimensional (2-D) separable-denoninator state-space digital filters is analyzed more precisely by taking into account 0 and 1 elements. First, l2-sensitivity measures are explored for a controllable canonical form as well as an observable canonical form in state-space digital filters. Next, an l2-sensitivity measure is investigated for a canonical form in 2-D separable-denominator state-space digital filters. Finally, numerical examples are presented to compare the resulting l2-sensitivity measures with the conventional ones.
{"title":"Analysis of l2-sensitivity for canonical forms in 1-D and 2-D separable-denominator digital filters","authors":"Y. Hinamoto, A. Doi","doi":"10.1109/MWSCAS.2012.6292171","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292171","url":null,"abstract":"Based on a pure l2 norm, the l2-sensitivity for canonical forms in one-dimensional (1-D) and two-dimensional (2-D) separable-denoninator state-space digital filters is analyzed more precisely by taking into account 0 and 1 elements. First, l2-sensitivity measures are explored for a controllable canonical form as well as an observable canonical form in state-space digital filters. Next, an l2-sensitivity measure is investigated for a canonical form in 2-D separable-denominator state-space digital filters. Finally, numerical examples are presented to compare the resulting l2-sensitivity measures with the conventional ones.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116263112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292082
K. Yelamarthi, Stephen Sherbrook, Jonathan Beckwith, M. Williams, Rob Lefief
This paper describes a radio frequency identification (RFID) and sonar-guided tour guide robot, CATE (Central's Automated Tour Experience). The portable terminal unit is an embedded system equipped with an RFID reader for localization, and sonar and IR sensors for obstacle detection and avoidance. CATE can guide the visitor through a predefined tour of the building, or create a new route on-the-fly. While in predefined tour mode, CATE completes the tour by avoiding obstacles using sonar and infrared sensor input. It will also provide audio and video information through an onboard computer, and can collect feedback from the user through a touch screen display. CATE has been successfully implemented and is under final stages of testing.
本文介绍了一种无线射频识别(RFID)和声纳引导的导游机器人，CATE (Central's Automated tour Experience)。便携式终端单元是一个嵌入式系统，配备用于定位的RFID读取器，以及用于障碍物探测和回避的声纳和红外传感器。CATE可以引导游客通过预定义的建筑之旅，或创建一个新的动态路线。在预设的漫游模式下，CATE利用声纳和红外传感器的输入，避开障碍物，完成漫游。它还将通过机载计算机提供音频和视频信息，并可以通过触摸屏显示器收集用户的反馈。CATE已经成功实施，并处于测试的最后阶段。
{"title":"An RFID based autonomous indoor tour guide robot","authors":"K. Yelamarthi, Stephen Sherbrook, Jonathan Beckwith, M. Williams, Rob Lefief","doi":"10.1109/MWSCAS.2012.6292082","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292082","url":null,"abstract":"This paper describes a radio frequency identification (RFID) and sonar-guided tour guide robot, CATE (Central's Automated Tour Experience). The portable terminal unit is an embedded system equipped with an RFID reader for localization, and sonar and IR sensors for obstacle detection and avoidance. CATE can guide the visitor through a predefined tour of the building, or create a new route on-the-fly. While in predefined tour mode, CATE completes the tour by avoiding obstacles using sonar and infrared sensor input. It will also provide audio and video information through an onboard computer, and can collect feedback from the user through a touch screen display. CATE has been successfully implemented and is under final stages of testing.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115269044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291960
Ramzi Darraji, F. Ghannouchi, A. Kwan, M. Helaoui
This paper exposes a number of analog and digital techniques for performance enhancement of Doherty power amplifiers (PAs). After briefly introducing the operation principle of the Doherty PA, the gain and phase impairments between the main and auxiliary amplifiers as well as the problem of power drive waste into the auxiliary branch at the low power mode are analyzed. Due to the dynamic nature of these problems, analog-based approaches cannot completely compensate for them. The digital Doherty PA architecture is then pointed out as the most suitable topology that enables an optimal operation of the Doherty PA. This architecture allows for the implementation of advanced digital signal processing algorithms, such as adaptive input power distribution and dynamic phase alignment that are experimentally proven to bring substantial performance enhancement.
{"title":"Mixed analog/digital design of wireless Doherty power amplifiers and transmitters","authors":"Ramzi Darraji, F. Ghannouchi, A. Kwan, M. Helaoui","doi":"10.1109/MWSCAS.2012.6291960","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291960","url":null,"abstract":"This paper exposes a number of analog and digital techniques for performance enhancement of Doherty power amplifiers (PAs). After briefly introducing the operation principle of the Doherty PA, the gain and phase impairments between the main and auxiliary amplifiers as well as the problem of power drive waste into the auxiliary branch at the low power mode are analyzed. Due to the dynamic nature of these problems, analog-based approaches cannot completely compensate for them. The digital Doherty PA architecture is then pointed out as the most suitable topology that enables an optimal operation of the Doherty PA. This architecture allows for the implementation of advanced digital signal processing algorithms, such as adaptive input power distribution and dynamic phase alignment that are experimentally proven to bring substantial performance enhancement.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292180
Won-Jae Yi, Weidi Jia, J. Saniie
In this paper, we present a system using an Android smartphone that collects, displays sensor data on the screen and streams to the central server simultaneously. Bluetooth and wireless Internet connections are used for data transmissions among the devices. Also, using Near Field Communication (NFC) technology, we have constructed a more efficient and convenient mechanism to achieve an automatic Bluetooth connection and application execution. This system is beneficial on body sensor networks (BSN) developed for medical healthcare applications. For demonstration purposes, an accelerometer, a temperature sensor and electrocardiography (ECG) signal data are used to perform the experiments. Raw sensor data are interpreted to either graphical or text notations to be presented on the smartphone and the central server. Furthermore, a Java-based central server application is used to demonstrate communication with the Android system for data storage and analysis.
{"title":"Mobile sensor data collector using Android smartphone","authors":"Won-Jae Yi, Weidi Jia, J. Saniie","doi":"10.1109/MWSCAS.2012.6292180","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292180","url":null,"abstract":"In this paper, we present a system using an Android smartphone that collects, displays sensor data on the screen and streams to the central server simultaneously. Bluetooth and wireless Internet connections are used for data transmissions among the devices. Also, using Near Field Communication (NFC) technology, we have constructed a more efficient and convenient mechanism to achieve an automatic Bluetooth connection and application execution. This system is beneficial on body sensor networks (BSN) developed for medical healthcare applications. For demonstration purposes, an accelerometer, a temperature sensor and electrocardiography (ECG) signal data are used to perform the experiments. Raw sensor data are interpreted to either graphical or text notations to be presented on the smartphone and the central server. Furthermore, a Java-based central server application is used to demonstrate communication with the Android system for data storage and analysis.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124484114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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