Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292188
Y. Ko, Hyun-Soo Kang, Jae-Won Suh
This paper presents an enhanced fast motion estimation method where a search point sampling technique is combined with the adaptive search range algorithm (ASRA) based on the distribution of motion vector differences, which is our previous work. Since the ASRA is based on downsizing of search ranges for less computational complexity rather than sub-sampling of search points that is adopted by most of the fast algorithms, it results in smaller search areas where all points are considered as search points. Therefore, the conventional fast algorithms based on search point sampling techniques such as three-step search algorithm can be easily employed to the ASRA. As a result, we propose an algorithm where a part of the points within the search areas determined by the ASRA are sampled as the search points. Experimental results show that the proposed method reduces complexity of our ASRA by about 60% without quality degradation.
{"title":"Fast motion estimation algorithm combining search point sampling technique with adaptive search range algorithm","authors":"Y. Ko, Hyun-Soo Kang, Jae-Won Suh","doi":"10.1109/MWSCAS.2012.6292188","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292188","url":null,"abstract":"This paper presents an enhanced fast motion estimation method where a search point sampling technique is combined with the adaptive search range algorithm (ASRA) based on the distribution of motion vector differences, which is our previous work. Since the ASRA is based on downsizing of search ranges for less computational complexity rather than sub-sampling of search points that is adopted by most of the fast algorithms, it results in smaller search areas where all points are considered as search points. Therefore, the conventional fast algorithms based on search point sampling techniques such as three-step search algorithm can be easily employed to the ASRA. As a result, we propose an algorithm where a part of the points within the search areas determined by the ASRA are sampled as the search points. Experimental results show that the proposed method reduces complexity of our ASRA by about 60% without quality degradation.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134388165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292011
Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren
The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.
{"title":"A digitally calibrated current-steering DAC with current-splitting array","authors":"Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren","doi":"10.1109/MWSCAS.2012.6292011","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292011","url":null,"abstract":"The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292097
Hemant Balijepalli, M. Niamat
This paper presents a novel design of a Configurable Logic Block (CLB) for a Field Programmable Gate Array (FPGA) based on a computing scheme in nanoscale technology called the Quantum-dot Cellular Automata (QCA). In QCA technology, the cells made of quantum dots transmit information from one cell to the other based on Coulombic repulsion between the electrons. The main goal behind the design of the CLB is to ultimately design a miniscule nano FPGA without transistors for the `beyond CMOS era' of the 2020s. Unlike previous research in this area, the attempt here is to take advantage of the unique QCA features in building the architecture. It is found that the proposed CLB has less latency and occupies less number of cells as compared to earlier designs. Different components of the CLB including a (4×16) decoder, a D-latch, a multiplexer and an RS-flip flop are designed, and simulated using the QCADesigner tool for functional correctness.
{"title":"Design of a nanoscale Quantum-dot Cellular Automata Configurable Logic Block for FPGAs","authors":"Hemant Balijepalli, M. Niamat","doi":"10.1109/MWSCAS.2012.6292097","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292097","url":null,"abstract":"This paper presents a novel design of a Configurable Logic Block (CLB) for a Field Programmable Gate Array (FPGA) based on a computing scheme in nanoscale technology called the Quantum-dot Cellular Automata (QCA). In QCA technology, the cells made of quantum dots transmit information from one cell to the other based on Coulombic repulsion between the electrons. The main goal behind the design of the CLB is to ultimately design a miniscule nano FPGA without transistors for the `beyond CMOS era' of the 2020s. Unlike previous research in this area, the attempt here is to take advantage of the unique QCA features in building the architecture. It is found that the proposed CLB has less latency and occupies less number of cells as compared to earlier designs. Different components of the CLB including a (4×16) decoder, a D-latch, a multiplexer and an RS-flip flop are designed, and simulated using the QCADesigner tool for functional correctness.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134084900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292018
Alireza Nilchi, D. Johns
A low-power switched-capacitor (SC) gain stage based on a capacitive charge-pump (CP) is proposed. It is shown that the CP gain stage achieves the same input-referred thermal noise as a conventional SC gain circuit, while consuming significantly lower power. The effect of parasitic capacitances on the CP gain circuit is discussed. Simulation results confirming the improved power/performance trade-off of the CP gain stage over the conventional approach are provided.
{"title":"Charge-pump based switched-capacitor gain stage","authors":"Alireza Nilchi, D. Johns","doi":"10.1109/MWSCAS.2012.6292018","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292018","url":null,"abstract":"A low-power switched-capacitor (SC) gain stage based on a capacitive charge-pump (CP) is proposed. It is shown that the CP gain stage achieves the same input-referred thermal noise as a conventional SC gain circuit, while consuming significantly lower power. The effect of parasitic capacitances on the CP gain circuit is discussed. Simulation results confirming the improved power/performance trade-off of the CP gain stage over the conventional approach are provided.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124694388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292100
S. Eratne, E. John, Byeong Kil Lee
Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.
{"title":"Reducing thermal hotspots in microprocessors with expanded component sizing","authors":"S. Eratne, E. John, Byeong Kil Lee","doi":"10.1109/MWSCAS.2012.6292100","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292100","url":null,"abstract":"Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291964
Ko-Chung Tseng, A. C. Parker
Detecting moving objects in a moving background or a dynamic scene is essential to the survival of some animals. The circuitry computing differential motion is found in the biological retina. An object-motion-sensitivity (OMS) ganglion cell remains silent under global motion of the entire image but fires when the image patch in its receptive field moves differently from the background. In this paper, we present a neuromorphic circuit that compares the motion speeds of the central receptive field and peripheral receptive field. We demonstrate that there is a response if motion speeds of the central and peripheral receptive fields are different. However, the response is suppressed if motion speeds of central and peripheral receptive fields are the same.
{"title":"A neuromorphic circuit that computes differential motion","authors":"Ko-Chung Tseng, A. C. Parker","doi":"10.1109/MWSCAS.2012.6291964","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291964","url":null,"abstract":"Detecting moving objects in a moving background or a dynamic scene is essential to the survival of some animals. The circuitry computing differential motion is found in the biological retina. An object-motion-sensitivity (OMS) ganglion cell remains silent under global motion of the entire image but fires when the image patch in its receptive field moves differently from the background. In this paper, we present a neuromorphic circuit that compares the motion speeds of the central receptive field and peripheral receptive field. We demonstrate that there is a response if motion speeds of the central and peripheral receptive fields are different. However, the response is suppressed if motion speeds of central and peripheral receptive fields are the same.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132334065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292033
Yi Chen, A. Basu, M. Je
A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large `pseudo-resistors' needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier.
{"title":"A digitally assisted, pseudo-resistor-less amplifier in 65nm CMOS for neural recording applications","authors":"Yi Chen, A. Basu, M. Je","doi":"10.1109/MWSCAS.2012.6292033","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292033","url":null,"abstract":"A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large `pseudo-resistors' needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132933541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/ICECS.2012.6463551
Chao Li, Jordi Cosp-Vilella, H. Martínez
In this paper we show two different schemes to implement a field programmable circuit that can connect n capacitors as a charge-pump of, eventually, any topology and switching pattern. Capacitor connectivity is configured by means of registers that control multiplexers that, in turn, select the phase signal that controls each switch. It is also shown that, with any of these schemes, dynamic configuration of the circuit may be achieved by simply adding additional control phases.
{"title":"Field programmable switched capacitor voltage converter","authors":"Chao Li, Jordi Cosp-Vilella, H. Martínez","doi":"10.1109/ICECS.2012.6463551","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463551","url":null,"abstract":"In this paper we show two different schemes to implement a field programmable circuit that can connect n capacitors as a charge-pump of, eventually, any topology and switching pattern. Capacitor connectivity is configured by means of registers that control multiplexers that, in turn, select the phase signal that controls each switch. It is also shown that, with any of these schemes, dynamic configuration of the circuit may be achieved by simply adding additional control phases.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292081
Amin Ojani, B. Mesgarzadeh, A. Alvandpour
A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.
{"title":"A process variation tolerant DLL-based UWB frequency synthesizer","authors":"Amin Ojani, B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/MWSCAS.2012.6292081","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292081","url":null,"abstract":"A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292017
Brandon M. Kelly, B. Rumberg, D. Graham
Sleep states are used in resource-constrained systems to conserve power, but they necessitate a wake-up circuit for detecting unpredictable events. In such systems, all information preceding a wake-up event will be forfeited. In this paper, we present an analog memory system that adaptively samples and records an input signal while the rest of the system sleeps, thereby preserving the information that would otherwise be lost. This system does so while consuming less than 3.52 μW. We also show how the adaptive sampling rate can be utilized to approximate the original signal using a minimal number of samples.
{"title":"An ultra-low-power analog memory system with an adaptive sampling rate","authors":"Brandon M. Kelly, B. Rumberg, D. Graham","doi":"10.1109/MWSCAS.2012.6292017","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292017","url":null,"abstract":"Sleep states are used in resource-constrained systems to conserve power, but they necessitate a wake-up circuit for detecting unpredictable events. In such systems, all information preceding a wake-up event will be forfeited. In this paper, we present an analog memory system that adaptively samples and records an input signal while the rest of the system sleeps, thereby preserving the information that would otherwise be lost. This system does so while consuming less than 3.52 μW. We also show how the adaptive sampling rate can be utilized to approximate the original signal using a minimal number of samples.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116864164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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