Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362046
M. Noyori, Y. Nakata, S. Odanaka, J. Yasui
In order to evaluate the VT shift due to hot-carriers in submicron n-channel FETs with several kinds of graded junction structures as compared with a conventional structures, long term stress tests were conducted. As a result, it was found that the VT shifts observed in these devices were caused not by channel-hot-electron but by an avalanche-hot-carrier, which is probably a hot hole, and that the VT shift can be suppressed pronouncedly by the graded drain structures. This paper describes VT shift characteristics due to avalanche-hot-carriers compared with those due to channel-hot-carriers as well as the analysis of VT shift reduction mechanism in the graded drain structured devices.
{"title":"Reduction of VT Shift Due to Avalanche-Hot-Carrier Injection using Graded Drain Structures in Submicron N-Channel MOSFET","authors":"M. Noyori, Y. Nakata, S. Odanaka, J. Yasui","doi":"10.1109/IRPS.1984.362046","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362046","url":null,"abstract":"In order to evaluate the VT shift due to hot-carriers in submicron n-channel FETs with several kinds of graded junction structures as compared with a conventional structures, long term stress tests were conducted. As a result, it was found that the VT shifts observed in these devices were caused not by channel-hot-electron but by an avalanche-hot-carrier, which is probably a hot hole, and that the VT shift can be suppressed pronouncedly by the graded drain structures. This paper describes VT shift characteristics due to avalanche-hot-carriers compared with those due to channel-hot-carriers as well as the analysis of VT shift reduction mechanism in the graded drain structured devices.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131940188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362026
J. Patterson
A technique is described to accomplish junction temperature measurements in semiconductor devices in the scanning electron microscope. It details the procedure to produce high spatial resolution measurements and thermal gradient images of the true junction temperature. This approach combines the information in the electron beam induced current mode and the characteristic change in the forward voltage drop of a junction with temperature to produce a temperature reading at the site struck by the electron beam. Because this technique is essentially the same as the junction forward voltage drop method, the procedure first requires that the calibration curve of the junction under examination be determined. This calibration is performed in the SEM under the same conditions that the subsequent measurements are to be made. A means for heating the sample in the SEM is required. The critical SEM parameters are electron beam current and acceleration potential, as well as magnification or spot size. The electron beam of the SEM is the constant current source for the measurement and must be the same magnitude as in the calibration step.
{"title":"Semiconductor Junction Temperature Measurement using the Electron Beam Induced Current Mode in the Scanning Electron Miscroscope","authors":"J. Patterson","doi":"10.1109/IRPS.1984.362026","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362026","url":null,"abstract":"A technique is described to accomplish junction temperature measurements in semiconductor devices in the scanning electron microscope. It details the procedure to produce high spatial resolution measurements and thermal gradient images of the true junction temperature. This approach combines the information in the electron beam induced current mode and the characteristic change in the forward voltage drop of a junction with temperature to produce a temperature reading at the site struck by the electron beam. Because this technique is essentially the same as the junction forward voltage drop method, the procedure first requires that the calibration curve of the junction under examination be determined. This calibration is performed in the SEM under the same conditions that the subsequent measurements are to be made. A means for heating the sample in the SEM is required. The critical SEM parameters are electron beam current and acceleration potential, as well as magnification or spot size. The electron beam of the SEM is the constant current source for the measurement and must be the same magnitude as in the calibration step.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116233625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362054
H. Schafft, Curtis D. Younkins, T. C. Grant, Chi-Yi Kao, A. Saxena
Metal line structures with intentional defects in the passivation, to simulate cracks or pin holes, were used in electromigration studies. Results show that the stress changes in the metallization caused by these defects are not as important as the restraining action of the passivation in affecting a metallization's resistance to electromigration failure. Also, the observed effects of restorative forces acting on the metallization suggests that continuous monitoring for open-circuit failure may be necessary to obtain an accurate measure of the mean-time-to-failure.
{"title":"Effect of Passivation and Passivation Defects on Electromigration Failure in Aluminum Metallization","authors":"H. Schafft, Curtis D. Younkins, T. C. Grant, Chi-Yi Kao, A. Saxena","doi":"10.1109/IRPS.1984.362054","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362054","url":null,"abstract":"Metal line structures with intentional defects in the passivation, to simulate cracks or pin holes, were used in electromigration studies. Results show that the stress changes in the metallization caused by these defects are not as important as the restraining action of the passivation in affecting a metallization's resistance to electromigration failure. Also, the observed effects of restorative forces acting on the metallization suggests that continuous monitoring for open-circuit failure may be necessary to obtain an accurate measure of the mean-time-to-failure.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362055
E. Severn, H. Huston, J. Lloyd
Open-circuit as well as short-circuit failures can occur at regions where relief of electromigration-induced compressive stress is realized. These failures require that the restraining passivation layer surrounding the metal conductor gives way before either an extrusion or a void can form. This passivation layer is a sputtered SiO glass and is, consequently, quite brittle. Brittle materials do not yield, but rather deform via crack propagation. It is known that cracking of quartz results in an acoustic event that should be detectable with modern acoustic emission instruments.
{"title":"Acoustic Emission Study of Electromigration Damage in Al-Cu Thin Film Conductor Stripes","authors":"E. Severn, H. Huston, J. Lloyd","doi":"10.1109/IRPS.1984.362055","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362055","url":null,"abstract":"Open-circuit as well as short-circuit failures can occur at regions where relief of electromigration-induced compressive stress is realized. These failures require that the restraining passivation layer surrounding the metal conductor gives way before either an extrusion or a void can form. This passivation layer is a sputtered SiO glass and is, consequently, quite brittle. Brittle materials do not yield, but rather deform via crack propagation. It is known that cracking of quartz results in an acoustic event that should be detectable with modern acoustic emission instruments.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133120878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362037
Eila B. Spialter, J. Brandewie, R. Kjar
A complex charge trapping instability was identified in CMOS/SOS circuits which had failed during extended life tests. The cause of this instability was shown to be latent oxide damage from forced oxide currents during ion implantation. A conducting wafer coating during ion implant was found to eliminate the forced oxide current and to prevent the instability.
{"title":"An Ion Implant Induced Instability Mechanism in CMOS/SOS Device","authors":"Eila B. Spialter, J. Brandewie, R. Kjar","doi":"10.1109/IRPS.1984.362037","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362037","url":null,"abstract":"A complex charge trapping instability was identified in CMOS/SOS circuits which had failed during extended life tests. The cause of this instability was shown to be latent oxide damage from forced oxide currents during ion implantation. A conducting wafer coating during ion implant was found to eliminate the forced oxide current and to prevent the instability.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362028
D. Burgess, P. Tan
Liquid crystals have been used for various purposes in failure analysis for several years. Hiatt, using cholesteric liquid crystals, demonstrated that hot spots could be detected and readily photographed under polarized light [1]. West omitted the polarized light for simplicity, but applied a 5-20 Hz square wave pulse to the failing device to make initial detection of the defect easier [2]. Fleuren achieved great sensitivity by adding temperature control, but the steps required to routinely reproduce his success were not clear [3]. This paper introduces a new heating method and detailed observations for use of a particular nematic liquid crystal. The resulting technique is both sensitive and convenient.
{"title":"Improved Sensitivity for Hot Spot Detection using Liquid Crystals","authors":"D. Burgess, P. Tan","doi":"10.1109/IRPS.1984.362028","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362028","url":null,"abstract":"Liquid crystals have been used for various purposes in failure analysis for several years. Hiatt, using cholesteric liquid crystals, demonstrated that hot spots could be detected and readily photographed under polarized light [1]. West omitted the polarized light for simplicity, but applied a 5-20 Hz square wave pulse to the failing device to make initial detection of the defect easier [2]. Fleuren achieved great sensitivity by adding temperature control, but the steps required to routinely reproduce his success were not clear [3]. This paper introduces a new heating method and detailed observations for use of a particular nematic liquid crystal. The resulting technique is both sensitive and convenient.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362052
R. Hummel, S. Goho, R. Dehoff
Grain boundary grooving, thermotransport and electrotransport operate simultaneously during current stressing of thin film metallizations. For different operating conditions or positions along a stripe, they may compete or reinforce each other in promoting hole formation. This work demonstrates that second components may influence this competition in a variety of ways. As the interactions become better understood, they may ultimately provide the basis for controlling hole formation and predicting reliability of thin film stripes.
{"title":"The Role of Thermal Grooving, Thermotransport and Electrotransport on the Failure of Thin Film Metallizations","authors":"R. Hummel, S. Goho, R. Dehoff","doi":"10.1109/IRPS.1984.362052","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362052","url":null,"abstract":"Grain boundary grooving, thermotransport and electrotransport operate simultaneously during current stressing of thin film metallizations. For different operating conditions or positions along a stripe, they may compete or reinforce each other in promoting hole formation. This work demonstrates that second components may influence this competition in a variety of ways. As the interactions become better understood, they may ultimately provide the basis for controlling hole formation and predicting reliability of thin film stripes.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126625791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362022
F. Henley
An improved technique for using a focused laser beam to extract logical levels of internal IC transistors in a non-contact and non-destructive manner is introduced and described. Advances in the detection scheme coupled with computer control and signal processing allow automated operation. Various tests were performed on CMOS microprocessors to exemplify the frequency, noise, and drift insensitivity of the detection scheme. These results will be presented, along with a discussion on the practical use of the technique and its extension for testing NMOS and bipolar technologies.
{"title":"Logic Failure Analysis of CMOS VLSI using a Laser Probe","authors":"F. Henley","doi":"10.1109/IRPS.1984.362022","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362022","url":null,"abstract":"An improved technique for using a focused laser beam to extract logical levels of internal IC transistors in a non-contact and non-destructive manner is introduced and described. Advances in the detection scheme coupled with computer control and signal processing allow automated operation. Various tests were performed on CMOS microprocessors to exemplify the frequency, noise, and drift insensitivity of the detection scheme. These results will be presented, along with a discussion on the practical use of the technique and its extension for testing NMOS and bipolar technologies.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114529500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362024
R. Belcher, G. P. Hart, W. R. Wade
Five sample-preparation techniques for failure analysis and process evaluation of integrated circuits by electron microscopy are described. These novel yet simple techniques, each with several applications, provide valuable device data for personnel in various aspects of semiconductor reliability. Methods described include effective deglassivation techniques, data-filled cross-sectional preparations, an accurate measurement system for critical dimension features, a simple backside etch procedure to prepare TEM (Transmission Electron Microscopy) and AES (Auger Electron Spectroscopy) samples, and an etchback technique for metal step coverage reliability.
{"title":"Novel Sample Preparations for Microanalysis","authors":"R. Belcher, G. P. Hart, W. R. Wade","doi":"10.1109/IRPS.1984.362024","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362024","url":null,"abstract":"Five sample-preparation techniques for failure analysis and process evaluation of integrated circuits by electron microscopy are described. These novel yet simple techniques, each with several applications, provide valuable device data for personnel in various aspects of semiconductor reliability. Methods described include effective deglassivation techniques, data-filled cross-sectional preparations, an accurate measurement system for critical dimension features, a simple backside etch procedure to prepare TEM (Transmission Electron Microscopy) and AES (Auger Electron Spectroscopy) samples, and an etchback technique for metal step coverage reliability.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362025
T. May, G. Scott, E. S. Meieran, P. Winer, V. Rao
A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and fault-free devices are imaged separately by means of stroboscopic voltage contrast in a scanning electron microscope and are then stored as incremental time sequences of images. These sequences represent the time evolution of states during a particular device test and are then compared in an image array processor. The divergences or changes between the faulty and fault-free device evolutions represent faults, which are then displayed on a color monitor. The architecture and implementation of the Dynamic Fault Imager is described. Several examples using highly-integrated microprocessors are given, including the imaging of functional failures, voltage marginalities, and critical speed path mapping. A partial classification of faults is presented, as well as a discussion of future trends. The technique appears to have wide application to solving problems in the design and manufacturing of future VLSI devices.
{"title":"Dynamic Fault Imaging of VLSI Random Logic Devices","authors":"T. May, G. Scott, E. S. Meieran, P. Winer, V. Rao","doi":"10.1109/IRPS.1984.362025","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362025","url":null,"abstract":"A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and fault-free devices are imaged separately by means of stroboscopic voltage contrast in a scanning electron microscope and are then stored as incremental time sequences of images. These sequences represent the time evolution of states during a particular device test and are then compared in an image array processor. The divergences or changes between the faulty and fault-free device evolutions represent faults, which are then displayed on a color monitor. The architecture and implementation of the Dynamic Fault Imager is described. Several examples using highly-integrated microprocessors are given, including the imaging of functional failures, voltage marginalities, and critical speed path mapping. A partial classification of faults is presented, as well as a discussion of future trends. The technique appears to have wide application to solving problems in the design and manufacturing of future VLSI devices.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121534778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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