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Turn-On Voltage Degradation of Short Channel MOSFETs Due to Generation of Interface States 界面态的产生导致短沟道mosfet的导通电压下降
Pub Date : 1984-04-03 DOI: 10.1109/IRPS.1984.362047
I. Eisele, P. Vitanov, F. Fischer, U. Schwabe
For scaled Mos devices long term reliability of the turn-on voltage is important. Longterm stability of the turn-on voltage has been measured under stress aging for 2000 h (T=150°C. E=2.5×106V/cm). Generation of interface traps without essential flatband shift is observed. Despite that, positive turn-on voltage shift appears for effective channel lengths L<2.0¿m. The stress measurements have been performed on multitransistor structures which permit to measure interface traps, threshold voltage, and feature sizes on the same test structure. The relationship between the turn-on voltage shift and the interface trap density is discussed with respect to the effective channel length.
对于规模化Mos器件,导通电压的长期可靠性非常重要。在应力老化2000 h (T=150℃)下,测量了导通电压的长期稳定性。E = 2.5×106 v /厘米)。产生的界面陷阱没有必要的平带移位观察。尽管如此,当有效通道长度L<2.0¿m时,出现正的导通电压移位。应力测量已在多晶体管结构上进行,该结构允许在同一测试结构上测量界面陷阱、阈值电压和特征尺寸。从有效通道长度的角度讨论了导通电压位移与界面阱密度之间的关系。
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引用次数: 0
Phosphorus Migration Kinetics from PSG to Glass Passivation Surface 磷从PSG到玻璃钝化表面的迁移动力学
Pub Date : 1984-04-03 DOI: 10.1109/IRPS.1984.362050
G. Digiacomo
The diffusion of phosphorus through chip glass passivation is studied at various temperatures and water vapor pressures. The phosphorus diffuses from the phosphosilicate glass (PSG) to the glass surface through defects. It is detected by electron microprobe at low accelerating potential (3¿ kV) to avoid excitation of the underlying PSG. The amount of phosphorus transported varies proportionally to the water vapor pressure with an activation energy of 0.32 eV.
研究了磷在不同温度和水蒸汽压条件下通过玻璃片钝化的扩散。磷通过缺陷从磷硅酸盐玻璃(PSG)扩散到玻璃表面。电子探针在低加速电位(3¿kV)下检测,以避免激发底层PSG。磷的输运量与水蒸气压成正比,活化能为0.32 eV。
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引用次数: 3
Latch-Up Analysis on a 64K Bit Full CMOS Static RAM using a Laser Scanner 用激光扫描仪分析64K位全CMOS静态RAM的锁存现象
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362021
T. Shiragasawa, H. Shimura, K. Kagawa, T. Yonezawa, M. Noyori
In order to quantitatively evaluate latch-up sensitivity on scaled CMOS LSIs, an advanced latch-up analyzer with a laser scanner has been developed. As a result of the application of the analyzer to a 64K bit full CMOS static RAM, the analyzer was found to be very useful in latch-up evaluation on CMOS LSIs. Furthermore, high sensitivity regions in the memory cell and a sensitivity distribution in the memory array block, which depend on pattern layout, have been clearly observed on the static RAM.
为了定量评价CMOS lsi的锁存灵敏度,研制了一种先进的带激光扫描仪的锁存分析仪。由于该分析仪应用于64K位全CMOS静态RAM,该分析仪被发现在CMOS lsi的锁存器评估中非常有用。此外,在静态随机存储器上,可以清楚地观察到存储器单元中的高灵敏度区域和存储器阵列块中依赖于模式布局的灵敏度分布。
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引用次数: 5
Time Dependent Dielectric Breakdown Measurement of High Pressure Low Temperature Oxidized Film 高压低温氧化膜随时间介电击穿测量
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362034
M. Hirayama, T. Matsukawa, N. Tsubouchi, H. Nakata
Time dependent dielectric breakdown characteristics of the thin silicon dioxide films were automatically measured. These films were obtained from the high pressure low temperature oxidation of silicon. Breakdown failures were independent on the oxidation pressure but dependent on the oxidation temperature and film thickness. The electric field acceleration factor is estimated about 105.6/MV/cm.
自动测量了二氧化硅薄膜随时间变化的介电击穿特性。这些薄膜是由硅的高压低温氧化得到的。击穿失效与氧化压力无关,而与氧化温度和膜厚度有关。电场加速度因子约为105.6/MV/cm。
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引用次数: 11
Mechanism of Oxide Leakage Current of Silicide Gate MOSFET's 硅化栅极MOSFET的氧化物漏电流机理
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362044
T. Watanabe, H. Ishiuchi, T. Tanaka, T. Mochizuki, O. Ozawa
Oxide leakage currents of silicide gate MOSFET's have been studied. It has been revealed that large oxide leakage currents flow under the negative gate bias in spite of reasonable Fowler-Nordheim currents under the positive gate bias. Local electric field enhancement due to the interfacial molybdenum silicide asperity well explains the experimental results.
研究了硅化栅极MOSFET的氧化物泄漏电流。结果表明,尽管正栅偏压下存在合理的Fowler-Nordheim电流,但在负栅偏压下仍存在较大的氧化物泄漏电流。界面硅化钼的粗糙性引起的局部电场增强很好地解释了实验结果。
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引用次数: 0
Theoretical and Experimental Studies of Failure Mechanisms in Gallium Arsenide Three-Terminal Transferred Electron Devices 砷化镓三端转移电子器件失效机理的理论与实验研究
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362019
H. Grubin, W. Anderson, A. Christou
A two-dimensional transient numerical study of failure mechanisms in gallium arsenide transferred electron devices was undertaken. The simulation, which incorporates the effects of elevated temperature operation, mobility and donor density variations was designed to assess these contributions on device operation and reliability. The results of the study are consistent with a previously proposed reliability model and are discussed below.
对砷化镓转移电子器件失效机理进行了二维瞬态数值研究。该模拟结合了高温操作、移动性和供体密度变化的影响,旨在评估这些因素对设备运行和可靠性的影响。研究结果与先前提出的可靠性模型一致,并在下文进行讨论。
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引用次数: 0
Predicting Oxide Failure Rates using the Matrix of a 64K DRAM Chip 利用64K DRAM芯片矩阵预测氧化物故障率
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362027
D. Wendell, D. Segers, Billy Wang
Long-term integrity and stability of oxides is of prime concern in MOS reliability. This paper presents a test method for the in-situ prediction of thin film thermal oxide failure rates. The method is correlated with standard accelerated device studies.
氧化物的长期完整性和稳定性是MOS可靠性的首要考虑因素。本文提出了一种原位预测薄膜热氧化物故障率的测试方法。该方法与标准加速装置研究相关联。
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引用次数: 6
Comparative Electromigration Tests of Al-Cu Alloys Al-Cu合金的比较电迁移试验
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362056
P. Merchant, T. Cass
Al-Cu films, obtained from several sputter deposition processes have been subjected to accelerated electromigration life tests. The resultant median times to failure (ranging from 15-1600 h) have been compared with the microstructure and alloy distributions in the films as measured by He backscattering spectroscopy, transmission electron microscopy and diffraction and X-ray diffraction. We conclude that the film texture and location of copper in the films have a strong influence on their electromigration resistance.
通过几种溅射沉积工艺获得的Al-Cu薄膜进行了加速电迁移寿命试验。用He后向散射光谱、透射电子显微镜、衍射和x射线衍射测量了薄膜的显微组织和合金分布,并对所得的失效中位时间(15-1600 h)进行了比较。我们得出结论,薄膜的结构和铜在薄膜中的位置对其电迁移电阻有很大的影响。
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引用次数: 1
Determination of Reliability from Ramped Voltage Breakdown Experiments; Application to Dual Dielectric MIM Capacitors 斜电压击穿试验可靠性的确定双介质MIM电容器的应用
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362032
M. Shatzkes, M. Av-Ron, K. Srikrishnan
Ramped voltage breakdown experiments were used to derive the dependence of life-time, ¿(v), on the applied voltage for Ta2O5-Si3N4 dual dielectric capacitors. Techniques previously described allowed for recognition of defective capacitors, which break down early, and for the effect of trapping of injected carriers, which retards the breakdown. It is there. ore possible to determine ¿(v) for charge-free nondefective capacitors--a quantity of interest for reliability. For nonoptimistic reliability projections, ¿(v) must be obtained over a range in voltage so that log ¿(v) versus v exhibits, at the lower portion of that range, an upward concavity. Projections thus obtained were verified in a life-test.
用斜电压击穿实验推导了Ta2O5-Si3N4双介质电容器寿命¿(v)与外加电压的关系。先前描述的技术允许识别早期击穿的缺陷电容器,以及捕获注入载流子的效果,这延缓了击穿。它就在那里。有可能确定无电荷无缺陷电容器的¿(v) -可靠性的兴趣量。对于非乐观可靠性预测,必须在电压范围内获得¿(v),以便在该范围的较低部分,log¿(v) vs . v呈现向上的凹度。这样得到的投影在寿命试验中得到了验证。
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引用次数: 2
Reliability/Design Assessment by Internal-Node Timing-Margin Analysis using Laser Photocurrent-Injection 激光光电注入内节点时间裕度分析的可靠性/设计评估
Pub Date : 1984-04-01 DOI: 10.1109/IRPS.1984.362023
D. J. Burns, Mark T. Pronobis, C. Eldering, Robert J. Hillman
A new device analysis technique is discussed which may prove useful in characterizing critical timing paths and analyzing timing related failure modes in high clock rate VLSI circuits. A focussed laser is used to inject localized photocurrent at the drain of a single transistor as the device is tested. The resulting effects on circuit performance have been studied and it is shown that individual circuit path propagation delays can be increased in this manner. To assign a relative value to a measurement, the operating frequency, power supply voltage or injected photocurrent level can be varied with the others fixed until the device just fails. Models, circuit simulations and experimental results obtained using this technique on a simple gate and results measured on CMOS microprocessors are given in this paper. Possible applications of the technique beyond the analysis of frequency sensitive failures include experimentally locating performance limiting timing paths in a circuit and assessing a circuit's sensitivity to process or failure mechanism induced drifts in device parameters which affect timing.
讨论了一种新的器件分析技术,该技术可用于高时钟速率VLSI电路中关键时序路径的表征和时序相关失效模式的分析。在测试器件时,使用聚焦激光器在单个晶体管的漏极注入局部光电流。研究了由此产生的对电路性能的影响,并表明可以通过这种方式增加单个电路路径的传播延迟。为了给测量值赋一个相对值,可以改变工作频率、电源电压或注入的光电流水平,而其他固定不变,直到设备失效。文中给出了该技术在简单栅极上的模型、电路仿真和实验结果,以及在CMOS微处理器上的测量结果。除了分析频率敏感故障之外,该技术的可能应用包括在电路中实验定位性能限制时序路径,以及评估电路对影响时序的工艺或故障机制引起的器件参数漂移的灵敏度。
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引用次数: 12
期刊
22nd International Reliability Physics Symposium
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